17a2aeb91SLi Yang// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 27a5d7347SHarninder Rai/* 37a5d7347SHarninder Rai * Device Tree Include file for NXP Layerscape-1088A family SoC. 47a5d7347SHarninder Rai * 5f7d48ffcSWasim Khan * Copyright 2017-2020 NXP 67a5d7347SHarninder Rai * 77a5d7347SHarninder Rai * Harninder Rai <harninder.rai@nxp.com> 87a5d7347SHarninder Rai * 97a5d7347SHarninder Rai */ 107a5d7347SHarninder Rai#include <dt-bindings/interrupt-controller/arm-gic.h> 11e4990b44SYuantian Tang#include <dt-bindings/thermal/thermal.h> 127a5d7347SHarninder Rai 137a5d7347SHarninder Rai/ { 147a5d7347SHarninder Rai compatible = "fsl,ls1088a"; 157a5d7347SHarninder Rai interrupt-parent = <&gic>; 167a5d7347SHarninder Rai #address-cells = <2>; 177a5d7347SHarninder Rai #size-cells = <2>; 187a5d7347SHarninder Rai 191e09dec9SHoria Geantă aliases { 201e09dec9SHoria Geantă crypto = &crypto; 21f4fe3a86SBiwen Li rtc1 = &ftm_alarm0; 221e09dec9SHoria Geantă }; 231e09dec9SHoria Geantă 247a5d7347SHarninder Rai cpus { 257a5d7347SHarninder Rai #address-cells = <1>; 267a5d7347SHarninder Rai #size-cells = <0>; 277a5d7347SHarninder Rai 287a5d7347SHarninder Rai /* We have 2 clusters having 4 Cortex-A53 cores each */ 297a5d7347SHarninder Rai cpu0: cpu@0 { 307a5d7347SHarninder Rai device_type = "cpu"; 317a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 327a5d7347SHarninder Rai reg = <0x0>; 337a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 345334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 35e4990b44SYuantian Tang #cooling-cells = <2>; 367a5d7347SHarninder Rai }; 377a5d7347SHarninder Rai 387a5d7347SHarninder Rai cpu1: cpu@1 { 397a5d7347SHarninder Rai device_type = "cpu"; 407a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 417a5d7347SHarninder Rai reg = <0x1>; 427a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 435334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 44346f5976SViresh Kumar #cooling-cells = <2>; 457a5d7347SHarninder Rai }; 467a5d7347SHarninder Rai 477a5d7347SHarninder Rai cpu2: cpu@2 { 487a5d7347SHarninder Rai device_type = "cpu"; 497a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 507a5d7347SHarninder Rai reg = <0x2>; 517a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 525334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 53346f5976SViresh Kumar #cooling-cells = <2>; 547a5d7347SHarninder Rai }; 557a5d7347SHarninder Rai 567a5d7347SHarninder Rai cpu3: cpu@3 { 577a5d7347SHarninder Rai device_type = "cpu"; 587a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 597a5d7347SHarninder Rai reg = <0x3>; 607a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 615334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 62346f5976SViresh Kumar #cooling-cells = <2>; 637a5d7347SHarninder Rai }; 647a5d7347SHarninder Rai 657a5d7347SHarninder Rai cpu4: cpu@100 { 667a5d7347SHarninder Rai device_type = "cpu"; 677a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 687a5d7347SHarninder Rai reg = <0x100>; 697a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 705334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 71e4990b44SYuantian Tang #cooling-cells = <2>; 727a5d7347SHarninder Rai }; 737a5d7347SHarninder Rai 747a5d7347SHarninder Rai cpu5: cpu@101 { 757a5d7347SHarninder Rai device_type = "cpu"; 767a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 777a5d7347SHarninder Rai reg = <0x101>; 787a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 795334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 80346f5976SViresh Kumar #cooling-cells = <2>; 817a5d7347SHarninder Rai }; 827a5d7347SHarninder Rai 837a5d7347SHarninder Rai cpu6: cpu@102 { 847a5d7347SHarninder Rai device_type = "cpu"; 857a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 867a5d7347SHarninder Rai reg = <0x102>; 877a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 885334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 89346f5976SViresh Kumar #cooling-cells = <2>; 907a5d7347SHarninder Rai }; 917a5d7347SHarninder Rai 927a5d7347SHarninder Rai cpu7: cpu@103 { 937a5d7347SHarninder Rai device_type = "cpu"; 947a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 957a5d7347SHarninder Rai reg = <0x103>; 967a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 975334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 98346f5976SViresh Kumar #cooling-cells = <2>; 995334e1a2SYuantian Tang }; 1005334e1a2SYuantian Tang 1015334e1a2SYuantian Tang CPU_PH20: cpu-ph20 { 1025334e1a2SYuantian Tang compatible = "arm,idle-state"; 1035334e1a2SYuantian Tang idle-state-name = "PH20"; 10469ea29b0SYuantian Tang arm,psci-suspend-param = <0x0>; 1055334e1a2SYuantian Tang entry-latency-us = <1000>; 1065334e1a2SYuantian Tang exit-latency-us = <1000>; 1075334e1a2SYuantian Tang min-residency-us = <3000>; 1087a5d7347SHarninder Rai }; 1097a5d7347SHarninder Rai }; 1107a5d7347SHarninder Rai 1117a5d7347SHarninder Rai gic: interrupt-controller@6000000 { 1127a5d7347SHarninder Rai compatible = "arm,gic-v3"; 1137a5d7347SHarninder Rai #interrupt-cells = <3>; 1147a5d7347SHarninder Rai interrupt-controller; 1157a5d7347SHarninder Rai reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1167a5d7347SHarninder Rai <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 1177a5d7347SHarninder Rai <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 1187a5d7347SHarninder Rai <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 1197a5d7347SHarninder Rai <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 1207a5d7347SHarninder Rai interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 121a3bbf4c5SHou Zhiqiang #address-cells = <2>; 122a3bbf4c5SHou Zhiqiang #size-cells = <2>; 123a3bbf4c5SHou Zhiqiang ranges; 124a3bbf4c5SHou Zhiqiang 125a3bbf4c5SHou Zhiqiang its: gic-its@6020000 { 126a3bbf4c5SHou Zhiqiang compatible = "arm,gic-v3-its"; 127a3bbf4c5SHou Zhiqiang msi-controller; 128a3bbf4c5SHou Zhiqiang reg = <0x0 0x6020000 0 0x20000>; 129a3bbf4c5SHou Zhiqiang }; 1307a5d7347SHarninder Rai }; 1317a5d7347SHarninder Rai 13285530a7aSFabio Estevam thermal-zones { 133acfa13abSYuantian Tang core-cluster { 13485530a7aSFabio Estevam polling-delay-passive = <1000>; 13585530a7aSFabio Estevam polling-delay = <5000>; 13685530a7aSFabio Estevam thermal-sensors = <&tmu 0>; 13785530a7aSFabio Estevam 13885530a7aSFabio Estevam trips { 139acfa13abSYuantian Tang core_cluster_alert: core-cluster-alert { 14085530a7aSFabio Estevam temperature = <85000>; 14185530a7aSFabio Estevam hysteresis = <2000>; 14285530a7aSFabio Estevam type = "passive"; 14385530a7aSFabio Estevam }; 14485530a7aSFabio Estevam 145acfa13abSYuantian Tang core-cluster-crit { 14685530a7aSFabio Estevam temperature = <95000>; 14785530a7aSFabio Estevam hysteresis = <2000>; 14885530a7aSFabio Estevam type = "critical"; 14985530a7aSFabio Estevam }; 15085530a7aSFabio Estevam }; 15185530a7aSFabio Estevam 15285530a7aSFabio Estevam cooling-maps { 15385530a7aSFabio Estevam map0 { 154acfa13abSYuantian Tang trip = <&core_cluster_alert>; 15585530a7aSFabio Estevam cooling-device = 156c9a1f243SViresh Kumar <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 157c9a1f243SViresh Kumar <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 158c9a1f243SViresh Kumar <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159c9a1f243SViresh Kumar <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 160c9a1f243SViresh Kumar <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161c9a1f243SViresh Kumar <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 162c9a1f243SViresh Kumar <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 163c9a1f243SViresh Kumar <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 16485530a7aSFabio Estevam }; 16585530a7aSFabio Estevam }; 16685530a7aSFabio Estevam }; 167acfa13abSYuantian Tang 168acfa13abSYuantian Tang soc { 169acfa13abSYuantian Tang polling-delay-passive = <1000>; 170acfa13abSYuantian Tang polling-delay = <5000>; 171acfa13abSYuantian Tang thermal-sensors = <&tmu 1>; 172acfa13abSYuantian Tang 173acfa13abSYuantian Tang trips { 174acfa13abSYuantian Tang soc-crit { 175acfa13abSYuantian Tang temperature = <95000>; 176acfa13abSYuantian Tang hysteresis = <2000>; 177acfa13abSYuantian Tang type = "critical"; 178acfa13abSYuantian Tang }; 179acfa13abSYuantian Tang }; 180acfa13abSYuantian Tang }; 18185530a7aSFabio Estevam }; 18285530a7aSFabio Estevam 1837a5d7347SHarninder Rai timer { 1847a5d7347SHarninder Rai compatible = "arm,armv8-timer"; 1857a5d7347SHarninder Rai interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 1867a5d7347SHarninder Rai <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 1877a5d7347SHarninder Rai <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 1887a5d7347SHarninder Rai <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 1897a5d7347SHarninder Rai }; 1907a5d7347SHarninder Rai 1915334e1a2SYuantian Tang psci { 1925334e1a2SYuantian Tang compatible = "arm,psci-0.2"; 1935334e1a2SYuantian Tang method = "smc"; 1945334e1a2SYuantian Tang }; 1955334e1a2SYuantian Tang 1967a5d7347SHarninder Rai sysclk: sysclk { 1977a5d7347SHarninder Rai compatible = "fixed-clock"; 1987a5d7347SHarninder Rai #clock-cells = <0>; 1997a5d7347SHarninder Rai clock-frequency = <100000000>; 2007a5d7347SHarninder Rai clock-output-names = "sysclk"; 2017a5d7347SHarninder Rai }; 2027a5d7347SHarninder Rai 2037a5d7347SHarninder Rai soc { 2047a5d7347SHarninder Rai compatible = "simple-bus"; 2057a5d7347SHarninder Rai #address-cells = <2>; 2067a5d7347SHarninder Rai #size-cells = <2>; 2077a5d7347SHarninder Rai ranges; 208d9a71ef0SIoana Ciocoi Radulescu dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 2097a5d7347SHarninder Rai 2107a5d7347SHarninder Rai clockgen: clocking@1300000 { 2117a5d7347SHarninder Rai compatible = "fsl,ls1088a-clockgen"; 2127a5d7347SHarninder Rai reg = <0 0x1300000 0 0xa0000>; 2137a5d7347SHarninder Rai #clock-cells = <2>; 2147a5d7347SHarninder Rai clocks = <&sysclk>; 2157a5d7347SHarninder Rai }; 2167a5d7347SHarninder Rai 21788b64bb1SAshish Kumar dcfg: dcfg@1e00000 { 21888b64bb1SAshish Kumar compatible = "fsl,ls1088a-dcfg", "syscon"; 21988b64bb1SAshish Kumar reg = <0x0 0x1e00000 0x0 0x10000>; 22088b64bb1SAshish Kumar little-endian; 22188b64bb1SAshish Kumar }; 22288b64bb1SAshish Kumar 223e4990b44SYuantian Tang tmu: tmu@1f80000 { 224e4990b44SYuantian Tang compatible = "fsl,qoriq-tmu"; 225e4990b44SYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 226e4990b44SYuantian Tang interrupts = <0 23 0x4>; 227acfa13abSYuantian Tang fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 228e4990b44SYuantian Tang fsl,tmu-calibration = 229e4990b44SYuantian Tang /* Calibration data group 1 */ 230acfa13abSYuantian Tang <0x00000000 0x00000023 231acfa13abSYuantian Tang 0x00000001 0x0000002a 232acfa13abSYuantian Tang 0x00000002 0x00000030 233acfa13abSYuantian Tang 0x00000003 0x00000037 234acfa13abSYuantian Tang 0x00000004 0x0000003d 235acfa13abSYuantian Tang 0x00000005 0x00000044 236acfa13abSYuantian Tang 0x00000006 0x0000004a 237acfa13abSYuantian Tang 0x00000007 0x00000051 238acfa13abSYuantian Tang 0x00000008 0x00000057 239acfa13abSYuantian Tang 0x00000009 0x0000005e 240acfa13abSYuantian Tang 0x0000000a 0x00000064 241acfa13abSYuantian Tang 0x0000000b 0x0000006b 242e4990b44SYuantian Tang /* Calibration data group 2 */ 243acfa13abSYuantian Tang 0x00010000 0x00000022 244acfa13abSYuantian Tang 0x00010001 0x0000002a 245acfa13abSYuantian Tang 0x00010002 0x00000032 246acfa13abSYuantian Tang 0x00010003 0x0000003a 247acfa13abSYuantian Tang 0x00010004 0x00000042 248acfa13abSYuantian Tang 0x00010005 0x0000004a 249acfa13abSYuantian Tang 0x00010006 0x00000052 250acfa13abSYuantian Tang 0x00010007 0x0000005a 251acfa13abSYuantian Tang 0x00010008 0x00000062 252acfa13abSYuantian Tang 0x00010009 0x0000006a 253e4990b44SYuantian Tang /* Calibration data group 3 */ 254acfa13abSYuantian Tang 0x00020000 0x00000021 255acfa13abSYuantian Tang 0x00020001 0x0000002b 256acfa13abSYuantian Tang 0x00020002 0x00000035 257acfa13abSYuantian Tang 0x00020003 0x00000040 258acfa13abSYuantian Tang 0x00020004 0x0000004a 259acfa13abSYuantian Tang 0x00020005 0x00000054 260acfa13abSYuantian Tang 0x00020006 0x0000005e 261e4990b44SYuantian Tang /* Calibration data group 4 */ 262acfa13abSYuantian Tang 0x00030000 0x00000010 263acfa13abSYuantian Tang 0x00030001 0x0000001c 264acfa13abSYuantian Tang 0x00030002 0x00000027 265acfa13abSYuantian Tang 0x00030003 0x00000032 266acfa13abSYuantian Tang 0x00030004 0x0000003e 267acfa13abSYuantian Tang 0x00030005 0x00000049 268acfa13abSYuantian Tang 0x00030006 0x00000054 269acfa13abSYuantian Tang 0x00030007 0x00000060>; 270e4990b44SYuantian Tang little-endian; 271e4990b44SYuantian Tang #thermal-sensor-cells = <1>; 272e4990b44SYuantian Tang }; 273e4990b44SYuantian Tang 27460ca9248SChuanhua Han dspi: spi@2100000 { 27560ca9248SChuanhua Han compatible = "fsl,ls1088a-dspi", 27660ca9248SChuanhua Han "fsl,ls1021a-v1.0-dspi"; 27760ca9248SChuanhua Han #address-cells = <1>; 27860ca9248SChuanhua Han #size-cells = <0>; 27960ca9248SChuanhua Han reg = <0x0 0x2100000 0x0 0x10000>; 28060ca9248SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 28160ca9248SChuanhua Han clock-names = "dspi"; 28260ca9248SChuanhua Han clocks = <&clockgen 4 1>; 28360ca9248SChuanhua Han spi-num-chipselects = <6>; 28460ca9248SChuanhua Han status = "disabled"; 28560ca9248SChuanhua Han }; 28660ca9248SChuanhua Han 2877a5d7347SHarninder Rai duart0: serial@21c0500 { 2887a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 2897a5d7347SHarninder Rai reg = <0x0 0x21c0500 0x0 0x100>; 2907a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2917a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 2927a5d7347SHarninder Rai status = "disabled"; 2937a5d7347SHarninder Rai }; 2947a5d7347SHarninder Rai 2957a5d7347SHarninder Rai duart1: serial@21c0600 { 2967a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 2977a5d7347SHarninder Rai reg = <0x0 0x21c0600 0x0 0x100>; 2987a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2997a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 3007a5d7347SHarninder Rai status = "disabled"; 3017a5d7347SHarninder Rai }; 3027a5d7347SHarninder Rai 3037a5d7347SHarninder Rai gpio0: gpio@2300000 { 304afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3057a5d7347SHarninder Rai reg = <0x0 0x2300000 0x0 0x10000>; 3067a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 30766f1f580SChuanhua Han little-endian; 3087a5d7347SHarninder Rai gpio-controller; 3097a5d7347SHarninder Rai #gpio-cells = <2>; 3107a5d7347SHarninder Rai interrupt-controller; 3117a5d7347SHarninder Rai #interrupt-cells = <2>; 3127a5d7347SHarninder Rai }; 3137a5d7347SHarninder Rai 3147a5d7347SHarninder Rai gpio1: gpio@2310000 { 315afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3167a5d7347SHarninder Rai reg = <0x0 0x2310000 0x0 0x10000>; 3177a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 31866f1f580SChuanhua Han little-endian; 3197a5d7347SHarninder Rai gpio-controller; 3207a5d7347SHarninder Rai #gpio-cells = <2>; 3217a5d7347SHarninder Rai interrupt-controller; 3227a5d7347SHarninder Rai #interrupt-cells = <2>; 3237a5d7347SHarninder Rai }; 3247a5d7347SHarninder Rai 3257a5d7347SHarninder Rai gpio2: gpio@2320000 { 326afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3277a5d7347SHarninder Rai reg = <0x0 0x2320000 0x0 0x10000>; 3287a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 32966f1f580SChuanhua Han little-endian; 3307a5d7347SHarninder Rai gpio-controller; 3317a5d7347SHarninder Rai #gpio-cells = <2>; 3327a5d7347SHarninder Rai interrupt-controller; 3337a5d7347SHarninder Rai #interrupt-cells = <2>; 3347a5d7347SHarninder Rai }; 3357a5d7347SHarninder Rai 3367a5d7347SHarninder Rai gpio3: gpio@2330000 { 337afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3387a5d7347SHarninder Rai reg = <0x0 0x2330000 0x0 0x10000>; 3397a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 34066f1f580SChuanhua Han little-endian; 3417a5d7347SHarninder Rai gpio-controller; 3427a5d7347SHarninder Rai #gpio-cells = <2>; 3437a5d7347SHarninder Rai interrupt-controller; 3447a5d7347SHarninder Rai #interrupt-cells = <2>; 3457a5d7347SHarninder Rai }; 3467a5d7347SHarninder Rai 3477a5d7347SHarninder Rai ifc: ifc@2240000 { 3487a5d7347SHarninder Rai compatible = "fsl,ifc", "simple-bus"; 3497a5d7347SHarninder Rai reg = <0x0 0x2240000 0x0 0x20000>; 3507a5d7347SHarninder Rai interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 3517a5d7347SHarninder Rai little-endian; 3527a5d7347SHarninder Rai #address-cells = <2>; 3537a5d7347SHarninder Rai #size-cells = <1>; 3547a5d7347SHarninder Rai status = "disabled"; 3557a5d7347SHarninder Rai }; 3567a5d7347SHarninder Rai 3577a5d7347SHarninder Rai i2c0: i2c@2000000 { 3587a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3597a5d7347SHarninder Rai #address-cells = <1>; 3607a5d7347SHarninder Rai #size-cells = <0>; 3617a5d7347SHarninder Rai reg = <0x0 0x2000000 0x0 0x10000>; 3627a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 36386c457e3SChuanhua Han clocks = <&clockgen 4 7>; 3647a5d7347SHarninder Rai status = "disabled"; 3657a5d7347SHarninder Rai }; 3667a5d7347SHarninder Rai 3677a5d7347SHarninder Rai i2c1: i2c@2010000 { 3687a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3697a5d7347SHarninder Rai #address-cells = <1>; 3707a5d7347SHarninder Rai #size-cells = <0>; 3717a5d7347SHarninder Rai reg = <0x0 0x2010000 0x0 0x10000>; 3727a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 37386c457e3SChuanhua Han clocks = <&clockgen 4 7>; 3747a5d7347SHarninder Rai status = "disabled"; 3757a5d7347SHarninder Rai }; 3767a5d7347SHarninder Rai 3777a5d7347SHarninder Rai i2c2: i2c@2020000 { 3787a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3797a5d7347SHarninder Rai #address-cells = <1>; 3807a5d7347SHarninder Rai #size-cells = <0>; 3817a5d7347SHarninder Rai reg = <0x0 0x2020000 0x0 0x10000>; 3827a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 38386c457e3SChuanhua Han clocks = <&clockgen 4 7>; 3847a5d7347SHarninder Rai status = "disabled"; 3857a5d7347SHarninder Rai }; 3867a5d7347SHarninder Rai 3877a5d7347SHarninder Rai i2c3: i2c@2030000 { 3887a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3897a5d7347SHarninder Rai #address-cells = <1>; 3907a5d7347SHarninder Rai #size-cells = <0>; 3917a5d7347SHarninder Rai reg = <0x0 0x2030000 0x0 0x10000>; 3927a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 39386c457e3SChuanhua Han clocks = <&clockgen 4 7>; 3947a5d7347SHarninder Rai status = "disabled"; 3957a5d7347SHarninder Rai }; 3967a5d7347SHarninder Rai 39768a2b3fdSAshish Kumar qspi: spi@20c0000 { 39868a2b3fdSAshish Kumar compatible = "fsl,ls2080a-qspi"; 39968a2b3fdSAshish Kumar #address-cells = <1>; 40068a2b3fdSAshish Kumar #size-cells = <0>; 40168a2b3fdSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 40268a2b3fdSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 40368a2b3fdSAshish Kumar reg-names = "QuadSPI", "QuadSPI-memory"; 40468a2b3fdSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 40568a2b3fdSAshish Kumar clock-names = "qspi_en", "qspi"; 40668a2b3fdSAshish Kumar clocks = <&clockgen 4 3>, <&clockgen 4 3>; 40768a2b3fdSAshish Kumar status = "disabled"; 40868a2b3fdSAshish Kumar }; 40968a2b3fdSAshish Kumar 410e56ae178SYangbo Lu esdhc: esdhc@2140000 { 411e56ae178SYangbo Lu compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 412e56ae178SYangbo Lu reg = <0x0 0x2140000 0x0 0x10000>; 413e56ae178SYangbo Lu interrupts = <0 28 0x4>; /* Level high type */ 414e56ae178SYangbo Lu clock-frequency = <0>; 4154671f9cfSYangbo Lu clocks = <&clockgen 2 1>; 416e56ae178SYangbo Lu voltage-ranges = <1800 1800 3300 3300>; 417e56ae178SYangbo Lu sdhci,auto-cmd12; 418e56ae178SYangbo Lu little-endian; 419e56ae178SYangbo Lu bus-width = <4>; 420e56ae178SYangbo Lu status = "disabled"; 421e56ae178SYangbo Lu }; 422e56ae178SYangbo Lu 423da244504SSerge Semin usb0: usb@3100000 { 424df063a1fSyinbo.zhu compatible = "snps,dwc3"; 425df063a1fSyinbo.zhu reg = <0x0 0x3100000 0x0 0x10000>; 426df063a1fSyinbo.zhu interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 427df063a1fSyinbo.zhu dr_mode = "host"; 428df063a1fSyinbo.zhu snps,quirk-frame-length-adjustment = <0x20>; 429df063a1fSyinbo.zhu snps,dis_rxdet_inp3_quirk; 4301000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 431df063a1fSyinbo.zhu status = "disabled"; 432df063a1fSyinbo.zhu }; 433df063a1fSyinbo.zhu 434da244504SSerge Semin usb1: usb@3110000 { 435df063a1fSyinbo.zhu compatible = "snps,dwc3"; 436df063a1fSyinbo.zhu reg = <0x0 0x3110000 0x0 0x10000>; 437df063a1fSyinbo.zhu interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 438df063a1fSyinbo.zhu dr_mode = "host"; 439df063a1fSyinbo.zhu snps,quirk-frame-length-adjustment = <0x20>; 440df063a1fSyinbo.zhu snps,dis_rxdet_inp3_quirk; 441df063a1fSyinbo.zhu status = "disabled"; 442df063a1fSyinbo.zhu }; 443df063a1fSyinbo.zhu 4447a5d7347SHarninder Rai sata: sata@3200000 { 445375b6755SYuantian Tang compatible = "fsl,ls1088a-ahci"; 44683d0c697SYuantian Tang reg = <0x0 0x3200000 0x0 0x10000>, 447375b6755SYuantian Tang <0x7 0x100520 0x0 0x4>; 44883d0c697SYuantian Tang reg-names = "ahci", "sata-ecc"; 4497a5d7347SHarninder Rai interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 4507a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 45183d0c697SYuantian Tang dma-coherent; 4527a5d7347SHarninder Rai status = "disabled"; 4537a5d7347SHarninder Rai }; 4541e09dec9SHoria Geantă 4551e09dec9SHoria Geantă crypto: crypto@8000000 { 4561e09dec9SHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 4571e09dec9SHoria Geantă fsl,sec-era = <8>; 4581e09dec9SHoria Geantă #address-cells = <1>; 4591e09dec9SHoria Geantă #size-cells = <1>; 4601e09dec9SHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 4611e09dec9SHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 4621e09dec9SHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 4631e09dec9SHoria Geantă dma-coherent; 4641e09dec9SHoria Geantă 4651e09dec9SHoria Geantă sec_jr0: jr@10000 { 4661e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4671e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4681e09dec9SHoria Geantă reg = <0x10000 0x10000>; 4691e09dec9SHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4701e09dec9SHoria Geantă }; 4711e09dec9SHoria Geantă 4721e09dec9SHoria Geantă sec_jr1: jr@20000 { 4731e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4741e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4751e09dec9SHoria Geantă reg = <0x20000 0x10000>; 4761e09dec9SHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 4771e09dec9SHoria Geantă }; 4781e09dec9SHoria Geantă 4791e09dec9SHoria Geantă sec_jr2: jr@30000 { 4801e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4811e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4821e09dec9SHoria Geantă reg = <0x30000 0x10000>; 4831e09dec9SHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 4841e09dec9SHoria Geantă }; 4851e09dec9SHoria Geantă 4861e09dec9SHoria Geantă sec_jr3: jr@40000 { 4871e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4881e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4891e09dec9SHoria Geantă reg = <0x40000 0x10000>; 4901e09dec9SHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 4911e09dec9SHoria Geantă }; 4921e09dec9SHoria Geantă }; 493647911c8SHou Zhiqiang 494f7d48ffcSWasim Khan pcie1: pcie@3400000 { 4951fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 496647911c8SHou Zhiqiang reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 497647911c8SHou Zhiqiang 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 498647911c8SHou Zhiqiang reg-names = "regs", "config"; 499647911c8SHou Zhiqiang interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 500647911c8SHou Zhiqiang interrupt-names = "aer"; 501647911c8SHou Zhiqiang #address-cells = <3>; 502647911c8SHou Zhiqiang #size-cells = <2>; 503647911c8SHou Zhiqiang device_type = "pci"; 504647911c8SHou Zhiqiang dma-coherent; 505881e90d2SHou Zhiqiang num-viewport = <256>; 506647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 507647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 508647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 509647911c8SHou Zhiqiang msi-parent = <&its>; 510647911c8SHou Zhiqiang #interrupt-cells = <1>; 511647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 512647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 513647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 514647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 515647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 516f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 517aa2aa888SBao Xiaowei status = "disabled"; 518647911c8SHou Zhiqiang }; 519647911c8SHou Zhiqiang 520f7d48ffcSWasim Khan pcie2: pcie@3500000 { 5211fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 522647911c8SHou Zhiqiang reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 523647911c8SHou Zhiqiang 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 524647911c8SHou Zhiqiang reg-names = "regs", "config"; 525647911c8SHou Zhiqiang interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 526647911c8SHou Zhiqiang interrupt-names = "aer"; 527647911c8SHou Zhiqiang #address-cells = <3>; 528647911c8SHou Zhiqiang #size-cells = <2>; 529647911c8SHou Zhiqiang device_type = "pci"; 530647911c8SHou Zhiqiang dma-coherent; 531881e90d2SHou Zhiqiang num-viewport = <6>; 532647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 533647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 534647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 535647911c8SHou Zhiqiang msi-parent = <&its>; 536647911c8SHou Zhiqiang #interrupt-cells = <1>; 537647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 538647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 539647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 540647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 541647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 542f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 543aa2aa888SBao Xiaowei status = "disabled"; 544647911c8SHou Zhiqiang }; 545647911c8SHou Zhiqiang 546f7d48ffcSWasim Khan pcie3: pcie@3600000 { 5471fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 548647911c8SHou Zhiqiang reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 549647911c8SHou Zhiqiang 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 550647911c8SHou Zhiqiang reg-names = "regs", "config"; 551647911c8SHou Zhiqiang interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 552647911c8SHou Zhiqiang interrupt-names = "aer"; 553647911c8SHou Zhiqiang #address-cells = <3>; 554647911c8SHou Zhiqiang #size-cells = <2>; 555647911c8SHou Zhiqiang device_type = "pci"; 556647911c8SHou Zhiqiang dma-coherent; 557881e90d2SHou Zhiqiang num-viewport = <6>; 558647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 559647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 560647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 561647911c8SHou Zhiqiang msi-parent = <&its>; 562647911c8SHou Zhiqiang #interrupt-cells = <1>; 563647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 564647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 565647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 566647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 567647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 568f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 569aa2aa888SBao Xiaowei status = "disabled"; 570647911c8SHou Zhiqiang }; 571cc223282SZhang Ying-22455 57283c58a55SNipun Gupta smmu: iommu@5000000 { 57383c58a55SNipun Gupta compatible = "arm,mmu-500"; 57483c58a55SNipun Gupta reg = <0 0x5000000 0 0x800000>; 57583c58a55SNipun Gupta #iommu-cells = <1>; 57683c58a55SNipun Gupta stream-match-mask = <0x7C00>; 57783c58a55SNipun Gupta #global-interrupts = <12>; 57883c58a55SNipun Gupta // global secure fault 57983c58a55SNipun Gupta interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 58083c58a55SNipun Gupta // combined secure 58183c58a55SNipun Gupta <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 58283c58a55SNipun Gupta // global non-secure fault 58383c58a55SNipun Gupta <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 58483c58a55SNipun Gupta // combined non-secure 58583c58a55SNipun Gupta <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 58683c58a55SNipun Gupta // performance counter interrupts 0-7 58783c58a55SNipun Gupta <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 58883c58a55SNipun Gupta <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 58983c58a55SNipun Gupta <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 59083c58a55SNipun Gupta <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 59183c58a55SNipun Gupta <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 59283c58a55SNipun Gupta <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 59383c58a55SNipun Gupta <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 59483c58a55SNipun Gupta <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 59583c58a55SNipun Gupta // per context interrupt, 64 interrupts 59683c58a55SNipun Gupta <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 59783c58a55SNipun Gupta <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 59883c58a55SNipun Gupta <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 59983c58a55SNipun Gupta <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 60083c58a55SNipun Gupta <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 60183c58a55SNipun Gupta <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 60283c58a55SNipun Gupta <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 60383c58a55SNipun Gupta <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 60483c58a55SNipun Gupta <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 60583c58a55SNipun Gupta <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 60683c58a55SNipun Gupta <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 60783c58a55SNipun Gupta <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 60883c58a55SNipun Gupta <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 60983c58a55SNipun Gupta <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 61083c58a55SNipun Gupta <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 61183c58a55SNipun Gupta <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 61283c58a55SNipun Gupta <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 61383c58a55SNipun Gupta <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 61483c58a55SNipun Gupta <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 61583c58a55SNipun Gupta <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 61683c58a55SNipun Gupta <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 61783c58a55SNipun Gupta <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 61883c58a55SNipun Gupta <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 61983c58a55SNipun Gupta <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 62083c58a55SNipun Gupta <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 62183c58a55SNipun Gupta <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 62283c58a55SNipun Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 62383c58a55SNipun Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 62483c58a55SNipun Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 62583c58a55SNipun Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 62683c58a55SNipun Gupta <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 62783c58a55SNipun Gupta <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 62883c58a55SNipun Gupta <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 62983c58a55SNipun Gupta <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 63083c58a55SNipun Gupta <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 63183c58a55SNipun Gupta <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 63283c58a55SNipun Gupta <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 63383c58a55SNipun Gupta <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 63483c58a55SNipun Gupta <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 63583c58a55SNipun Gupta <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 63683c58a55SNipun Gupta <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 63783c58a55SNipun Gupta <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 63883c58a55SNipun Gupta <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 63983c58a55SNipun Gupta <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 64083c58a55SNipun Gupta <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 64183c58a55SNipun Gupta <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 64283c58a55SNipun Gupta <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 64383c58a55SNipun Gupta <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 64483c58a55SNipun Gupta <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 64583c58a55SNipun Gupta <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 64683c58a55SNipun Gupta <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 64783c58a55SNipun Gupta <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 64883c58a55SNipun Gupta <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 64983c58a55SNipun Gupta <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 65083c58a55SNipun Gupta <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 65183c58a55SNipun Gupta <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 65283c58a55SNipun Gupta <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 65383c58a55SNipun Gupta <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 65483c58a55SNipun Gupta <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 65583c58a55SNipun Gupta <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 65683c58a55SNipun Gupta <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 65783c58a55SNipun Gupta <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 65883c58a55SNipun Gupta <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 65983c58a55SNipun Gupta <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 66083c58a55SNipun Gupta }; 66183c58a55SNipun Gupta 662546d92d3SIoana Ciornei console@8340020 { 663546d92d3SIoana Ciornei compatible = "fsl,dpaa2-console"; 664546d92d3SIoana Ciornei reg = <0x00000000 0x08340020 0 0x2>; 665546d92d3SIoana Ciornei }; 666546d92d3SIoana Ciornei 667fe844f19SYangbo Lu ptp-timer@8b95000 { 668fe844f19SYangbo Lu compatible = "fsl,dpaa2-ptp"; 669fe844f19SYangbo Lu reg = <0x0 0x8b95000 0x0 0x100>; 670fe844f19SYangbo Lu clocks = <&clockgen 4 0>; 671fe844f19SYangbo Lu little-endian; 672fe844f19SYangbo Lu fsl,extts-fifo; 673fe844f19SYangbo Lu }; 674fe844f19SYangbo Lu 675bbe75af7SIoana Ciornei emdio1: mdio@8b96000 { 676bbe75af7SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 677bbe75af7SIoana Ciornei reg = <0x0 0x8b96000 0x0 0x1000>; 678bbe75af7SIoana Ciornei little-endian; 679bbe75af7SIoana Ciornei #address-cells = <1>; 680bbe75af7SIoana Ciornei #size-cells = <0>; 681bbe75af7SIoana Ciornei status = "disabled"; 682bbe75af7SIoana Ciornei }; 683bbe75af7SIoana Ciornei 684bbe75af7SIoana Ciornei emdio2: mdio@8b97000 { 685bbe75af7SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 686bbe75af7SIoana Ciornei reg = <0x0 0x8b97000 0x0 0x1000>; 687bbe75af7SIoana Ciornei little-endian; 688bbe75af7SIoana Ciornei #address-cells = <1>; 689bbe75af7SIoana Ciornei #size-cells = <0>; 690bbe75af7SIoana Ciornei status = "disabled"; 691bbe75af7SIoana Ciornei }; 692bbe75af7SIoana Ciornei 693*379b4f76SIoana Ciornei pcs_mdio2: mdio@8c0b000 { 694*379b4f76SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 695*379b4f76SIoana Ciornei reg = <0x0 0x8c0b000 0x0 0x1000>; 696*379b4f76SIoana Ciornei little-endian; 697*379b4f76SIoana Ciornei #address-cells = <1>; 698*379b4f76SIoana Ciornei #size-cells = <0>; 699*379b4f76SIoana Ciornei status = "disabled"; 700*379b4f76SIoana Ciornei 701*379b4f76SIoana Ciornei pcs2: ethernet-phy@0 { 702*379b4f76SIoana Ciornei reg = <0>; 703*379b4f76SIoana Ciornei }; 704*379b4f76SIoana Ciornei }; 705*379b4f76SIoana Ciornei 70673f034ccSIoana Ciornei pcs_mdio3: mdio@8c0f000 { 70773f034ccSIoana Ciornei compatible = "fsl,fman-memac-mdio"; 70873f034ccSIoana Ciornei reg = <0x0 0x8c0f000 0x0 0x1000>; 70973f034ccSIoana Ciornei little-endian; 71073f034ccSIoana Ciornei #address-cells = <1>; 71173f034ccSIoana Ciornei #size-cells = <0>; 71273f034ccSIoana Ciornei status = "disabled"; 71373f034ccSIoana Ciornei 71473f034ccSIoana Ciornei pcs3_0: ethernet-phy@0 { 71573f034ccSIoana Ciornei reg = <0>; 71673f034ccSIoana Ciornei }; 71773f034ccSIoana Ciornei 71873f034ccSIoana Ciornei pcs3_1: ethernet-phy@1 { 71973f034ccSIoana Ciornei reg = <1>; 72073f034ccSIoana Ciornei }; 72173f034ccSIoana Ciornei 72273f034ccSIoana Ciornei pcs3_2: ethernet-phy@2 { 72373f034ccSIoana Ciornei reg = <2>; 72473f034ccSIoana Ciornei }; 72573f034ccSIoana Ciornei 72673f034ccSIoana Ciornei pcs3_3: ethernet-phy@3 { 72773f034ccSIoana Ciornei reg = <3>; 72873f034ccSIoana Ciornei }; 72973f034ccSIoana Ciornei }; 73073f034ccSIoana Ciornei 73173f034ccSIoana Ciornei pcs_mdio7: mdio@8c1f000 { 73273f034ccSIoana Ciornei compatible = "fsl,fman-memac-mdio"; 73373f034ccSIoana Ciornei reg = <0x0 0x8c1f000 0x0 0x1000>; 73473f034ccSIoana Ciornei little-endian; 73573f034ccSIoana Ciornei #address-cells = <1>; 73673f034ccSIoana Ciornei #size-cells = <0>; 73773f034ccSIoana Ciornei status = "disabled"; 73873f034ccSIoana Ciornei 73973f034ccSIoana Ciornei pcs7_0: ethernet-phy@0 { 74073f034ccSIoana Ciornei reg = <0>; 74173f034ccSIoana Ciornei }; 74273f034ccSIoana Ciornei 74373f034ccSIoana Ciornei pcs7_1: ethernet-phy@1 { 74473f034ccSIoana Ciornei reg = <1>; 74573f034ccSIoana Ciornei }; 74673f034ccSIoana Ciornei 74773f034ccSIoana Ciornei pcs7_2: ethernet-phy@2 { 74873f034ccSIoana Ciornei reg = <2>; 74973f034ccSIoana Ciornei }; 75073f034ccSIoana Ciornei 75173f034ccSIoana Ciornei pcs7_3: ethernet-phy@3 { 75273f034ccSIoana Ciornei reg = <3>; 75373f034ccSIoana Ciornei }; 75473f034ccSIoana Ciornei }; 75573f034ccSIoana Ciornei 756cc223282SZhang Ying-22455 cluster1_core0_watchdog: wdt@c000000 { 757cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 758cc223282SZhang Ying-22455 reg = <0x0 0xc000000 0x0 0x1000>; 759f3cbcbbbSZhao Qiang clocks = <&clockgen 4 15>, <&clockgen 4 15>; 760f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 761cc223282SZhang Ying-22455 }; 762cc223282SZhang Ying-22455 763cc223282SZhang Ying-22455 cluster1_core1_watchdog: wdt@c010000 { 764cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 765cc223282SZhang Ying-22455 reg = <0x0 0xc010000 0x0 0x1000>; 766f3cbcbbbSZhao Qiang clocks = <&clockgen 4 15>, <&clockgen 4 15>; 767f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 768cc223282SZhang Ying-22455 }; 769cc223282SZhang Ying-22455 770cc223282SZhang Ying-22455 cluster1_core2_watchdog: wdt@c020000 { 771cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 772cc223282SZhang Ying-22455 reg = <0x0 0xc020000 0x0 0x1000>; 773f3cbcbbbSZhao Qiang clocks = <&clockgen 4 15>, <&clockgen 4 15>; 774f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 775cc223282SZhang Ying-22455 }; 776cc223282SZhang Ying-22455 777cc223282SZhang Ying-22455 cluster1_core3_watchdog: wdt@c030000 { 778cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 779cc223282SZhang Ying-22455 reg = <0x0 0xc030000 0x0 0x1000>; 780f3cbcbbbSZhao Qiang clocks = <&clockgen 4 15>, <&clockgen 4 15>; 781f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 782cc223282SZhang Ying-22455 }; 783cc223282SZhang Ying-22455 784cc223282SZhang Ying-22455 cluster2_core0_watchdog: wdt@c100000 { 785cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 786cc223282SZhang Ying-22455 reg = <0x0 0xc100000 0x0 0x1000>; 787f3cbcbbbSZhao Qiang clocks = <&clockgen 4 15>, <&clockgen 4 15>; 788f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 789cc223282SZhang Ying-22455 }; 790cc223282SZhang Ying-22455 791cc223282SZhang Ying-22455 cluster2_core1_watchdog: wdt@c110000 { 792cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 793cc223282SZhang Ying-22455 reg = <0x0 0xc110000 0x0 0x1000>; 794f3cbcbbbSZhao Qiang clocks = <&clockgen 4 15>, <&clockgen 4 15>; 795f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 796cc223282SZhang Ying-22455 }; 797cc223282SZhang Ying-22455 798cc223282SZhang Ying-22455 cluster2_core2_watchdog: wdt@c120000 { 799cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 800cc223282SZhang Ying-22455 reg = <0x0 0xc120000 0x0 0x1000>; 801f3cbcbbbSZhao Qiang clocks = <&clockgen 4 15>, <&clockgen 4 15>; 802f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 803cc223282SZhang Ying-22455 }; 804cc223282SZhang Ying-22455 805cc223282SZhang Ying-22455 cluster2_core3_watchdog: wdt@c130000 { 806cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 807cc223282SZhang Ying-22455 reg = <0x0 0xc130000 0x0 0x1000>; 808f3cbcbbbSZhao Qiang clocks = <&clockgen 4 15>, <&clockgen 4 15>; 809f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 810cc223282SZhang Ying-22455 }; 811a2468676SIoana Ciocoi Radulescu 812a2468676SIoana Ciocoi Radulescu fsl_mc: fsl-mc@80c000000 { 813a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc"; 814a2468676SIoana Ciocoi Radulescu reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 815a2468676SIoana Ciocoi Radulescu <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 816a2468676SIoana Ciocoi Radulescu msi-parent = <&its>; 81783c58a55SNipun Gupta iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 818859873fbSNipun Gupta dma-coherent; 819a2468676SIoana Ciocoi Radulescu #address-cells = <3>; 820a2468676SIoana Ciocoi Radulescu #size-cells = <1>; 821a2468676SIoana Ciocoi Radulescu 822a2468676SIoana Ciocoi Radulescu /* 823a2468676SIoana Ciocoi Radulescu * Region type 0x0 - MC portals 824a2468676SIoana Ciocoi Radulescu * Region type 0x1 - QBMAN portals 825a2468676SIoana Ciocoi Radulescu */ 826a2468676SIoana Ciocoi Radulescu ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 827a2468676SIoana Ciocoi Radulescu 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 828a2468676SIoana Ciocoi Radulescu 829a2468676SIoana Ciocoi Radulescu dpmacs { 830a2468676SIoana Ciocoi Radulescu #address-cells = <1>; 831a2468676SIoana Ciocoi Radulescu #size-cells = <0>; 832a2468676SIoana Ciocoi Radulescu 83373f034ccSIoana Ciornei dpmac1: ethernet@1 { 834a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 835a2468676SIoana Ciocoi Radulescu reg = <1>; 836a2468676SIoana Ciocoi Radulescu }; 837a2468676SIoana Ciocoi Radulescu 83873f034ccSIoana Ciornei dpmac2: ethernet@2 { 839a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 840a2468676SIoana Ciocoi Radulescu reg = <2>; 841a2468676SIoana Ciocoi Radulescu }; 842a2468676SIoana Ciocoi Radulescu 84373f034ccSIoana Ciornei dpmac3: ethernet@3 { 844a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 845a2468676SIoana Ciocoi Radulescu reg = <3>; 846a2468676SIoana Ciocoi Radulescu }; 847a2468676SIoana Ciocoi Radulescu 84873f034ccSIoana Ciornei dpmac4: ethernet@4 { 849a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 850a2468676SIoana Ciocoi Radulescu reg = <4>; 851a2468676SIoana Ciocoi Radulescu }; 852a2468676SIoana Ciocoi Radulescu 85373f034ccSIoana Ciornei dpmac5: ethernet@5 { 854a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 855a2468676SIoana Ciocoi Radulescu reg = <5>; 856a2468676SIoana Ciocoi Radulescu }; 857a2468676SIoana Ciocoi Radulescu 85873f034ccSIoana Ciornei dpmac6: ethernet@6 { 859a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 860a2468676SIoana Ciocoi Radulescu reg = <6>; 861a2468676SIoana Ciocoi Radulescu }; 862a2468676SIoana Ciocoi Radulescu 86373f034ccSIoana Ciornei dpmac7: ethernet@7 { 864a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 865a2468676SIoana Ciocoi Radulescu reg = <7>; 866a2468676SIoana Ciocoi Radulescu }; 867a2468676SIoana Ciocoi Radulescu 86873f034ccSIoana Ciornei dpmac8: ethernet@8 { 869a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 870a2468676SIoana Ciocoi Radulescu reg = <8>; 871a2468676SIoana Ciocoi Radulescu }; 872a2468676SIoana Ciocoi Radulescu 87373f034ccSIoana Ciornei dpmac9: ethernet@9 { 874a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 875a2468676SIoana Ciocoi Radulescu reg = <9>; 876a2468676SIoana Ciocoi Radulescu }; 877a2468676SIoana Ciocoi Radulescu 87873f034ccSIoana Ciornei dpmac10: ethernet@a { 879a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 880a2468676SIoana Ciocoi Radulescu reg = <0xa>; 881a2468676SIoana Ciocoi Radulescu }; 882a2468676SIoana Ciocoi Radulescu }; 883a2468676SIoana Ciocoi Radulescu }; 884f4fe3a86SBiwen Li 885f4fe3a86SBiwen Li rcpm: power-controller@1e34040 { 886f4fe3a86SBiwen Li compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; 887f4fe3a86SBiwen Li reg = <0x0 0x1e34040 0x0 0x18>; 888f4fe3a86SBiwen Li #fsl,rcpm-wakeup-cells = <6>; 889f4fe3a86SBiwen Li }; 890f4fe3a86SBiwen Li 891f4fe3a86SBiwen Li ftm_alarm0: timer@2800000 { 892f4fe3a86SBiwen Li compatible = "fsl,ls1088a-ftm-alarm"; 893f4fe3a86SBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 894f4fe3a86SBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; 895f4fe3a86SBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 896f4fe3a86SBiwen Li }; 8977a5d7347SHarninder Rai }; 8987a5d7347SHarninder Rai 89951b29445SSumit Garg firmware { 90051b29445SSumit Garg optee { 90151b29445SSumit Garg compatible = "linaro,optee-tz"; 90251b29445SSumit Garg method = "smc"; 90351b29445SSumit Garg }; 90451b29445SSumit Garg }; 9057a5d7347SHarninder Rai}; 906