1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/gpio/gpio.h> 15 16/ { 17 compatible = "fsl,ls1046a"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 crypto = &crypto; 24 fman0 = &fman0; 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 ethernet4 = &enet4; 30 ethernet5 = &enet5; 31 ethernet6 = &enet6; 32 ethernet7 = &enet7; 33 rtc1 = &ftm_alarm0; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a72"; 43 reg = <0x0>; 44 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 45 next-level-cache = <&l2>; 46 cpu-idle-states = <&CPU_PH20>; 47 #cooling-cells = <2>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a72"; 53 reg = <0x1>; 54 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 55 next-level-cache = <&l2>; 56 cpu-idle-states = <&CPU_PH20>; 57 #cooling-cells = <2>; 58 }; 59 60 cpu2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a72"; 63 reg = <0x2>; 64 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 65 next-level-cache = <&l2>; 66 cpu-idle-states = <&CPU_PH20>; 67 #cooling-cells = <2>; 68 }; 69 70 cpu3: cpu@3 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a72"; 73 reg = <0x3>; 74 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 75 next-level-cache = <&l2>; 76 cpu-idle-states = <&CPU_PH20>; 77 #cooling-cells = <2>; 78 }; 79 80 l2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 }; 85 }; 86 87 idle-states { 88 /* 89 * PSCI node is not added default, U-boot will add missing 90 * parts if it determines to use PSCI. 91 */ 92 entry-method = "psci"; 93 94 CPU_PH20: cpu-ph20 { 95 compatible = "arm,idle-state"; 96 idle-state-name = "PH20"; 97 arm,psci-suspend-param = <0x0>; 98 entry-latency-us = <1000>; 99 exit-latency-us = <1000>; 100 min-residency-us = <3000>; 101 }; 102 }; 103 104 memory@80000000 { 105 device_type = "memory"; 106 /* Real size will be filled by bootloader */ 107 reg = <0x0 0x80000000 0x0 0x0>; 108 }; 109 110 sysclk: sysclk { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <100000000>; 114 clock-output-names = "sysclk"; 115 }; 116 117 reboot { 118 compatible = "syscon-reboot"; 119 regmap = <&dcfg>; 120 offset = <0xb0>; 121 mask = <0x02>; 122 }; 123 124 thermal-zones { 125 ddr-controller { 126 polling-delay-passive = <1000>; 127 polling-delay = <5000>; 128 thermal-sensors = <&tmu 0>; 129 130 trips { 131 ddr-ctrler-alert { 132 temperature = <85000>; 133 hysteresis = <2000>; 134 type = "passive"; 135 }; 136 137 ddr-ctrler-crit { 138 temperature = <95000>; 139 hysteresis = <2000>; 140 type = "critical"; 141 }; 142 }; 143 }; 144 145 serdes { 146 polling-delay-passive = <1000>; 147 polling-delay = <5000>; 148 thermal-sensors = <&tmu 1>; 149 150 trips { 151 serdes-alert { 152 temperature = <85000>; 153 hysteresis = <2000>; 154 type = "passive"; 155 }; 156 157 serdes-crit { 158 temperature = <95000>; 159 hysteresis = <2000>; 160 type = "critical"; 161 }; 162 }; 163 }; 164 165 fman { 166 polling-delay-passive = <1000>; 167 polling-delay = <5000>; 168 thermal-sensors = <&tmu 2>; 169 170 trips { 171 fman-alert { 172 temperature = <85000>; 173 hysteresis = <2000>; 174 type = "passive"; 175 }; 176 177 fman-crit { 178 temperature = <95000>; 179 hysteresis = <2000>; 180 type = "critical"; 181 }; 182 }; 183 }; 184 185 core-cluster { 186 polling-delay-passive = <1000>; 187 polling-delay = <5000>; 188 thermal-sensors = <&tmu 3>; 189 190 trips { 191 core_cluster_alert: core-cluster-alert { 192 temperature = <85000>; 193 hysteresis = <2000>; 194 type = "passive"; 195 }; 196 197 core_cluster_crit: core-cluster-crit { 198 temperature = <95000>; 199 hysteresis = <2000>; 200 type = "critical"; 201 }; 202 }; 203 204 cooling-maps { 205 map0 { 206 trip = <&core_cluster_alert>; 207 cooling-device = 208 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 212 }; 213 }; 214 }; 215 216 sec { 217 polling-delay-passive = <1000>; 218 polling-delay = <5000>; 219 thermal-sensors = <&tmu 4>; 220 221 trips { 222 sec-alert { 223 temperature = <85000>; 224 hysteresis = <2000>; 225 type = "passive"; 226 }; 227 228 sec-crit { 229 temperature = <95000>; 230 hysteresis = <2000>; 231 type = "critical"; 232 }; 233 }; 234 }; 235 }; 236 237 timer { 238 compatible = "arm,armv8-timer"; 239 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 240 IRQ_TYPE_LEVEL_LOW)>, 241 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 242 IRQ_TYPE_LEVEL_LOW)>, 243 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 244 IRQ_TYPE_LEVEL_LOW)>, 245 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 246 IRQ_TYPE_LEVEL_LOW)>; 247 }; 248 249 pmu { 250 compatible = "arm,cortex-a72-pmu"; 251 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 255 interrupt-affinity = <&cpu0>, 256 <&cpu1>, 257 <&cpu2>, 258 <&cpu3>; 259 }; 260 261 gic: interrupt-controller@1400000 { 262 compatible = "arm,gic-400"; 263 #interrupt-cells = <3>; 264 interrupt-controller; 265 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 266 <0x0 0x1420000 0 0x20000>, /* GICC */ 267 <0x0 0x1440000 0 0x20000>, /* GICH */ 268 <0x0 0x1460000 0 0x20000>; /* GICV */ 269 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 270 IRQ_TYPE_LEVEL_LOW)>; 271 }; 272 273 soc: soc { 274 compatible = "simple-bus"; 275 #address-cells = <2>; 276 #size-cells = <2>; 277 ranges; 278 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 279 dma-coherent; 280 281 ddr: memory-controller@1080000 { 282 compatible = "fsl,qoriq-memory-controller"; 283 reg = <0x0 0x1080000 0x0 0x1000>; 284 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 285 big-endian; 286 }; 287 288 ifc: memory-controller@1530000 { 289 compatible = "fsl,ifc"; 290 reg = <0x0 0x1530000 0x0 0x10000>; 291 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 292 status = "disabled"; 293 }; 294 295 qspi: spi@1550000 { 296 compatible = "fsl,ls1021a-qspi"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0x0 0x1550000 0x0 0x10000>, 300 <0x0 0x40000000 0x0 0x10000000>; 301 reg-names = "QuadSPI", "QuadSPI-memory"; 302 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 303 clock-names = "qspi_en", "qspi"; 304 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 305 QORIQ_CLK_PLL_DIV(2)>, 306 <&clockgen QORIQ_CLK_PLATFORM_PLL 307 QORIQ_CLK_PLL_DIV(2)>; 308 status = "disabled"; 309 }; 310 311 esdhc: esdhc@1560000 { 312 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 313 reg = <0x0 0x1560000 0x0 0x10000>; 314 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 316 voltage-ranges = <1800 1800 3300 3300>; 317 sdhci,auto-cmd12; 318 big-endian; 319 bus-width = <4>; 320 }; 321 322 scfg: scfg@1570000 { 323 compatible = "fsl,ls1046a-scfg", "syscon"; 324 reg = <0x0 0x1570000 0x0 0x10000>; 325 big-endian; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0x0 0x0 0x1570000 0x10000>; 329 330 extirq: interrupt-controller@1ac { 331 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; 332 #interrupt-cells = <2>; 333 #address-cells = <0>; 334 interrupt-controller; 335 reg = <0x1ac 4>; 336 interrupt-map = 337 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 338 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 339 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 340 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 341 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 342 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 343 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 344 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 345 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 346 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 347 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 348 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 349 interrupt-map-mask = <0xf 0x0>; 350 }; 351 }; 352 353 crypto: crypto@1700000 { 354 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 355 "fsl,sec-v4.0"; 356 fsl,sec-era = <8>; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges = <0x0 0x00 0x1700000 0x100000>; 360 reg = <0x00 0x1700000 0x0 0x100000>; 361 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 362 363 sec_jr0: jr@10000 { 364 compatible = "fsl,sec-v5.4-job-ring", 365 "fsl,sec-v5.0-job-ring", 366 "fsl,sec-v4.0-job-ring"; 367 reg = <0x10000 0x10000>; 368 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 369 }; 370 371 sec_jr1: jr@20000 { 372 compatible = "fsl,sec-v5.4-job-ring", 373 "fsl,sec-v5.0-job-ring", 374 "fsl,sec-v4.0-job-ring"; 375 reg = <0x20000 0x10000>; 376 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 377 }; 378 379 sec_jr2: jr@30000 { 380 compatible = "fsl,sec-v5.4-job-ring", 381 "fsl,sec-v5.0-job-ring", 382 "fsl,sec-v4.0-job-ring"; 383 reg = <0x30000 0x10000>; 384 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 385 }; 386 387 sec_jr3: jr@40000 { 388 compatible = "fsl,sec-v5.4-job-ring", 389 "fsl,sec-v5.0-job-ring", 390 "fsl,sec-v4.0-job-ring"; 391 reg = <0x40000 0x10000>; 392 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 393 }; 394 }; 395 396 qman: qman@1880000 { 397 compatible = "fsl,qman"; 398 reg = <0x0 0x1880000 0x0 0x10000>; 399 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 400 memory-region = <&qman_fqd &qman_pfdr>; 401 402 }; 403 404 bman: bman@1890000 { 405 compatible = "fsl,bman"; 406 reg = <0x0 0x1890000 0x0 0x10000>; 407 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 408 memory-region = <&bman_fbpr>; 409 410 }; 411 412 qportals: qman-portals@500000000 { 413 ranges = <0x0 0x5 0x00000000 0x8000000>; 414 }; 415 416 bportals: bman-portals@508000000 { 417 ranges = <0x0 0x5 0x08000000 0x8000000>; 418 }; 419 420 sfp: efuse@1e80000 { 421 compatible = "fsl,ls1021a-sfp"; 422 reg = <0x0 0x1e80000 0x0 0x10000>; 423 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 424 QORIQ_CLK_PLL_DIV(4)>; 425 clock-names = "sfp"; 426 }; 427 428 dcfg: dcfg@1ee0000 { 429 compatible = "fsl,ls1046a-dcfg", "syscon"; 430 reg = <0x0 0x1ee0000 0x0 0x1000>; 431 big-endian; 432 }; 433 434 clockgen: clocking@1ee1000 { 435 compatible = "fsl,ls1046a-clockgen"; 436 reg = <0x0 0x1ee1000 0x0 0x1000>; 437 #clock-cells = <2>; 438 clocks = <&sysclk>; 439 }; 440 441 tmu: tmu@1f00000 { 442 compatible = "fsl,qoriq-tmu"; 443 reg = <0x0 0x1f00000 0x0 0x10000>; 444 interrupts = <0 33 0x4>; 445 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 446 fsl,tmu-calibration = 447 /* Calibration data group 1 */ 448 <0x00000000 0x00000023 449 0x00000001 0x00000029 450 0x00000002 0x0000002f 451 0x00000003 0x00000036 452 0x00000004 0x0000003c 453 0x00000005 0x00000042 454 0x00000006 0x00000049 455 0x00000007 0x0000004f 456 0x00000008 0x00000055 457 0x00000009 0x0000005c 458 0x0000000a 0x00000062 459 0x0000000b 0x00000068 460 /* Calibration data group 2 */ 461 0x00010000 0x00000022 462 0x00010001 0x0000002a 463 0x00010002 0x00000032 464 0x00010003 0x0000003a 465 0x00010004 0x00000042 466 0x00010005 0x0000004a 467 0x00010006 0x00000052 468 0x00010007 0x0000005a 469 0x00010008 0x00000062 470 0x00010009 0x0000006a 471 /* Calibration data group 3 */ 472 0x00020000 0x00000021 473 0x00020001 0x0000002b 474 0x00020002 0x00000035 475 0x00020003 0x0000003e 476 0x00020004 0x00000048 477 0x00020005 0x00000052 478 0x00020006 0x0000005c 479 /* Calibration data group 4 */ 480 0x00030000 0x00000011 481 0x00030001 0x0000001a 482 0x00030002 0x00000024 483 0x00030003 0x0000002e 484 0x00030004 0x00000038 485 0x00030005 0x00000042 486 0x00030006 0x0000004c 487 0x00030007 0x00000056>; 488 big-endian; 489 #thermal-sensor-cells = <1>; 490 }; 491 492 dspi: spi@2100000 { 493 compatible = "fsl,ls1021a-v1.0-dspi"; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 reg = <0x0 0x2100000 0x0 0x10000>; 497 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 498 clock-names = "dspi"; 499 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 500 QORIQ_CLK_PLL_DIV(2)>; 501 spi-num-chipselects = <5>; 502 big-endian; 503 status = "disabled"; 504 }; 505 506 i2c0: i2c@2180000 { 507 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 reg = <0x0 0x2180000 0x0 0x10000>; 511 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 513 QORIQ_CLK_PLL_DIV(2)>; 514 dmas = <&edma0 1 38>, 515 <&edma0 1 39>; 516 dma-names = "rx", "tx"; 517 status = "disabled"; 518 }; 519 520 i2c1: i2c@2190000 { 521 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 reg = <0x0 0x2190000 0x0 0x10000>; 525 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 527 QORIQ_CLK_PLL_DIV(2)>; 528 scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 529 status = "disabled"; 530 }; 531 532 i2c2: i2c@21a0000 { 533 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 reg = <0x0 0x21a0000 0x0 0x10000>; 537 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 539 QORIQ_CLK_PLL_DIV(2)>; 540 scl-gpios = <&gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 541 status = "disabled"; 542 }; 543 544 i2c3: i2c@21b0000 { 545 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 reg = <0x0 0x21b0000 0x0 0x10000>; 549 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 551 QORIQ_CLK_PLL_DIV(2)>; 552 scl-gpios = <&gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 553 status = "disabled"; 554 }; 555 556 duart0: serial@21c0500 { 557 compatible = "fsl,ns16550", "ns16550a"; 558 reg = <0x00 0x21c0500 0x0 0x100>; 559 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 561 QORIQ_CLK_PLL_DIV(2)>; 562 status = "disabled"; 563 }; 564 565 duart1: serial@21c0600 { 566 compatible = "fsl,ns16550", "ns16550a"; 567 reg = <0x00 0x21c0600 0x0 0x100>; 568 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 570 QORIQ_CLK_PLL_DIV(2)>; 571 status = "disabled"; 572 }; 573 574 duart2: serial@21d0500 { 575 compatible = "fsl,ns16550", "ns16550a"; 576 reg = <0x0 0x21d0500 0x0 0x100>; 577 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 579 QORIQ_CLK_PLL_DIV(2)>; 580 status = "disabled"; 581 }; 582 583 duart3: serial@21d0600 { 584 compatible = "fsl,ns16550", "ns16550a"; 585 reg = <0x0 0x21d0600 0x0 0x100>; 586 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 588 QORIQ_CLK_PLL_DIV(2)>; 589 status = "disabled"; 590 }; 591 592 gpio0: gpio@2300000 { 593 compatible = "fsl,qoriq-gpio"; 594 reg = <0x0 0x2300000 0x0 0x10000>; 595 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 596 gpio-controller; 597 #gpio-cells = <2>; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 }; 601 602 gpio1: gpio@2310000 { 603 compatible = "fsl,qoriq-gpio"; 604 reg = <0x0 0x2310000 0x0 0x10000>; 605 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 606 gpio-controller; 607 #gpio-cells = <2>; 608 interrupt-controller; 609 #interrupt-cells = <2>; 610 }; 611 612 gpio2: gpio@2320000 { 613 compatible = "fsl,qoriq-gpio"; 614 reg = <0x0 0x2320000 0x0 0x10000>; 615 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 616 gpio-controller; 617 #gpio-cells = <2>; 618 interrupt-controller; 619 #interrupt-cells = <2>; 620 }; 621 622 gpio3: gpio@2330000 { 623 compatible = "fsl,qoriq-gpio"; 624 reg = <0x0 0x2330000 0x0 0x10000>; 625 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 626 gpio-controller; 627 #gpio-cells = <2>; 628 interrupt-controller; 629 #interrupt-cells = <2>; 630 }; 631 632 lpuart0: serial@2950000 { 633 compatible = "fsl,ls1021a-lpuart"; 634 reg = <0x0 0x2950000 0x0 0x1000>; 635 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 637 QORIQ_CLK_PLL_DIV(1)>; 638 clock-names = "ipg"; 639 status = "disabled"; 640 }; 641 642 lpuart1: serial@2960000 { 643 compatible = "fsl,ls1021a-lpuart"; 644 reg = <0x0 0x2960000 0x0 0x1000>; 645 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 647 QORIQ_CLK_PLL_DIV(2)>; 648 clock-names = "ipg"; 649 status = "disabled"; 650 }; 651 652 lpuart2: serial@2970000 { 653 compatible = "fsl,ls1021a-lpuart"; 654 reg = <0x0 0x2970000 0x0 0x1000>; 655 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 657 QORIQ_CLK_PLL_DIV(2)>; 658 clock-names = "ipg"; 659 status = "disabled"; 660 }; 661 662 lpuart3: serial@2980000 { 663 compatible = "fsl,ls1021a-lpuart"; 664 reg = <0x0 0x2980000 0x0 0x1000>; 665 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 667 QORIQ_CLK_PLL_DIV(2)>; 668 clock-names = "ipg"; 669 status = "disabled"; 670 }; 671 672 lpuart4: serial@2990000 { 673 compatible = "fsl,ls1021a-lpuart"; 674 reg = <0x0 0x2990000 0x0 0x1000>; 675 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 677 QORIQ_CLK_PLL_DIV(2)>; 678 clock-names = "ipg"; 679 status = "disabled"; 680 }; 681 682 lpuart5: serial@29a0000 { 683 compatible = "fsl,ls1021a-lpuart"; 684 reg = <0x0 0x29a0000 0x0 0x1000>; 685 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 687 QORIQ_CLK_PLL_DIV(2)>; 688 clock-names = "ipg"; 689 status = "disabled"; 690 }; 691 692 wdog0: watchdog@2ad0000 { 693 compatible = "fsl,imx21-wdt"; 694 reg = <0x0 0x2ad0000 0x0 0x10000>; 695 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 697 QORIQ_CLK_PLL_DIV(2)>; 698 big-endian; 699 }; 700 701 edma0: dma-controller@2c00000 { 702 #dma-cells = <2>; 703 compatible = "fsl,vf610-edma"; 704 reg = <0x0 0x2c00000 0x0 0x10000>, 705 <0x0 0x2c10000 0x0 0x10000>, 706 <0x0 0x2c20000 0x0 0x10000>; 707 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 709 interrupt-names = "edma-tx", "edma-err"; 710 dma-channels = <32>; 711 big-endian; 712 clock-names = "dmamux0", "dmamux1"; 713 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 714 QORIQ_CLK_PLL_DIV(2)>, 715 <&clockgen QORIQ_CLK_PLATFORM_PLL 716 QORIQ_CLK_PLL_DIV(2)>; 717 }; 718 719 aux_bus: aux_bus { 720 #address-cells = <2>; 721 #size-cells = <2>; 722 compatible = "simple-bus"; 723 ranges; 724 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; 725 726 usb0: usb@2f00000 { 727 compatible = "snps,dwc3"; 728 reg = <0x0 0x2f00000 0x0 0x10000>; 729 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 730 dr_mode = "host"; 731 snps,quirk-frame-length-adjustment = <0x20>; 732 snps,dis_rxdet_inp3_quirk; 733 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 734 usb3-lpm-capable; 735 }; 736 737 usb1: usb@3000000 { 738 compatible = "snps,dwc3"; 739 reg = <0x0 0x3000000 0x0 0x10000>; 740 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 741 dr_mode = "host"; 742 snps,quirk-frame-length-adjustment = <0x20>; 743 snps,dis_rxdet_inp3_quirk; 744 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 745 usb3-lpm-capable; 746 }; 747 748 usb2: usb@3100000 { 749 compatible = "snps,dwc3"; 750 reg = <0x0 0x3100000 0x0 0x10000>; 751 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 752 dr_mode = "host"; 753 snps,quirk-frame-length-adjustment = <0x20>; 754 snps,dis_rxdet_inp3_quirk; 755 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 756 usb3-lpm-capable; 757 }; 758 759 sata: sata@3200000 { 760 compatible = "fsl,ls1046a-ahci"; 761 reg = <0x0 0x3200000 0x0 0x10000>, 762 <0x0 0x20140520 0x0 0x4>; 763 reg-names = "ahci", "sata-ecc"; 764 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 766 QORIQ_CLK_PLL_DIV(2)>; 767 }; 768 }; 769 770 msi1: msi-controller@1580000 { 771 compatible = "fsl,ls1046a-msi"; 772 msi-controller; 773 reg = <0x0 0x1580000 0x0 0x10000>; 774 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 778 }; 779 780 msi2: msi-controller@1590000 { 781 compatible = "fsl,ls1046a-msi"; 782 msi-controller; 783 reg = <0x0 0x1590000 0x0 0x10000>; 784 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 788 }; 789 790 msi3: msi-controller@15a0000 { 791 compatible = "fsl,ls1046a-msi"; 792 msi-controller; 793 reg = <0x0 0x15a0000 0x0 0x10000>; 794 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 798 }; 799 800 pcie1: pcie@3400000 { 801 compatible = "fsl,ls1046a-pcie"; 802 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 803 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 804 reg-names = "regs", "config"; 805 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 806 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 807 interrupt-names = "aer", "pme"; 808 #address-cells = <3>; 809 #size-cells = <2>; 810 device_type = "pci"; 811 num-viewport = <8>; 812 bus-range = <0x0 0xff>; 813 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 814 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 815 msi-parent = <&msi1>, <&msi2>, <&msi3>; 816 #interrupt-cells = <1>; 817 interrupt-map-mask = <0 0 0 7>; 818 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 819 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 820 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 821 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 822 big-endian; 823 status = "disabled"; 824 }; 825 826 pcie_ep1: pcie_ep@3400000 { 827 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 828 reg = <0x00 0x03400000 0x0 0x00100000>, 829 <0x40 0x00000000 0x8 0x00000000>; 830 reg-names = "regs", "addr_space"; 831 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "pme"; 833 num-ib-windows = <6>; 834 num-ob-windows = <8>; 835 big-endian; 836 status = "disabled"; 837 }; 838 839 pcie2: pcie@3500000 { 840 compatible = "fsl,ls1046a-pcie"; 841 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 842 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 843 reg-names = "regs", "config"; 844 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 845 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 846 interrupt-names = "aer", "pme"; 847 #address-cells = <3>; 848 #size-cells = <2>; 849 device_type = "pci"; 850 num-viewport = <8>; 851 bus-range = <0x0 0xff>; 852 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 853 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 854 msi-parent = <&msi2>, <&msi3>, <&msi1>; 855 #interrupt-cells = <1>; 856 interrupt-map-mask = <0 0 0 7>; 857 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 858 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 859 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 860 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 861 big-endian; 862 status = "disabled"; 863 }; 864 865 pcie_ep2: pcie_ep@3500000 { 866 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 867 reg = <0x00 0x03500000 0x0 0x00100000>, 868 <0x48 0x00000000 0x8 0x00000000>; 869 reg-names = "regs", "addr_space"; 870 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 871 interrupt-names = "pme"; 872 num-ib-windows = <6>; 873 num-ob-windows = <8>; 874 big-endian; 875 status = "disabled"; 876 }; 877 878 pcie3: pcie@3600000 { 879 compatible = "fsl,ls1046a-pcie"; 880 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 881 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 882 reg-names = "regs", "config"; 883 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 884 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 885 interrupt-names = "aer", "pme"; 886 #address-cells = <3>; 887 #size-cells = <2>; 888 device_type = "pci"; 889 num-viewport = <8>; 890 bus-range = <0x0 0xff>; 891 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 892 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 893 msi-parent = <&msi3>, <&msi1>, <&msi2>; 894 #interrupt-cells = <1>; 895 interrupt-map-mask = <0 0 0 7>; 896 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 897 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 898 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 899 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 900 big-endian; 901 status = "disabled"; 902 }; 903 904 pcie_ep3: pcie_ep@3600000 { 905 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; 906 reg = <0x00 0x03600000 0x0 0x00100000>, 907 <0x50 0x00000000 0x8 0x00000000>; 908 reg-names = "regs", "addr_space"; 909 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 910 interrupt-names = "pme"; 911 num-ib-windows = <6>; 912 num-ob-windows = <8>; 913 big-endian; 914 status = "disabled"; 915 }; 916 917 qdma: dma-controller@8380000 { 918 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 919 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 920 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 921 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 922 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 927 interrupt-names = "qdma-error", "qdma-queue0", 928 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 929 dma-channels = <8>; 930 block-number = <1>; 931 block-offset = <0x10000>; 932 fsl,dma-queues = <2>; 933 status-sizes = <64>; 934 queue-sizes = <64 64>; 935 big-endian; 936 }; 937 938 rcpm: power-controller@1ee2140 { 939 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; 940 reg = <0x0 0x1ee2140 0x0 0x4>; 941 #fsl,rcpm-wakeup-cells = <1>; 942 }; 943 944 ftm_alarm0: timer@29d0000 { 945 compatible = "fsl,ls1046a-ftm-alarm"; 946 reg = <0x0 0x29d0000 0x0 0x10000>; 947 fsl,rcpm-wakeup = <&rcpm 0x20000>; 948 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 949 big-endian; 950 }; 951 }; 952 953 reserved-memory { 954 #address-cells = <2>; 955 #size-cells = <2>; 956 ranges; 957 958 bman_fbpr: bman-fbpr { 959 compatible = "shared-dma-pool"; 960 size = <0 0x1000000>; 961 alignment = <0 0x1000000>; 962 no-map; 963 }; 964 965 qman_fqd: qman-fqd { 966 compatible = "shared-dma-pool"; 967 size = <0 0x800000>; 968 alignment = <0 0x800000>; 969 no-map; 970 }; 971 972 qman_pfdr: qman-pfdr { 973 compatible = "shared-dma-pool"; 974 size = <0 0x2000000>; 975 alignment = <0 0x2000000>; 976 no-map; 977 }; 978 }; 979 980 firmware { 981 optee { 982 compatible = "linaro,optee-tz"; 983 method = "smc"; 984 }; 985 }; 986}; 987 988#include "qoriq-qman-portals.dtsi" 989#include "qoriq-bman-portals.dtsi" 990