1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 *
8 * Mingkai Hu <mingkai.hu@nxp.com>
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15	compatible = "fsl,ls1046a";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		crypto = &crypto;
22		fman0 = &fman0;
23		ethernet0 = &enet0;
24		ethernet1 = &enet1;
25		ethernet2 = &enet2;
26		ethernet3 = &enet3;
27		ethernet4 = &enet4;
28		ethernet5 = &enet5;
29		ethernet6 = &enet6;
30		ethernet7 = &enet7;
31		rtc1 = &ftm_alarm0;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu0: cpu@0 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a72";
41			reg = <0x0>;
42			clocks = <&clockgen 1 0>;
43			next-level-cache = <&l2>;
44			cpu-idle-states = <&CPU_PH20>;
45			#cooling-cells = <2>;
46		};
47
48		cpu1: cpu@1 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a72";
51			reg = <0x1>;
52			clocks = <&clockgen 1 0>;
53			next-level-cache = <&l2>;
54			cpu-idle-states = <&CPU_PH20>;
55			#cooling-cells = <2>;
56		};
57
58		cpu2: cpu@2 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a72";
61			reg = <0x2>;
62			clocks = <&clockgen 1 0>;
63			next-level-cache = <&l2>;
64			cpu-idle-states = <&CPU_PH20>;
65			#cooling-cells = <2>;
66		};
67
68		cpu3: cpu@3 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a72";
71			reg = <0x3>;
72			clocks = <&clockgen 1 0>;
73			next-level-cache = <&l2>;
74			cpu-idle-states = <&CPU_PH20>;
75			#cooling-cells = <2>;
76		};
77
78		l2: l2-cache {
79			compatible = "cache";
80		};
81	};
82
83	idle-states {
84		/*
85		 * PSCI node is not added default, U-boot will add missing
86		 * parts if it determines to use PSCI.
87		 */
88		entry-method = "psci";
89
90		CPU_PH20: cpu-ph20 {
91			compatible = "arm,idle-state";
92			idle-state-name = "PH20";
93			arm,psci-suspend-param = <0x0>;
94			entry-latency-us = <1000>;
95			exit-latency-us = <1000>;
96			min-residency-us = <3000>;
97		};
98	};
99
100	memory@80000000 {
101		device_type = "memory";
102		/* Real size will be filled by bootloader */
103		reg = <0x0 0x80000000 0x0 0x0>;
104	};
105
106	sysclk: sysclk {
107		compatible = "fixed-clock";
108		#clock-cells = <0>;
109		clock-frequency = <100000000>;
110		clock-output-names = "sysclk";
111	};
112
113	reboot {
114		compatible ="syscon-reboot";
115		regmap = <&dcfg>;
116		offset = <0xb0>;
117		mask = <0x02>;
118	};
119
120	thermal-zones {
121		ddr-controller {
122			polling-delay-passive = <1000>;
123			polling-delay = <5000>;
124			thermal-sensors = <&tmu 0>;
125
126			trips {
127				ddr-ctrler-alert {
128					temperature = <85000>;
129					hysteresis = <2000>;
130					type = "passive";
131				};
132
133				ddr-ctrler-crit {
134					temperature = <95000>;
135					hysteresis = <2000>;
136					type = "critical";
137				};
138			};
139		};
140
141		serdes {
142			polling-delay-passive = <1000>;
143			polling-delay = <5000>;
144			thermal-sensors = <&tmu 1>;
145
146			trips {
147				serdes-alert {
148					temperature = <85000>;
149					hysteresis = <2000>;
150					type = "passive";
151				};
152
153				serdes-crit {
154					temperature = <95000>;
155					hysteresis = <2000>;
156					type = "critical";
157				};
158			};
159		};
160
161		fman {
162			polling-delay-passive = <1000>;
163			polling-delay = <5000>;
164			thermal-sensors = <&tmu 2>;
165
166			trips {
167				fman-alert {
168					temperature = <85000>;
169					hysteresis = <2000>;
170					type = "passive";
171				};
172
173				fman-crit {
174					temperature = <95000>;
175					hysteresis = <2000>;
176					type = "critical";
177				};
178			};
179		};
180
181		core-cluster {
182			polling-delay-passive = <1000>;
183			polling-delay = <5000>;
184			thermal-sensors = <&tmu 3>;
185
186			trips {
187				core_cluster_alert: core-cluster-alert {
188					temperature = <85000>;
189					hysteresis = <2000>;
190					type = "passive";
191				};
192
193				core_cluster_crit: core-cluster-crit {
194					temperature = <95000>;
195					hysteresis = <2000>;
196					type = "critical";
197				};
198			};
199
200			cooling-maps {
201				map0 {
202					trip = <&core_cluster_alert>;
203					cooling-device =
204						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
205						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
208				};
209			};
210		};
211
212		sec {
213			polling-delay-passive = <1000>;
214			polling-delay = <5000>;
215			thermal-sensors = <&tmu 4>;
216
217			trips {
218				sec-alert {
219					temperature = <85000>;
220					hysteresis = <2000>;
221					type = "passive";
222				};
223
224				sec-crit {
225					temperature = <95000>;
226					hysteresis = <2000>;
227					type = "critical";
228				};
229			};
230		};
231	};
232
233	timer {
234		compatible = "arm,armv8-timer";
235		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
236					  IRQ_TYPE_LEVEL_LOW)>,
237			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
238					  IRQ_TYPE_LEVEL_LOW)>,
239			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
240					  IRQ_TYPE_LEVEL_LOW)>,
241			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
242					  IRQ_TYPE_LEVEL_LOW)>;
243	};
244
245	pmu {
246		compatible = "arm,cortex-a72-pmu";
247		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
248			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
249			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
250			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
251		interrupt-affinity = <&cpu0>,
252				     <&cpu1>,
253				     <&cpu2>,
254				     <&cpu3>;
255	};
256
257	gic: interrupt-controller@1400000 {
258		compatible = "arm,gic-400";
259		#interrupt-cells = <3>;
260		interrupt-controller;
261		reg = <0x0 0x1410000 0 0x10000>, /* GICD */
262		      <0x0 0x1420000 0 0x20000>, /* GICC */
263		      <0x0 0x1440000 0 0x20000>, /* GICH */
264		      <0x0 0x1460000 0 0x20000>; /* GICV */
265		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
266					 IRQ_TYPE_LEVEL_LOW)>;
267	};
268
269	soc: soc {
270		compatible = "simple-bus";
271		#address-cells = <2>;
272		#size-cells = <2>;
273		ranges;
274
275		ddr: memory-controller@1080000 {
276			compatible = "fsl,qoriq-memory-controller";
277			reg = <0x0 0x1080000 0x0 0x1000>;
278			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
279			big-endian;
280		};
281
282		ifc: ifc@1530000 {
283			compatible = "fsl,ifc", "simple-bus";
284			reg = <0x0 0x1530000 0x0 0x10000>;
285			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
286			status = "disabled";
287		};
288
289		qspi: spi@1550000 {
290			compatible = "fsl,ls1021a-qspi";
291			#address-cells = <1>;
292			#size-cells = <0>;
293			reg = <0x0 0x1550000 0x0 0x10000>,
294				<0x0 0x40000000 0x0 0x10000000>;
295			reg-names = "QuadSPI", "QuadSPI-memory";
296			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
297			clock-names = "qspi_en", "qspi";
298			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
299			status = "disabled";
300		};
301
302		esdhc: esdhc@1560000 {
303			compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
304			reg = <0x0 0x1560000 0x0 0x10000>;
305			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
306			clocks = <&clockgen 2 1>;
307			voltage-ranges = <1800 1800 3300 3300>;
308			sdhci,auto-cmd12;
309			big-endian;
310			bus-width = <4>;
311		};
312
313		scfg: scfg@1570000 {
314			compatible = "fsl,ls1046a-scfg", "syscon";
315			reg = <0x0 0x1570000 0x0 0x10000>;
316			big-endian;
317		};
318
319		crypto: crypto@1700000 {
320			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
321				     "fsl,sec-v4.0";
322			fsl,sec-era = <8>;
323			#address-cells = <1>;
324			#size-cells = <1>;
325			ranges = <0x0 0x00 0x1700000 0x100000>;
326			reg = <0x00 0x1700000 0x0 0x100000>;
327			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
328
329			sec_jr0: jr@10000 {
330				compatible = "fsl,sec-v5.4-job-ring",
331					     "fsl,sec-v5.0-job-ring",
332					     "fsl,sec-v4.0-job-ring";
333				reg	   = <0x10000 0x10000>;
334				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
335			};
336
337			sec_jr1: jr@20000 {
338				compatible = "fsl,sec-v5.4-job-ring",
339					     "fsl,sec-v5.0-job-ring",
340					     "fsl,sec-v4.0-job-ring";
341				reg	   = <0x20000 0x10000>;
342				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
343			};
344
345			sec_jr2: jr@30000 {
346				compatible = "fsl,sec-v5.4-job-ring",
347					     "fsl,sec-v5.0-job-ring",
348					     "fsl,sec-v4.0-job-ring";
349				reg	   = <0x30000 0x10000>;
350				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
351			};
352
353			sec_jr3: jr@40000 {
354				compatible = "fsl,sec-v5.4-job-ring",
355					     "fsl,sec-v5.0-job-ring",
356					     "fsl,sec-v4.0-job-ring";
357				reg	   = <0x40000 0x10000>;
358				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
359			};
360		};
361
362		qman: qman@1880000 {
363			compatible = "fsl,qman";
364			reg = <0x0 0x1880000 0x0 0x10000>;
365			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
366			memory-region = <&qman_fqd &qman_pfdr>;
367
368		};
369
370		bman: bman@1890000 {
371			compatible = "fsl,bman";
372			reg = <0x0 0x1890000 0x0 0x10000>;
373			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
374			memory-region = <&bman_fbpr>;
375
376		};
377
378		qportals: qman-portals@500000000 {
379			ranges = <0x0 0x5 0x00000000 0x8000000>;
380		};
381
382		bportals: bman-portals@508000000 {
383			ranges = <0x0 0x5 0x08000000 0x8000000>;
384		};
385
386		dcfg: dcfg@1ee0000 {
387			compatible = "fsl,ls1046a-dcfg", "syscon";
388			reg = <0x0 0x1ee0000 0x0 0x10000>;
389			big-endian;
390		};
391
392		clockgen: clocking@1ee1000 {
393			compatible = "fsl,ls1046a-clockgen";
394			reg = <0x0 0x1ee1000 0x0 0x1000>;
395			#clock-cells = <2>;
396			clocks = <&sysclk>;
397		};
398
399		tmu: tmu@1f00000 {
400			compatible = "fsl,qoriq-tmu";
401			reg = <0x0 0x1f00000 0x0 0x10000>;
402			interrupts = <0 33 0x4>;
403			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
404			fsl,tmu-calibration =
405				/* Calibration data group 1 */
406				<0x00000000 0x00000026
407				0x00000001 0x0000002d
408				0x00000002 0x00000032
409				0x00000003 0x00000039
410				0x00000004 0x0000003f
411				0x00000005 0x00000046
412				0x00000006 0x0000004d
413				0x00000007 0x00000054
414				0x00000008 0x0000005a
415				0x00000009 0x00000061
416				0x0000000a 0x0000006a
417				0x0000000b 0x00000071
418				/* Calibration data group 2 */
419				0x00010000 0x00000025
420				0x00010001 0x0000002c
421				0x00010002 0x00000035
422				0x00010003 0x0000003d
423				0x00010004 0x00000045
424				0x00010005 0x0000004e
425				0x00010006 0x00000057
426				0x00010007 0x00000061
427				0x00010008 0x0000006b
428				0x00010009 0x00000076
429				/* Calibration data group 3 */
430				0x00020000 0x00000029
431				0x00020001 0x00000033
432				0x00020002 0x0000003d
433				0x00020003 0x00000049
434				0x00020004 0x00000056
435				0x00020005 0x00000061
436				0x00020006 0x0000006d
437				/* Calibration data group 4 */
438				0x00030000 0x00000021
439				0x00030001 0x0000002a
440				0x00030002 0x0000003c
441				0x00030003 0x0000004e>;
442			big-endian;
443			#thermal-sensor-cells = <1>;
444		};
445
446		dspi: spi@2100000 {
447			compatible = "fsl,ls1021a-v1.0-dspi";
448			#address-cells = <1>;
449			#size-cells = <0>;
450			reg = <0x0 0x2100000 0x0 0x10000>;
451			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
452			clock-names = "dspi";
453			clocks = <&clockgen 4 1>;
454			spi-num-chipselects = <5>;
455			big-endian;
456			status = "disabled";
457		};
458
459		i2c0: i2c@2180000 {
460			compatible = "fsl,vf610-i2c";
461			#address-cells = <1>;
462			#size-cells = <0>;
463			reg = <0x0 0x2180000 0x0 0x10000>;
464			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
465			clocks = <&clockgen 4 1>;
466			dmas = <&edma0 1 39>,
467			       <&edma0 1 38>;
468			dma-names = "tx", "rx";
469			status = "disabled";
470		};
471
472		i2c1: i2c@2190000 {
473			compatible = "fsl,vf610-i2c";
474			#address-cells = <1>;
475			#size-cells = <0>;
476			reg = <0x0 0x2190000 0x0 0x10000>;
477			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
478			clocks = <&clockgen 4 1>;
479			status = "disabled";
480		};
481
482		i2c2: i2c@21a0000 {
483			compatible = "fsl,vf610-i2c";
484			#address-cells = <1>;
485			#size-cells = <0>;
486			reg = <0x0 0x21a0000 0x0 0x10000>;
487			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
488			clocks = <&clockgen 4 1>;
489			status = "disabled";
490		};
491
492		i2c3: i2c@21b0000 {
493			compatible = "fsl,vf610-i2c";
494			#address-cells = <1>;
495			#size-cells = <0>;
496			reg = <0x0 0x21b0000 0x0 0x10000>;
497			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
498			clocks = <&clockgen 4 1>;
499			status = "disabled";
500		};
501
502		duart0: serial@21c0500 {
503			compatible = "fsl,ns16550", "ns16550a";
504			reg = <0x00 0x21c0500 0x0 0x100>;
505			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
506			clocks = <&clockgen 4 1>;
507			status = "disabled";
508		};
509
510		duart1: serial@21c0600 {
511			compatible = "fsl,ns16550", "ns16550a";
512			reg = <0x00 0x21c0600 0x0 0x100>;
513			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
514			clocks = <&clockgen 4 1>;
515			status = "disabled";
516		};
517
518		duart2: serial@21d0500 {
519			compatible = "fsl,ns16550", "ns16550a";
520			reg = <0x0 0x21d0500 0x0 0x100>;
521			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
522			clocks = <&clockgen 4 1>;
523			status = "disabled";
524		};
525
526		duart3: serial@21d0600 {
527			compatible = "fsl,ns16550", "ns16550a";
528			reg = <0x0 0x21d0600 0x0 0x100>;
529			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
530			clocks = <&clockgen 4 1>;
531			status = "disabled";
532		};
533
534		gpio0: gpio@2300000 {
535			compatible = "fsl,qoriq-gpio";
536			reg = <0x0 0x2300000 0x0 0x10000>;
537			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
538			gpio-controller;
539			#gpio-cells = <2>;
540			interrupt-controller;
541			#interrupt-cells = <2>;
542		};
543
544		gpio1: gpio@2310000 {
545			compatible = "fsl,qoriq-gpio";
546			reg = <0x0 0x2310000 0x0 0x10000>;
547			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
548			gpio-controller;
549			#gpio-cells = <2>;
550			interrupt-controller;
551			#interrupt-cells = <2>;
552		};
553
554		gpio2: gpio@2320000 {
555			compatible = "fsl,qoriq-gpio";
556			reg = <0x0 0x2320000 0x0 0x10000>;
557			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
558			gpio-controller;
559			#gpio-cells = <2>;
560			interrupt-controller;
561			#interrupt-cells = <2>;
562		};
563
564		gpio3: gpio@2330000 {
565			compatible = "fsl,qoriq-gpio";
566			reg = <0x0 0x2330000 0x0 0x10000>;
567			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
568			gpio-controller;
569			#gpio-cells = <2>;
570			interrupt-controller;
571			#interrupt-cells = <2>;
572		};
573
574		lpuart0: serial@2950000 {
575			compatible = "fsl,ls1021a-lpuart";
576			reg = <0x0 0x2950000 0x0 0x1000>;
577			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
578			clocks = <&clockgen 4 0>;
579			clock-names = "ipg";
580			status = "disabled";
581		};
582
583		lpuart1: serial@2960000 {
584			compatible = "fsl,ls1021a-lpuart";
585			reg = <0x0 0x2960000 0x0 0x1000>;
586			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
587			clocks = <&clockgen 4 1>;
588			clock-names = "ipg";
589			status = "disabled";
590		};
591
592		lpuart2: serial@2970000 {
593			compatible = "fsl,ls1021a-lpuart";
594			reg = <0x0 0x2970000 0x0 0x1000>;
595			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
596			clocks = <&clockgen 4 1>;
597			clock-names = "ipg";
598			status = "disabled";
599		};
600
601		lpuart3: serial@2980000 {
602			compatible = "fsl,ls1021a-lpuart";
603			reg = <0x0 0x2980000 0x0 0x1000>;
604			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
605			clocks = <&clockgen 4 1>;
606			clock-names = "ipg";
607			status = "disabled";
608		};
609
610		lpuart4: serial@2990000 {
611			compatible = "fsl,ls1021a-lpuart";
612			reg = <0x0 0x2990000 0x0 0x1000>;
613			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
614			clocks = <&clockgen 4 1>;
615			clock-names = "ipg";
616			status = "disabled";
617		};
618
619		lpuart5: serial@29a0000 {
620			compatible = "fsl,ls1021a-lpuart";
621			reg = <0x0 0x29a0000 0x0 0x1000>;
622			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
623			clocks = <&clockgen 4 1>;
624			clock-names = "ipg";
625			status = "disabled";
626		};
627
628		wdog0: watchdog@2ad0000 {
629			compatible = "fsl,imx21-wdt";
630			reg = <0x0 0x2ad0000 0x0 0x10000>;
631			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
632			clocks = <&clockgen 4 1>;
633			big-endian;
634		};
635
636		edma0: edma@2c00000 {
637			#dma-cells = <2>;
638			compatible = "fsl,vf610-edma";
639			reg = <0x0 0x2c00000 0x0 0x10000>,
640			      <0x0 0x2c10000 0x0 0x10000>,
641			      <0x0 0x2c20000 0x0 0x10000>;
642			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
643				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
644			interrupt-names = "edma-tx", "edma-err";
645			dma-channels = <32>;
646			big-endian;
647			clock-names = "dmamux0", "dmamux1";
648			clocks = <&clockgen 4 1>,
649				 <&clockgen 4 1>;
650		};
651
652		usb0: usb@2f00000 {
653			compatible = "snps,dwc3";
654			reg = <0x0 0x2f00000 0x0 0x10000>;
655			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
656			dr_mode = "host";
657			snps,quirk-frame-length-adjustment = <0x20>;
658			snps,dis_rxdet_inp3_quirk;
659			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
660		};
661
662		usb1: usb@3000000 {
663			compatible = "snps,dwc3";
664			reg = <0x0 0x3000000 0x0 0x10000>;
665			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
666			dr_mode = "host";
667			snps,quirk-frame-length-adjustment = <0x20>;
668			snps,dis_rxdet_inp3_quirk;
669			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
670		};
671
672		usb2: usb@3100000 {
673			compatible = "snps,dwc3";
674			reg = <0x0 0x3100000 0x0 0x10000>;
675			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
676			dr_mode = "host";
677			snps,quirk-frame-length-adjustment = <0x20>;
678			snps,dis_rxdet_inp3_quirk;
679			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
680		};
681
682		sata: sata@3200000 {
683			compatible = "fsl,ls1046a-ahci";
684			reg = <0x0 0x3200000 0x0 0x10000>,
685				<0x0 0x20140520 0x0 0x4>;
686			reg-names = "ahci", "sata-ecc";
687			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
688			clocks = <&clockgen 4 1>;
689		};
690
691		msi1: msi-controller@1580000 {
692			compatible = "fsl,ls1046a-msi";
693			msi-controller;
694			reg = <0x0 0x1580000 0x0 0x10000>;
695			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
696				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
697				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
698				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
699		};
700
701		msi2: msi-controller@1590000 {
702			compatible = "fsl,ls1046a-msi";
703			msi-controller;
704			reg = <0x0 0x1590000 0x0 0x10000>;
705			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
706				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
707				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
708				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
709		};
710
711		msi3: msi-controller@15a0000 {
712			compatible = "fsl,ls1046a-msi";
713			msi-controller;
714			reg = <0x0 0x15a0000 0x0 0x10000>;
715			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
716				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
717				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
718				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
719		};
720
721		pcie@3400000 {
722			compatible = "fsl,ls1046a-pcie";
723			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
724			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
725			reg-names = "regs", "config";
726			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
727				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
728			interrupt-names = "aer", "pme";
729			#address-cells = <3>;
730			#size-cells = <2>;
731			device_type = "pci";
732			dma-coherent;
733			num-viewport = <8>;
734			bus-range = <0x0 0xff>;
735			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
736				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
737			msi-parent = <&msi1>, <&msi2>, <&msi3>;
738			#interrupt-cells = <1>;
739			interrupt-map-mask = <0 0 0 7>;
740			interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
741					<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
742					<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
743					<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
744			status = "disabled";
745		};
746
747		pcie_ep@3400000 {
748			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
749			reg = <0x00 0x03400000 0x0 0x00100000
750				0x40 0x00000000 0x8 0x00000000>;
751			reg-names = "regs", "addr_space";
752			num-ib-windows = <6>;
753			num-ob-windows = <8>;
754			status = "disabled";
755		};
756
757		pcie@3500000 {
758			compatible = "fsl,ls1046a-pcie";
759			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
760			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
761			reg-names = "regs", "config";
762			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
763				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
764			interrupt-names = "aer", "pme";
765			#address-cells = <3>;
766			#size-cells = <2>;
767			device_type = "pci";
768			dma-coherent;
769			num-viewport = <8>;
770			bus-range = <0x0 0xff>;
771			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
772				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
773			msi-parent = <&msi2>, <&msi3>, <&msi1>;
774			#interrupt-cells = <1>;
775			interrupt-map-mask = <0 0 0 7>;
776			interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
777					<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
778					<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
779					<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
780			status = "disabled";
781		};
782
783		pcie_ep@3500000 {
784			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
785			reg = <0x00 0x03500000 0x0 0x00100000
786				0x48 0x00000000 0x8 0x00000000>;
787			reg-names = "regs", "addr_space";
788			num-ib-windows = <6>;
789			num-ob-windows = <8>;
790			status = "disabled";
791		};
792
793		pcie@3600000 {
794			compatible = "fsl,ls1046a-pcie";
795			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
796			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
797			reg-names = "regs", "config";
798			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
799				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
800			interrupt-names = "aer", "pme";
801			#address-cells = <3>;
802			#size-cells = <2>;
803			device_type = "pci";
804			dma-coherent;
805			num-viewport = <8>;
806			bus-range = <0x0 0xff>;
807			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
808				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
809			msi-parent = <&msi3>, <&msi1>, <&msi2>;
810			#interrupt-cells = <1>;
811			interrupt-map-mask = <0 0 0 7>;
812			interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
813					<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
814					<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
815					<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
816			status = "disabled";
817		};
818
819		pcie_ep@3600000 {
820			compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
821			reg = <0x00 0x03600000 0x0 0x00100000
822				0x50 0x00000000 0x8 0x00000000>;
823			reg-names = "regs", "addr_space";
824			num-ib-windows = <6>;
825			num-ob-windows = <8>;
826			status = "disabled";
827		};
828
829		qdma: dma-controller@8380000 {
830			compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
831			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
832			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
833			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
834			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
835				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
836				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
837				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
838				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
839			interrupt-names = "qdma-error", "qdma-queue0",
840				"qdma-queue1", "qdma-queue2", "qdma-queue3";
841			dma-channels = <8>;
842			block-number = <1>;
843			block-offset = <0x10000>;
844			fsl,dma-queues = <2>;
845			status-sizes = <64>;
846			queue-sizes = <64 64>;
847			big-endian;
848		};
849
850		rcpm: power-controller@1ee2140 {
851			compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
852			reg = <0x0 0x1ee2140 0x0 0x4>;
853			#fsl,rcpm-wakeup-cells = <1>;
854		};
855
856		ftm_alarm0: timer@29d0000 {
857			compatible = "fsl,ls1046a-ftm-alarm";
858			reg = <0x0 0x29d0000 0x0 0x10000>;
859			fsl,rcpm-wakeup = <&rcpm 0x20000>;
860			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
861			big-endian;
862		};
863	};
864
865	reserved-memory {
866		#address-cells = <2>;
867		#size-cells = <2>;
868		ranges;
869
870		bman_fbpr: bman-fbpr {
871			compatible = "shared-dma-pool";
872			size = <0 0x1000000>;
873			alignment = <0 0x1000000>;
874			no-map;
875		};
876
877		qman_fqd: qman-fqd {
878			compatible = "shared-dma-pool";
879			size = <0 0x800000>;
880			alignment = <0 0x800000>;
881			no-map;
882		};
883
884		qman_pfdr: qman-pfdr {
885			compatible = "shared-dma-pool";
886			size = <0 0x2000000>;
887			alignment = <0 0x2000000>;
888			no-map;
889		};
890	};
891
892	firmware {
893		optee {
894			compatible = "linaro,optee-tz";
895			method = "smc";
896		};
897	};
898};
899
900#include "qoriq-qman-portals.dtsi"
901#include "qoriq-bman-portals.dtsi"
902