1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 *
7 * Mingkai Hu <mingkai.hu@nxp.com>
8 */
9
10/dts-v1/;
11
12#include "fsl-ls1046a.dtsi"
13
14/ {
15	model = "LS1046A RDB Board";
16	compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
17
18	aliases {
19		serial0 = &duart0;
20		serial1 = &duart1;
21		serial2 = &duart2;
22		serial3 = &duart3;
23	};
24
25	chosen {
26		stdout-path = "serial0:115200n8";
27	};
28};
29
30&duart0 {
31	status = "okay";
32};
33
34&duart1 {
35	status = "okay";
36};
37
38&esdhc {
39	mmc-hs200-1_8v;
40	sd-uhs-sdr104;
41	sd-uhs-sdr50;
42	sd-uhs-sdr25;
43	sd-uhs-sdr12;
44};
45
46&i2c0 {
47	status = "okay";
48
49	ina220@40 {
50		compatible = "ti,ina220";
51		reg = <0x40>;
52		shunt-resistor = <1000>;
53	};
54
55	temp-sensor@4c {
56		compatible = "adi,adt7461";
57		reg = <0x4c>;
58	};
59
60	eeprom@52 {
61		compatible = "atmel,24c512";
62		reg = <0x52>;
63	};
64
65	eeprom@53 {
66		compatible = "atmel,24c512";
67		reg = <0x53>;
68	};
69};
70
71&i2c3 {
72	status = "okay";
73
74	rtc@51 {
75		compatible = "nxp,pcf2129";
76		reg = <0x51>;
77	};
78};
79
80&ifc {
81	#address-cells = <2>;
82	#size-cells = <1>;
83	/* NAND Flashe and CPLD on board */
84	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
85		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
86	status = "okay";
87
88	nand@0,0 {
89		compatible = "fsl,ifc-nand";
90		#address-cells = <1>;
91		#size-cells = <1>;
92		reg = <0x0 0x0 0x10000>;
93	};
94
95	cpld: board-control@2,0 {
96		compatible = "fsl,ls1046ardb-cpld";
97		reg = <0x2 0x0 0x0000100>;
98	};
99};
100
101&qspi {
102	status = "okay";
103
104	qflash0: s25fs512s@0 {
105		compatible = "spansion,m25p80";
106		#address-cells = <1>;
107		#size-cells = <1>;
108		spi-max-frequency = <20000000>;
109		spi-rx-bus-width = <4>;
110		spi-tx-bus-width = <4>;
111		reg = <0>;
112	};
113
114	qflash1: s25fs512s@1 {
115		compatible = "spansion,m25p80";
116		#address-cells = <1>;
117		#size-cells = <1>;
118		spi-max-frequency = <20000000>;
119		spi-rx-bus-width = <4>;
120		spi-tx-bus-width = <4>;
121		reg = <1>;
122	};
123};
124
125#include "fsl-ls1046-post.dtsi"
126
127&fman0 {
128	ethernet@e4000 {
129		phy-handle = <&rgmii_phy1>;
130		phy-connection-type = "rgmii";
131	};
132
133	ethernet@e6000 {
134		phy-handle = <&rgmii_phy2>;
135		phy-connection-type = "rgmii";
136	};
137
138	ethernet@e8000 {
139		phy-handle = <&sgmii_phy1>;
140		phy-connection-type = "sgmii";
141	};
142
143	ethernet@ea000 {
144		phy-handle = <&sgmii_phy2>;
145		phy-connection-type = "sgmii";
146	};
147
148	ethernet@f0000 { /* 10GEC1 */
149		phy-handle = <&aqr106_phy>;
150		phy-connection-type = "xgmii";
151	};
152
153	ethernet@f2000 { /* 10GEC2 */
154		fixed-link = <0 1 1000 0 0>;
155		phy-connection-type = "xgmii";
156	};
157
158	mdio@fc000 {
159		rgmii_phy1: ethernet-phy@1 {
160			reg = <0x1>;
161		};
162
163		rgmii_phy2: ethernet-phy@2 {
164			reg = <0x2>;
165		};
166
167		sgmii_phy1: ethernet-phy@3 {
168			reg = <0x3>;
169		};
170
171		sgmii_phy2: ethernet-phy@4 {
172			reg = <0x4>;
173		};
174	};
175
176	mdio@fd000 {
177		aqr106_phy: ethernet-phy@0 {
178			compatible = "ethernet-phy-ieee802.3-c45";
179			interrupts = <0 131 4>;
180			reg = <0x0>;
181		};
182	};
183};
184