1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11#include <dt-bindings/thermal/thermal.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15	compatible = "fsl,ls1043a";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		crypto = &crypto;
22		fman0 = &fman0;
23		ethernet0 = &enet0;
24		ethernet1 = &enet1;
25		ethernet2 = &enet2;
26		ethernet3 = &enet3;
27		ethernet4 = &enet4;
28		ethernet5 = &enet5;
29		ethernet6 = &enet6;
30		rtc1 = &ftm_alarm0;
31	};
32
33	cpus {
34		#address-cells = <1>;
35		#size-cells = <0>;
36
37		/*
38		 * We expect the enable-method for cpu's to be "psci", but this
39		 * is dependent on the SoC FW, which will fill this in.
40		 *
41		 * Currently supported enable-method is psci v0.2
42		 */
43		cpu0: cpu@0 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53";
46			reg = <0x0>;
47			clocks = <&clockgen 1 0>;
48			next-level-cache = <&l2>;
49			cpu-idle-states = <&CPU_PH20>;
50			#cooling-cells = <2>;
51		};
52
53		cpu1: cpu@1 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a53";
56			reg = <0x1>;
57			clocks = <&clockgen 1 0>;
58			next-level-cache = <&l2>;
59			cpu-idle-states = <&CPU_PH20>;
60			#cooling-cells = <2>;
61		};
62
63		cpu2: cpu@2 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a53";
66			reg = <0x2>;
67			clocks = <&clockgen 1 0>;
68			next-level-cache = <&l2>;
69			cpu-idle-states = <&CPU_PH20>;
70			#cooling-cells = <2>;
71		};
72
73		cpu3: cpu@3 {
74			device_type = "cpu";
75			compatible = "arm,cortex-a53";
76			reg = <0x3>;
77			clocks = <&clockgen 1 0>;
78			next-level-cache = <&l2>;
79			cpu-idle-states = <&CPU_PH20>;
80			#cooling-cells = <2>;
81		};
82
83		l2: l2-cache {
84			compatible = "cache";
85		};
86	};
87
88	idle-states {
89		/*
90		 * PSCI node is not added default, U-boot will add missing
91		 * parts if it determines to use PSCI.
92		 */
93		entry-method = "psci";
94
95		CPU_PH20: cpu-ph20 {
96			compatible = "arm,idle-state";
97			idle-state-name = "PH20";
98			arm,psci-suspend-param = <0x0>;
99			entry-latency-us = <1000>;
100			exit-latency-us = <1000>;
101			min-residency-us = <3000>;
102		};
103	};
104
105	memory@80000000 {
106		device_type = "memory";
107		reg = <0x0 0x80000000 0 0x80000000>;
108		      /* DRAM space 1, size: 2GiB DRAM */
109	};
110
111	reserved-memory {
112		#address-cells = <2>;
113		#size-cells = <2>;
114		ranges;
115
116		bman_fbpr: bman-fbpr {
117			compatible = "shared-dma-pool";
118			size = <0 0x1000000>;
119			alignment = <0 0x1000000>;
120			no-map;
121		};
122
123		qman_fqd: qman-fqd {
124			compatible = "shared-dma-pool";
125			size = <0 0x400000>;
126			alignment = <0 0x400000>;
127			no-map;
128		};
129
130		qman_pfdr: qman-pfdr {
131			compatible = "shared-dma-pool";
132			size = <0 0x2000000>;
133			alignment = <0 0x2000000>;
134			no-map;
135		};
136	};
137
138	sysclk: sysclk {
139		compatible = "fixed-clock";
140		#clock-cells = <0>;
141		clock-frequency = <100000000>;
142		clock-output-names = "sysclk";
143	};
144
145	reboot {
146		compatible ="syscon-reboot";
147		regmap = <&dcfg>;
148		offset = <0xb0>;
149		mask = <0x02>;
150	};
151
152	thermal-zones {
153		ddr-controller {
154			polling-delay-passive = <1000>;
155			polling-delay = <5000>;
156			thermal-sensors = <&tmu 0>;
157
158			trips {
159				ddr-ctrler-alert {
160					temperature = <85000>;
161					hysteresis = <2000>;
162					type = "passive";
163				};
164
165				ddr-ctrler-crit {
166					temperature = <95000>;
167					hysteresis = <2000>;
168					type = "critical";
169				};
170			};
171		};
172
173		serdes {
174			polling-delay-passive = <1000>;
175			polling-delay = <5000>;
176			thermal-sensors = <&tmu 1>;
177
178			trips {
179				serdes-alert {
180					temperature = <85000>;
181					hysteresis = <2000>;
182					type = "passive";
183				};
184
185				serdes-crit {
186					temperature = <95000>;
187					hysteresis = <2000>;
188					type = "critical";
189				};
190			};
191		};
192
193		fman {
194			polling-delay-passive = <1000>;
195			polling-delay = <5000>;
196			thermal-sensors = <&tmu 2>;
197
198			trips {
199				fman-alert {
200					temperature = <85000>;
201					hysteresis = <2000>;
202					type = "passive";
203				};
204
205				fman-crit {
206					temperature = <95000>;
207					hysteresis = <2000>;
208					type = "critical";
209				};
210			};
211		};
212
213		core-cluster {
214			polling-delay-passive = <1000>;
215			polling-delay = <5000>;
216			thermal-sensors = <&tmu 3>;
217
218			trips {
219				core_cluster_alert: core-cluster-alert {
220					temperature = <85000>;
221					hysteresis = <2000>;
222					type = "passive";
223				};
224
225				core_cluster_crit: core-cluster-crit {
226					temperature = <95000>;
227					hysteresis = <2000>;
228					type = "critical";
229				};
230			};
231
232			cooling-maps {
233				map0 {
234					trip = <&core_cluster_alert>;
235					cooling-device =
236						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
237						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
238						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
239						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
240				};
241			};
242		};
243
244		sec {
245			polling-delay-passive = <1000>;
246			polling-delay = <5000>;
247			thermal-sensors = <&tmu 4>;
248
249			trips {
250				sec-alert {
251					temperature = <85000>;
252					hysteresis = <2000>;
253					type = "passive";
254				};
255
256				sec-crit {
257					temperature = <95000>;
258					hysteresis = <2000>;
259					type = "critical";
260				};
261			};
262		};
263	};
264
265	timer {
266		compatible = "arm,armv8-timer";
267		interrupts = <1 13 0xf08>, /* Physical Secure PPI */
268			     <1 14 0xf08>, /* Physical Non-Secure PPI */
269			     <1 11 0xf08>, /* Virtual PPI */
270			     <1 10 0xf08>; /* Hypervisor PPI */
271		fsl,erratum-a008585;
272	};
273
274	pmu {
275		compatible = "arm,armv8-pmuv3";
276		interrupts = <0 106 0x4>,
277			     <0 107 0x4>,
278			     <0 95 0x4>,
279			     <0 97 0x4>;
280		interrupt-affinity = <&cpu0>,
281				     <&cpu1>,
282				     <&cpu2>,
283				     <&cpu3>;
284	};
285
286	gic: interrupt-controller@1400000 {
287		compatible = "arm,gic-400";
288		#interrupt-cells = <3>;
289		interrupt-controller;
290		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
291		      <0x0 0x1402000 0 0x2000>, /* GICC */
292		      <0x0 0x1404000 0 0x2000>, /* GICH */
293		      <0x0 0x1406000 0 0x2000>; /* GICV */
294		interrupts = <1 9 0xf08>;
295	};
296
297	soc: soc {
298		compatible = "simple-bus";
299		#address-cells = <2>;
300		#size-cells = <2>;
301		ranges;
302
303		clockgen: clocking@1ee1000 {
304			compatible = "fsl,ls1043a-clockgen";
305			reg = <0x0 0x1ee1000 0x0 0x1000>;
306			#clock-cells = <2>;
307			clocks = <&sysclk>;
308		};
309
310		scfg: scfg@1570000 {
311			compatible = "fsl,ls1043a-scfg", "syscon";
312			reg = <0x0 0x1570000 0x0 0x10000>;
313			big-endian;
314		};
315
316		crypto: crypto@1700000 {
317			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
318				     "fsl,sec-v4.0";
319			fsl,sec-era = <3>;
320			#address-cells = <1>;
321			#size-cells = <1>;
322			ranges = <0x0 0x00 0x1700000 0x100000>;
323			reg = <0x00 0x1700000 0x0 0x100000>;
324			interrupts = <0 75 0x4>;
325
326			sec_jr0: jr@10000 {
327				compatible = "fsl,sec-v5.4-job-ring",
328					     "fsl,sec-v5.0-job-ring",
329					     "fsl,sec-v4.0-job-ring";
330				reg	   = <0x10000 0x10000>;
331				interrupts = <0 71 0x4>;
332			};
333
334			sec_jr1: jr@20000 {
335				compatible = "fsl,sec-v5.4-job-ring",
336					     "fsl,sec-v5.0-job-ring",
337					     "fsl,sec-v4.0-job-ring";
338				reg	   = <0x20000 0x10000>;
339				interrupts = <0 72 0x4>;
340			};
341
342			sec_jr2: jr@30000 {
343				compatible = "fsl,sec-v5.4-job-ring",
344					     "fsl,sec-v5.0-job-ring",
345					     "fsl,sec-v4.0-job-ring";
346				reg	   = <0x30000 0x10000>;
347				interrupts = <0 73 0x4>;
348			};
349
350			sec_jr3: jr@40000 {
351				compatible = "fsl,sec-v5.4-job-ring",
352					     "fsl,sec-v5.0-job-ring",
353					     "fsl,sec-v4.0-job-ring";
354				reg	   = <0x40000 0x10000>;
355				interrupts = <0 74 0x4>;
356			};
357		};
358
359		dcfg: dcfg@1ee0000 {
360			compatible = "fsl,ls1043a-dcfg", "syscon";
361			reg = <0x0 0x1ee0000 0x0 0x10000>;
362			big-endian;
363		};
364
365		ifc: ifc@1530000 {
366			compatible = "fsl,ifc", "simple-bus";
367			reg = <0x0 0x1530000 0x0 0x10000>;
368			interrupts = <0 43 0x4>;
369		};
370
371		qspi: spi@1550000 {
372			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
373			#address-cells = <1>;
374			#size-cells = <0>;
375			reg = <0x0 0x1550000 0x0 0x10000>,
376				<0x0 0x40000000 0x0 0x4000000>;
377			reg-names = "QuadSPI", "QuadSPI-memory";
378			interrupts = <0 99 0x4>;
379			clock-names = "qspi_en", "qspi";
380			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
381			status = "disabled";
382		};
383
384		esdhc: esdhc@1560000 {
385			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
386			reg = <0x0 0x1560000 0x0 0x10000>;
387			interrupts = <0 62 0x4>;
388			clock-frequency = <0>;
389			voltage-ranges = <1800 1800 3300 3300>;
390			sdhci,auto-cmd12;
391			big-endian;
392			bus-width = <4>;
393		};
394
395		ddr: memory-controller@1080000 {
396			compatible = "fsl,qoriq-memory-controller";
397			reg = <0x0 0x1080000 0x0 0x1000>;
398			interrupts = <0 144 0x4>;
399			big-endian;
400		};
401
402		tmu: tmu@1f00000 {
403			compatible = "fsl,qoriq-tmu";
404			reg = <0x0 0x1f00000 0x0 0x10000>;
405			interrupts = <0 33 0x4>;
406			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
407			fsl,tmu-calibration = <0x00000000 0x00000026
408					       0x00000001 0x0000002d
409					       0x00000002 0x00000032
410					       0x00000003 0x00000039
411					       0x00000004 0x0000003f
412					       0x00000005 0x00000046
413					       0x00000006 0x0000004d
414					       0x00000007 0x00000054
415					       0x00000008 0x0000005a
416					       0x00000009 0x00000061
417					       0x0000000a 0x0000006a
418					       0x0000000b 0x00000071
419
420					       0x00010000 0x00000025
421					       0x00010001 0x0000002c
422					       0x00010002 0x00000035
423					       0x00010003 0x0000003d
424					       0x00010004 0x00000045
425					       0x00010005 0x0000004e
426					       0x00010006 0x00000057
427					       0x00010007 0x00000061
428					       0x00010008 0x0000006b
429					       0x00010009 0x00000076
430
431					       0x00020000 0x00000029
432					       0x00020001 0x00000033
433					       0x00020002 0x0000003d
434					       0x00020003 0x00000049
435					       0x00020004 0x00000056
436					       0x00020005 0x00000061
437					       0x00020006 0x0000006d
438
439					       0x00030000 0x00000021
440					       0x00030001 0x0000002a
441					       0x00030002 0x0000003c
442					       0x00030003 0x0000004e>;
443			#thermal-sensor-cells = <1>;
444		};
445
446		qman: qman@1880000 {
447			compatible = "fsl,qman";
448			reg = <0x0 0x1880000 0x0 0x10000>;
449			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
450			memory-region = <&qman_fqd &qman_pfdr>;
451		};
452
453		bman: bman@1890000 {
454			compatible = "fsl,bman";
455			reg = <0x0 0x1890000 0x0 0x10000>;
456			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
457			memory-region = <&bman_fbpr>;
458		};
459
460		bportals: bman-portals@508000000 {
461			ranges = <0x0 0x5 0x08000000 0x8000000>;
462		};
463
464		qportals: qman-portals@500000000 {
465			ranges = <0x0 0x5 0x00000000 0x8000000>;
466		};
467
468		dspi0: spi@2100000 {
469			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
470			#address-cells = <1>;
471			#size-cells = <0>;
472			reg = <0x0 0x2100000 0x0 0x10000>;
473			interrupts = <0 64 0x4>;
474			clock-names = "dspi";
475			clocks = <&clockgen 4 0>;
476			spi-num-chipselects = <5>;
477			big-endian;
478			status = "disabled";
479		};
480
481		dspi1: spi@2110000 {
482			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
483			#address-cells = <1>;
484			#size-cells = <0>;
485			reg = <0x0 0x2110000 0x0 0x10000>;
486			interrupts = <0 65 0x4>;
487			clock-names = "dspi";
488			clocks = <&clockgen 4 0>;
489			spi-num-chipselects = <5>;
490			big-endian;
491			status = "disabled";
492		};
493
494		i2c0: i2c@2180000 {
495			compatible = "fsl,vf610-i2c";
496			#address-cells = <1>;
497			#size-cells = <0>;
498			reg = <0x0 0x2180000 0x0 0x10000>;
499			interrupts = <0 56 0x4>;
500			clock-names = "i2c";
501			clocks = <&clockgen 4 0>;
502			dmas = <&edma0 1 39>,
503			       <&edma0 1 38>;
504			dma-names = "tx", "rx";
505			status = "disabled";
506		};
507
508		i2c1: i2c@2190000 {
509			compatible = "fsl,vf610-i2c";
510			#address-cells = <1>;
511			#size-cells = <0>;
512			reg = <0x0 0x2190000 0x0 0x10000>;
513			interrupts = <0 57 0x4>;
514			clock-names = "i2c";
515			clocks = <&clockgen 4 0>;
516			status = "disabled";
517		};
518
519		i2c2: i2c@21a0000 {
520			compatible = "fsl,vf610-i2c";
521			#address-cells = <1>;
522			#size-cells = <0>;
523			reg = <0x0 0x21a0000 0x0 0x10000>;
524			interrupts = <0 58 0x4>;
525			clock-names = "i2c";
526			clocks = <&clockgen 4 0>;
527			status = "disabled";
528		};
529
530		i2c3: i2c@21b0000 {
531			compatible = "fsl,vf610-i2c";
532			#address-cells = <1>;
533			#size-cells = <0>;
534			reg = <0x0 0x21b0000 0x0 0x10000>;
535			interrupts = <0 59 0x4>;
536			clock-names = "i2c";
537			clocks = <&clockgen 4 0>;
538			status = "disabled";
539		};
540
541		duart0: serial@21c0500 {
542			compatible = "fsl,ns16550", "ns16550a";
543			reg = <0x00 0x21c0500 0x0 0x100>;
544			interrupts = <0 54 0x4>;
545			clocks = <&clockgen 4 0>;
546		};
547
548		duart1: serial@21c0600 {
549			compatible = "fsl,ns16550", "ns16550a";
550			reg = <0x00 0x21c0600 0x0 0x100>;
551			interrupts = <0 54 0x4>;
552			clocks = <&clockgen 4 0>;
553		};
554
555		duart2: serial@21d0500 {
556			compatible = "fsl,ns16550", "ns16550a";
557			reg = <0x0 0x21d0500 0x0 0x100>;
558			interrupts = <0 55 0x4>;
559			clocks = <&clockgen 4 0>;
560		};
561
562		duart3: serial@21d0600 {
563			compatible = "fsl,ns16550", "ns16550a";
564			reg = <0x0 0x21d0600 0x0 0x100>;
565			interrupts = <0 55 0x4>;
566			clocks = <&clockgen 4 0>;
567		};
568
569		gpio1: gpio@2300000 {
570			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
571			reg = <0x0 0x2300000 0x0 0x10000>;
572			interrupts = <0 66 0x4>;
573			gpio-controller;
574			#gpio-cells = <2>;
575			interrupt-controller;
576			#interrupt-cells = <2>;
577		};
578
579		gpio2: gpio@2310000 {
580			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
581			reg = <0x0 0x2310000 0x0 0x10000>;
582			interrupts = <0 67 0x4>;
583			gpio-controller;
584			#gpio-cells = <2>;
585			interrupt-controller;
586			#interrupt-cells = <2>;
587		};
588
589		gpio3: gpio@2320000 {
590			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
591			reg = <0x0 0x2320000 0x0 0x10000>;
592			interrupts = <0 68 0x4>;
593			gpio-controller;
594			#gpio-cells = <2>;
595			interrupt-controller;
596			#interrupt-cells = <2>;
597		};
598
599		gpio4: gpio@2330000 {
600			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
601			reg = <0x0 0x2330000 0x0 0x10000>;
602			interrupts = <0 134 0x4>;
603			gpio-controller;
604			#gpio-cells = <2>;
605			interrupt-controller;
606			#interrupt-cells = <2>;
607		};
608
609		uqe: uqe@2400000 {
610			#address-cells = <1>;
611			#size-cells = <1>;
612			compatible = "fsl,qe", "simple-bus";
613			ranges = <0x0 0x0 0x2400000 0x40000>;
614			reg = <0x0 0x2400000 0x0 0x480>;
615			brg-frequency = <100000000>;
616			bus-frequency = <200000000>;
617			fsl,qe-num-riscs = <1>;
618			fsl,qe-num-snums = <28>;
619
620			qeic: qeic@80 {
621				compatible = "fsl,qe-ic";
622				reg = <0x80 0x80>;
623				#address-cells = <0>;
624				interrupt-controller;
625				#interrupt-cells = <1>;
626				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
627					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
628			};
629
630			si1: si@700 {
631				#address-cells = <1>;
632				#size-cells = <0>;
633				compatible = "fsl,ls1043-qe-si",
634						"fsl,t1040-qe-si";
635				reg = <0x700 0x80>;
636			};
637
638			siram1: siram@1000 {
639				#address-cells = <1>;
640				#size-cells = <1>;
641				compatible = "fsl,ls1043-qe-siram",
642						"fsl,t1040-qe-siram";
643				reg = <0x1000 0x800>;
644			};
645
646			ucc@2000 {
647				cell-index = <1>;
648				reg = <0x2000 0x200>;
649				interrupts = <32>;
650				interrupt-parent = <&qeic>;
651			};
652
653			ucc@2200 {
654				cell-index = <3>;
655				reg = <0x2200 0x200>;
656				interrupts = <34>;
657				interrupt-parent = <&qeic>;
658			};
659
660			muram@10000 {
661				#address-cells = <1>;
662				#size-cells = <1>;
663				compatible = "fsl,qe-muram", "fsl,cpm-muram";
664				ranges = <0x0 0x10000 0x6000>;
665
666				data-only@0 {
667					compatible = "fsl,qe-muram-data",
668					"fsl,cpm-muram-data";
669					reg = <0x0 0x6000>;
670				};
671			};
672		};
673
674		lpuart0: serial@2950000 {
675			compatible = "fsl,ls1021a-lpuart";
676			reg = <0x0 0x2950000 0x0 0x1000>;
677			interrupts = <0 48 0x4>;
678			clocks = <&clockgen 0 0>;
679			clock-names = "ipg";
680			status = "disabled";
681		};
682
683		lpuart1: serial@2960000 {
684			compatible = "fsl,ls1021a-lpuart";
685			reg = <0x0 0x2960000 0x0 0x1000>;
686			interrupts = <0 49 0x4>;
687			clocks = <&clockgen 4 0>;
688			clock-names = "ipg";
689			status = "disabled";
690		};
691
692		lpuart2: serial@2970000 {
693			compatible = "fsl,ls1021a-lpuart";
694			reg = <0x0 0x2970000 0x0 0x1000>;
695			interrupts = <0 50 0x4>;
696			clocks = <&clockgen 4 0>;
697			clock-names = "ipg";
698			status = "disabled";
699		};
700
701		lpuart3: serial@2980000 {
702			compatible = "fsl,ls1021a-lpuart";
703			reg = <0x0 0x2980000 0x0 0x1000>;
704			interrupts = <0 51 0x4>;
705			clocks = <&clockgen 4 0>;
706			clock-names = "ipg";
707			status = "disabled";
708		};
709
710		lpuart4: serial@2990000 {
711			compatible = "fsl,ls1021a-lpuart";
712			reg = <0x0 0x2990000 0x0 0x1000>;
713			interrupts = <0 52 0x4>;
714			clocks = <&clockgen 4 0>;
715			clock-names = "ipg";
716			status = "disabled";
717		};
718
719		lpuart5: serial@29a0000 {
720			compatible = "fsl,ls1021a-lpuart";
721			reg = <0x0 0x29a0000 0x0 0x1000>;
722			interrupts = <0 53 0x4>;
723			clocks = <&clockgen 4 0>;
724			clock-names = "ipg";
725			status = "disabled";
726		};
727
728		wdog0: wdog@2ad0000 {
729			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
730			reg = <0x0 0x2ad0000 0x0 0x10000>;
731			interrupts = <0 83 0x4>;
732			clocks = <&clockgen 4 0>;
733			clock-names = "wdog";
734			big-endian;
735		};
736
737		edma0: edma@2c00000 {
738			#dma-cells = <2>;
739			compatible = "fsl,vf610-edma";
740			reg = <0x0 0x2c00000 0x0 0x10000>,
741			      <0x0 0x2c10000 0x0 0x10000>,
742			      <0x0 0x2c20000 0x0 0x10000>;
743			interrupts = <0 103 0x4>,
744				     <0 103 0x4>;
745			interrupt-names = "edma-tx", "edma-err";
746			dma-channels = <32>;
747			big-endian;
748			clock-names = "dmamux0", "dmamux1";
749			clocks = <&clockgen 4 0>,
750				 <&clockgen 4 0>;
751		};
752
753		usb0: usb3@2f00000 {
754			compatible = "snps,dwc3";
755			reg = <0x0 0x2f00000 0x0 0x10000>;
756			interrupts = <0 60 0x4>;
757			dr_mode = "host";
758			snps,quirk-frame-length-adjustment = <0x20>;
759			snps,dis_rxdet_inp3_quirk;
760			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
761			status = "disabled";
762		};
763
764		usb1: usb3@3000000 {
765			compatible = "snps,dwc3";
766			reg = <0x0 0x3000000 0x0 0x10000>;
767			interrupts = <0 61 0x4>;
768			dr_mode = "host";
769			snps,quirk-frame-length-adjustment = <0x20>;
770			snps,dis_rxdet_inp3_quirk;
771			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
772			status = "disabled";
773		};
774
775		usb2: usb3@3100000 {
776			compatible = "snps,dwc3";
777			reg = <0x0 0x3100000 0x0 0x10000>;
778			interrupts = <0 63 0x4>;
779			dr_mode = "host";
780			snps,quirk-frame-length-adjustment = <0x20>;
781			snps,dis_rxdet_inp3_quirk;
782			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
783			status = "disabled";
784		};
785
786		sata: sata@3200000 {
787			compatible = "fsl,ls1043a-ahci";
788			reg = <0x0 0x3200000 0x0 0x10000>,
789				<0x0 0x20140520 0x0 0x4>;
790			reg-names = "ahci", "sata-ecc";
791			interrupts = <0 69 0x4>;
792			clocks = <&clockgen 4 0>;
793			dma-coherent;
794		};
795
796		msi1: msi-controller1@1571000 {
797			compatible = "fsl,ls1043a-msi";
798			reg = <0x0 0x1571000 0x0 0x8>;
799			msi-controller;
800			interrupts = <0 116 0x4>;
801		};
802
803		msi2: msi-controller2@1572000 {
804			compatible = "fsl,ls1043a-msi";
805			reg = <0x0 0x1572000 0x0 0x8>;
806			msi-controller;
807			interrupts = <0 126 0x4>;
808		};
809
810		msi3: msi-controller3@1573000 {
811			compatible = "fsl,ls1043a-msi";
812			reg = <0x0 0x1573000 0x0 0x8>;
813			msi-controller;
814			interrupts = <0 160 0x4>;
815		};
816
817		pcie1: pcie@3400000 {
818			compatible = "fsl,ls1043a-pcie";
819			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
820			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
821			reg-names = "regs", "config";
822			interrupts = <0 118 0x4>, /* controller interrupt */
823				     <0 117 0x4>; /* PME interrupt */
824			interrupt-names = "intr", "pme";
825			#address-cells = <3>;
826			#size-cells = <2>;
827			device_type = "pci";
828			dma-coherent;
829			num-viewport = <6>;
830			bus-range = <0x0 0xff>;
831			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
832				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
833			msi-parent = <&msi1>, <&msi2>, <&msi3>;
834			#interrupt-cells = <1>;
835			interrupt-map-mask = <0 0 0 7>;
836			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
837					<0000 0 0 2 &gic 0 111 0x4>,
838					<0000 0 0 3 &gic 0 112 0x4>,
839					<0000 0 0 4 &gic 0 113 0x4>;
840			status = "disabled";
841		};
842
843		pcie2: pcie@3500000 {
844			compatible = "fsl,ls1043a-pcie";
845			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
846			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
847			reg-names = "regs", "config";
848			interrupts = <0 128 0x4>,
849				     <0 127 0x4>;
850			interrupt-names = "intr", "pme";
851			#address-cells = <3>;
852			#size-cells = <2>;
853			device_type = "pci";
854			dma-coherent;
855			num-viewport = <6>;
856			bus-range = <0x0 0xff>;
857			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
858				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
859			msi-parent = <&msi1>, <&msi2>, <&msi3>;
860			#interrupt-cells = <1>;
861			interrupt-map-mask = <0 0 0 7>;
862			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
863					<0000 0 0 2 &gic 0 121 0x4>,
864					<0000 0 0 3 &gic 0 122 0x4>,
865					<0000 0 0 4 &gic 0 123 0x4>;
866			status = "disabled";
867		};
868
869		pcie3: pcie@3600000 {
870			compatible = "fsl,ls1043a-pcie";
871			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
872			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
873			reg-names = "regs", "config";
874			interrupts = <0 162 0x4>,
875				     <0 161 0x4>;
876			interrupt-names = "intr", "pme";
877			#address-cells = <3>;
878			#size-cells = <2>;
879			device_type = "pci";
880			dma-coherent;
881			num-viewport = <6>;
882			bus-range = <0x0 0xff>;
883			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
884				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
885			msi-parent = <&msi1>, <&msi2>, <&msi3>;
886			#interrupt-cells = <1>;
887			interrupt-map-mask = <0 0 0 7>;
888			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
889					<0000 0 0 2 &gic 0 155 0x4>,
890					<0000 0 0 3 &gic 0 156 0x4>,
891					<0000 0 0 4 &gic 0 157 0x4>;
892			status = "disabled";
893		};
894
895		qdma: dma-controller@8380000 {
896			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
897			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
898			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
899			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
900			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
901				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
902				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
903				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
904				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
905			interrupt-names = "qdma-error", "qdma-queue0",
906				"qdma-queue1", "qdma-queue2", "qdma-queue3";
907			dma-channels = <8>;
908			block-number = <1>;
909			block-offset = <0x10000>;
910			fsl,dma-queues = <2>;
911			status-sizes = <64>;
912			queue-sizes = <64 64>;
913			big-endian;
914		};
915
916		rcpm: power-controller@1ee2140 {
917			compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
918			reg = <0x0 0x1ee2140 0x0 0x4>;
919			#fsl,rcpm-wakeup-cells = <1>;
920		};
921
922		ftm_alarm0: timer@29d0000 {
923			compatible = "fsl,ls1043a-ftm-alarm";
924			reg = <0x0 0x29d0000 0x0 0x10000>;
925			fsl,rcpm-wakeup = <&rcpm 0x20000>;
926			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
927			big-endian;
928		};
929	};
930
931	firmware {
932		optee {
933			compatible = "linaro,optee-tz";
934			method = "smc";
935		};
936	};
937
938};
939
940#include "qoriq-qman-portals.dtsi"
941#include "qoriq-bman-portals.dtsi"
942