1/* 2 * Device Tree Include file for Freescale Layerscape-1043A family SoC. 3 * 4 * Copyright 2014-2015, Freescale Semiconductor 5 * 6 * Mingkai Hu <Mingkai.hu@freescale.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPLv2 or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This library is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This library is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47/ { 48 compatible = "fsl,ls1043a"; 49 interrupt-parent = <&gic>; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 /* 58 * We expect the enable-method for cpu's to be "psci", but this 59 * is dependent on the SoC FW, which will fill this in. 60 * 61 * Currently supported enable-method is psci v0.2 62 */ 63 cpu0: cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x0>; 67 clocks = <&clockgen 1 0>; 68 next-level-cache = <&l2>; 69 }; 70 71 cpu1: cpu@1 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x1>; 75 clocks = <&clockgen 1 0>; 76 next-level-cache = <&l2>; 77 }; 78 79 cpu2: cpu@2 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x2>; 83 clocks = <&clockgen 1 0>; 84 next-level-cache = <&l2>; 85 }; 86 87 cpu3: cpu@3 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x3>; 91 clocks = <&clockgen 1 0>; 92 next-level-cache = <&l2>; 93 }; 94 95 l2: l2-cache { 96 compatible = "cache"; 97 }; 98 }; 99 100 memory@80000000 { 101 device_type = "memory"; 102 reg = <0x0 0x80000000 0 0x80000000>; 103 /* DRAM space 1, size: 2GiB DRAM */ 104 }; 105 106 sysclk: sysclk { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 clock-frequency = <100000000>; 110 clock-output-names = "sysclk"; 111 }; 112 113 reboot { 114 compatible ="syscon-reboot"; 115 regmap = <&dcfg>; 116 offset = <0xb0>; 117 mask = <0x02>; 118 }; 119 120 timer { 121 compatible = "arm,armv8-timer"; 122 interrupts = <1 13 0xf08>, /* Physical Secure PPI */ 123 <1 14 0xf08>, /* Physical Non-Secure PPI */ 124 <1 11 0xf08>, /* Virtual PPI */ 125 <1 10 0xf08>; /* Hypervisor PPI */ 126 fsl,erratum-a008585; 127 }; 128 129 pmu { 130 compatible = "arm,armv8-pmuv3"; 131 interrupts = <0 106 0x4>, 132 <0 107 0x4>, 133 <0 95 0x4>, 134 <0 97 0x4>; 135 interrupt-affinity = <&cpu0>, 136 <&cpu1>, 137 <&cpu2>, 138 <&cpu3>; 139 }; 140 141 gic: interrupt-controller@1400000 { 142 compatible = "arm,gic-400"; 143 #interrupt-cells = <3>; 144 interrupt-controller; 145 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 146 <0x0 0x1402000 0 0x2000>, /* GICC */ 147 <0x0 0x1404000 0 0x2000>, /* GICH */ 148 <0x0 0x1406000 0 0x2000>; /* GICV */ 149 interrupts = <1 9 0xf08>; 150 }; 151 152 soc { 153 compatible = "simple-bus"; 154 #address-cells = <2>; 155 #size-cells = <2>; 156 ranges; 157 158 clockgen: clocking@1ee1000 { 159 compatible = "fsl,ls1043a-clockgen"; 160 reg = <0x0 0x1ee1000 0x0 0x1000>; 161 #clock-cells = <2>; 162 clocks = <&sysclk>; 163 }; 164 165 scfg: scfg@1570000 { 166 compatible = "fsl,ls1043a-scfg", "syscon"; 167 reg = <0x0 0x1570000 0x0 0x10000>; 168 big-endian; 169 }; 170 171 crypto: crypto@1700000 { 172 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 173 "fsl,sec-v4.0"; 174 fsl,sec-era = <3>; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 ranges = <0x0 0x00 0x1700000 0x100000>; 178 reg = <0x00 0x1700000 0x0 0x100000>; 179 interrupts = <0 75 0x4>; 180 181 sec_jr0: jr@10000 { 182 compatible = "fsl,sec-v5.4-job-ring", 183 "fsl,sec-v5.0-job-ring", 184 "fsl,sec-v4.0-job-ring"; 185 reg = <0x10000 0x10000>; 186 interrupts = <0 71 0x4>; 187 }; 188 189 sec_jr1: jr@20000 { 190 compatible = "fsl,sec-v5.4-job-ring", 191 "fsl,sec-v5.0-job-ring", 192 "fsl,sec-v4.0-job-ring"; 193 reg = <0x20000 0x10000>; 194 interrupts = <0 72 0x4>; 195 }; 196 197 sec_jr2: jr@30000 { 198 compatible = "fsl,sec-v5.4-job-ring", 199 "fsl,sec-v5.0-job-ring", 200 "fsl,sec-v4.0-job-ring"; 201 reg = <0x30000 0x10000>; 202 interrupts = <0 73 0x4>; 203 }; 204 205 sec_jr3: jr@40000 { 206 compatible = "fsl,sec-v5.4-job-ring", 207 "fsl,sec-v5.0-job-ring", 208 "fsl,sec-v4.0-job-ring"; 209 reg = <0x40000 0x10000>; 210 interrupts = <0 74 0x4>; 211 }; 212 }; 213 214 dcfg: dcfg@1ee0000 { 215 compatible = "fsl,ls1043a-dcfg", "syscon"; 216 reg = <0x0 0x1ee0000 0x0 0x10000>; 217 big-endian; 218 }; 219 220 ifc: ifc@1530000 { 221 compatible = "fsl,ifc", "simple-bus"; 222 reg = <0x0 0x1530000 0x0 0x10000>; 223 interrupts = <0 43 0x4>; 224 }; 225 226 qspi: quadspi@1550000 { 227 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 reg = <0x0 0x1550000 0x0 0x10000>, 231 <0x0 0x40000000 0x0 0x4000000>; 232 reg-names = "QuadSPI", "QuadSPI-memory"; 233 interrupts = <0 99 0x4>; 234 clock-names = "qspi_en", "qspi"; 235 clocks = <&clockgen 4 0>, <&clockgen 4 0>; 236 big-endian; 237 status = "disabled"; 238 }; 239 240 esdhc: esdhc@1560000 { 241 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; 242 reg = <0x0 0x1560000 0x0 0x10000>; 243 interrupts = <0 62 0x4>; 244 clock-frequency = <0>; 245 voltage-ranges = <1800 1800 3300 3300>; 246 sdhci,auto-cmd12; 247 big-endian; 248 bus-width = <4>; 249 }; 250 251 ddr: memory-controller@1080000 { 252 compatible = "fsl,qoriq-memory-controller"; 253 reg = <0x0 0x1080000 0x0 0x1000>; 254 interrupts = <0 144 0x4>; 255 big-endian; 256 }; 257 258 dspi0: dspi@2100000 { 259 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 reg = <0x0 0x2100000 0x0 0x10000>; 263 interrupts = <0 64 0x4>; 264 clock-names = "dspi"; 265 clocks = <&clockgen 4 0>; 266 spi-num-chipselects = <5>; 267 big-endian; 268 status = "disabled"; 269 }; 270 271 dspi1: dspi@2110000 { 272 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 reg = <0x0 0x2110000 0x0 0x10000>; 276 interrupts = <0 65 0x4>; 277 clock-names = "dspi"; 278 clocks = <&clockgen 4 0>; 279 spi-num-chipselects = <5>; 280 big-endian; 281 status = "disabled"; 282 }; 283 284 i2c0: i2c@2180000 { 285 compatible = "fsl,vf610-i2c"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 reg = <0x0 0x2180000 0x0 0x10000>; 289 interrupts = <0 56 0x4>; 290 clock-names = "i2c"; 291 clocks = <&clockgen 4 0>; 292 dmas = <&edma0 1 39>, 293 <&edma0 1 38>; 294 dma-names = "tx", "rx"; 295 status = "disabled"; 296 }; 297 298 i2c1: i2c@2190000 { 299 compatible = "fsl,vf610-i2c"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 reg = <0x0 0x2190000 0x0 0x10000>; 303 interrupts = <0 57 0x4>; 304 clock-names = "i2c"; 305 clocks = <&clockgen 4 0>; 306 status = "disabled"; 307 }; 308 309 i2c2: i2c@21a0000 { 310 compatible = "fsl,vf610-i2c"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 reg = <0x0 0x21a0000 0x0 0x10000>; 314 interrupts = <0 58 0x4>; 315 clock-names = "i2c"; 316 clocks = <&clockgen 4 0>; 317 status = "disabled"; 318 }; 319 320 i2c3: i2c@21b0000 { 321 compatible = "fsl,vf610-i2c"; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 reg = <0x0 0x21b0000 0x0 0x10000>; 325 interrupts = <0 59 0x4>; 326 clock-names = "i2c"; 327 clocks = <&clockgen 4 0>; 328 status = "disabled"; 329 }; 330 331 duart0: serial@21c0500 { 332 compatible = "fsl,ns16550", "ns16550a"; 333 reg = <0x00 0x21c0500 0x0 0x100>; 334 interrupts = <0 54 0x4>; 335 clocks = <&clockgen 4 0>; 336 }; 337 338 duart1: serial@21c0600 { 339 compatible = "fsl,ns16550", "ns16550a"; 340 reg = <0x00 0x21c0600 0x0 0x100>; 341 interrupts = <0 54 0x4>; 342 clocks = <&clockgen 4 0>; 343 }; 344 345 duart2: serial@21d0500 { 346 compatible = "fsl,ns16550", "ns16550a"; 347 reg = <0x0 0x21d0500 0x0 0x100>; 348 interrupts = <0 55 0x4>; 349 clocks = <&clockgen 4 0>; 350 }; 351 352 duart3: serial@21d0600 { 353 compatible = "fsl,ns16550", "ns16550a"; 354 reg = <0x0 0x21d0600 0x0 0x100>; 355 interrupts = <0 55 0x4>; 356 clocks = <&clockgen 4 0>; 357 }; 358 359 gpio1: gpio@2300000 { 360 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 361 reg = <0x0 0x2300000 0x0 0x10000>; 362 interrupts = <0 66 0x4>; 363 gpio-controller; 364 #gpio-cells = <2>; 365 interrupt-controller; 366 #interrupt-cells = <2>; 367 }; 368 369 gpio2: gpio@2310000 { 370 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 371 reg = <0x0 0x2310000 0x0 0x10000>; 372 interrupts = <0 67 0x4>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 }; 378 379 gpio3: gpio@2320000 { 380 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 381 reg = <0x0 0x2320000 0x0 0x10000>; 382 interrupts = <0 68 0x4>; 383 gpio-controller; 384 #gpio-cells = <2>; 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 }; 388 389 gpio4: gpio@2330000 { 390 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 391 reg = <0x0 0x2330000 0x0 0x10000>; 392 interrupts = <0 134 0x4>; 393 gpio-controller; 394 #gpio-cells = <2>; 395 interrupt-controller; 396 #interrupt-cells = <2>; 397 }; 398 399 lpuart0: serial@2950000 { 400 compatible = "fsl,ls1021a-lpuart"; 401 reg = <0x0 0x2950000 0x0 0x1000>; 402 interrupts = <0 48 0x4>; 403 clocks = <&clockgen 0 0>; 404 clock-names = "ipg"; 405 status = "disabled"; 406 }; 407 408 lpuart1: serial@2960000 { 409 compatible = "fsl,ls1021a-lpuart"; 410 reg = <0x0 0x2960000 0x0 0x1000>; 411 interrupts = <0 49 0x4>; 412 clocks = <&clockgen 4 0>; 413 clock-names = "ipg"; 414 status = "disabled"; 415 }; 416 417 lpuart2: serial@2970000 { 418 compatible = "fsl,ls1021a-lpuart"; 419 reg = <0x0 0x2970000 0x0 0x1000>; 420 interrupts = <0 50 0x4>; 421 clocks = <&clockgen 4 0>; 422 clock-names = "ipg"; 423 status = "disabled"; 424 }; 425 426 lpuart3: serial@2980000 { 427 compatible = "fsl,ls1021a-lpuart"; 428 reg = <0x0 0x2980000 0x0 0x1000>; 429 interrupts = <0 51 0x4>; 430 clocks = <&clockgen 4 0>; 431 clock-names = "ipg"; 432 status = "disabled"; 433 }; 434 435 lpuart4: serial@2990000 { 436 compatible = "fsl,ls1021a-lpuart"; 437 reg = <0x0 0x2990000 0x0 0x1000>; 438 interrupts = <0 52 0x4>; 439 clocks = <&clockgen 4 0>; 440 clock-names = "ipg"; 441 status = "disabled"; 442 }; 443 444 lpuart5: serial@29a0000 { 445 compatible = "fsl,ls1021a-lpuart"; 446 reg = <0x0 0x29a0000 0x0 0x1000>; 447 interrupts = <0 53 0x4>; 448 clocks = <&clockgen 4 0>; 449 clock-names = "ipg"; 450 status = "disabled"; 451 }; 452 453 wdog0: wdog@2ad0000 { 454 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; 455 reg = <0x0 0x2ad0000 0x0 0x10000>; 456 interrupts = <0 83 0x4>; 457 clocks = <&clockgen 4 0>; 458 clock-names = "wdog"; 459 big-endian; 460 }; 461 462 edma0: edma@2c00000 { 463 #dma-cells = <2>; 464 compatible = "fsl,vf610-edma"; 465 reg = <0x0 0x2c00000 0x0 0x10000>, 466 <0x0 0x2c10000 0x0 0x10000>, 467 <0x0 0x2c20000 0x0 0x10000>; 468 interrupts = <0 103 0x4>, 469 <0 103 0x4>; 470 interrupt-names = "edma-tx", "edma-err"; 471 dma-channels = <32>; 472 big-endian; 473 clock-names = "dmamux0", "dmamux1"; 474 clocks = <&clockgen 4 0>, 475 <&clockgen 4 0>; 476 }; 477 478 usb0: usb3@2f00000 { 479 compatible = "snps,dwc3"; 480 reg = <0x0 0x2f00000 0x0 0x10000>; 481 interrupts = <0 60 0x4>; 482 dr_mode = "host"; 483 snps,quirk-frame-length-adjustment = <0x20>; 484 snps,dis_rxdet_inp3_quirk; 485 }; 486 487 usb1: usb3@3000000 { 488 compatible = "snps,dwc3"; 489 reg = <0x0 0x3000000 0x0 0x10000>; 490 interrupts = <0 61 0x4>; 491 dr_mode = "host"; 492 snps,quirk-frame-length-adjustment = <0x20>; 493 snps,dis_rxdet_inp3_quirk; 494 }; 495 496 usb2: usb3@3100000 { 497 compatible = "snps,dwc3"; 498 reg = <0x0 0x3100000 0x0 0x10000>; 499 interrupts = <0 63 0x4>; 500 dr_mode = "host"; 501 snps,quirk-frame-length-adjustment = <0x20>; 502 snps,dis_rxdet_inp3_quirk; 503 }; 504 505 sata: sata@3200000 { 506 compatible = "fsl,ls1043a-ahci"; 507 reg = <0x0 0x3200000 0x0 0x10000>; 508 interrupts = <0 69 0x4>; 509 clocks = <&clockgen 4 0>; 510 dma-coherent; 511 }; 512 513 msi1: msi-controller1@1571000 { 514 compatible = "fsl,1s1043a-msi"; 515 reg = <0x0 0x1571000 0x0 0x8>; 516 msi-controller; 517 interrupts = <0 116 0x4>; 518 }; 519 520 msi2: msi-controller2@1572000 { 521 compatible = "fsl,1s1043a-msi"; 522 reg = <0x0 0x1572000 0x0 0x8>; 523 msi-controller; 524 interrupts = <0 126 0x4>; 525 }; 526 527 msi3: msi-controller3@1573000 { 528 compatible = "fsl,1s1043a-msi"; 529 reg = <0x0 0x1573000 0x0 0x8>; 530 msi-controller; 531 interrupts = <0 160 0x4>; 532 }; 533 534 pcie@3400000 { 535 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; 536 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 537 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 538 reg-names = "regs", "config"; 539 interrupts = <0 118 0x4>, /* controller interrupt */ 540 <0 117 0x4>; /* PME interrupt */ 541 interrupt-names = "intr", "pme"; 542 #address-cells = <3>; 543 #size-cells = <2>; 544 device_type = "pci"; 545 dma-coherent; 546 num-lanes = <4>; 547 bus-range = <0x0 0xff>; 548 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 549 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 550 msi-parent = <&msi1>; 551 #interrupt-cells = <1>; 552 interrupt-map-mask = <0 0 0 7>; 553 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, 554 <0000 0 0 2 &gic 0 111 0x4>, 555 <0000 0 0 3 &gic 0 112 0x4>, 556 <0000 0 0 4 &gic 0 113 0x4>; 557 }; 558 559 pcie@3500000 { 560 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; 561 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 562 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 563 reg-names = "regs", "config"; 564 interrupts = <0 128 0x4>, 565 <0 127 0x4>; 566 interrupt-names = "intr", "pme"; 567 #address-cells = <3>; 568 #size-cells = <2>; 569 device_type = "pci"; 570 dma-coherent; 571 num-lanes = <2>; 572 bus-range = <0x0 0xff>; 573 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 574 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 575 msi-parent = <&msi2>; 576 #interrupt-cells = <1>; 577 interrupt-map-mask = <0 0 0 7>; 578 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, 579 <0000 0 0 2 &gic 0 121 0x4>, 580 <0000 0 0 3 &gic 0 122 0x4>, 581 <0000 0 0 4 &gic 0 123 0x4>; 582 }; 583 584 pcie@3600000 { 585 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; 586 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 587 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 588 reg-names = "regs", "config"; 589 interrupts = <0 162 0x4>, 590 <0 161 0x4>; 591 interrupt-names = "intr", "pme"; 592 #address-cells = <3>; 593 #size-cells = <2>; 594 device_type = "pci"; 595 dma-coherent; 596 num-lanes = <2>; 597 bus-range = <0x0 0xff>; 598 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 599 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 600 msi-parent = <&msi3>; 601 #interrupt-cells = <1>; 602 interrupt-map-mask = <0 0 0 7>; 603 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, 604 <0000 0 0 2 &gic 0 155 0x4>, 605 <0000 0 0 3 &gic 0 156 0x4>, 606 <0000 0 0 4 &gic 0 157 0x4>; 607 }; 608 }; 609 610}; 611