1/*
2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
3 *
4 * Copyright 2014-2015, Freescale Semiconductor
5 *
6 * Mingkai Hu <Mingkai.hu@freescale.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 *  a) This library is free software; you can redistribute it and/or
14 *     modify it under the terms of the GNU General Public License as
15 *     published by the Free Software Foundation; either version 2 of the
16 *     License, or (at your option) any later version.
17 *
18 *     This library is distributed in the hope that it will be useful,
19 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
20 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21 *     GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 *  b) Permission is hereby granted, free of charge, to any person
26 *     obtaining a copy of this software and associated documentation
27 *     files (the "Software"), to deal in the Software without
28 *     restriction, including without limitation the rights to use,
29 *     copy, modify, merge, publish, distribute, sublicense, and/or
30 *     sell copies of the Software, and to permit persons to whom the
31 *     Software is furnished to do so, subject to the following
32 *     conditions:
33 *
34 *     The above copyright notice and this permission notice shall be
35 *     included in all copies or substantial portions of the Software.
36 *
37 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 *     OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include <dt-bindings/thermal/thermal.h>
48
49/ {
50	compatible = "fsl,ls1043a";
51	interrupt-parent = <&gic>;
52	#address-cells = <2>;
53	#size-cells = <2>;
54
55	cpus {
56		#address-cells = <1>;
57		#size-cells = <0>;
58
59		/*
60		 * We expect the enable-method for cpu's to be "psci", but this
61		 * is dependent on the SoC FW, which will fill this in.
62		 *
63		 * Currently supported enable-method is psci v0.2
64		 */
65		cpu0: cpu@0 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53";
68			reg = <0x0>;
69			clocks = <&clockgen 1 0>;
70			next-level-cache = <&l2>;
71			#cooling-cells = <2>;
72		};
73
74		cpu1: cpu@1 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53";
77			reg = <0x1>;
78			clocks = <&clockgen 1 0>;
79			next-level-cache = <&l2>;
80		};
81
82		cpu2: cpu@2 {
83			device_type = "cpu";
84			compatible = "arm,cortex-a53";
85			reg = <0x2>;
86			clocks = <&clockgen 1 0>;
87			next-level-cache = <&l2>;
88		};
89
90		cpu3: cpu@3 {
91			device_type = "cpu";
92			compatible = "arm,cortex-a53";
93			reg = <0x3>;
94			clocks = <&clockgen 1 0>;
95			next-level-cache = <&l2>;
96		};
97
98		l2: l2-cache {
99			compatible = "cache";
100		};
101	};
102
103	memory@80000000 {
104		device_type = "memory";
105		reg = <0x0 0x80000000 0 0x80000000>;
106		      /* DRAM space 1, size: 2GiB DRAM */
107	};
108
109	sysclk: sysclk {
110		compatible = "fixed-clock";
111		#clock-cells = <0>;
112		clock-frequency = <100000000>;
113		clock-output-names = "sysclk";
114	};
115
116	reboot {
117		compatible ="syscon-reboot";
118		regmap = <&dcfg>;
119		offset = <0xb0>;
120		mask = <0x02>;
121	};
122
123	timer {
124		compatible = "arm,armv8-timer";
125		interrupts = <1 13 0xf08>, /* Physical Secure PPI */
126			     <1 14 0xf08>, /* Physical Non-Secure PPI */
127			     <1 11 0xf08>, /* Virtual PPI */
128			     <1 10 0xf08>; /* Hypervisor PPI */
129		fsl,erratum-a008585;
130	};
131
132	pmu {
133		compatible = "arm,armv8-pmuv3";
134		interrupts = <0 106 0x4>,
135			     <0 107 0x4>,
136			     <0 95 0x4>,
137			     <0 97 0x4>;
138		interrupt-affinity = <&cpu0>,
139				     <&cpu1>,
140				     <&cpu2>,
141				     <&cpu3>;
142	};
143
144	gic: interrupt-controller@1400000 {
145		compatible = "arm,gic-400";
146		#interrupt-cells = <3>;
147		interrupt-controller;
148		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
149		      <0x0 0x1402000 0 0x2000>, /* GICC */
150		      <0x0 0x1404000 0 0x2000>, /* GICH */
151		      <0x0 0x1406000 0 0x2000>; /* GICV */
152		interrupts = <1 9 0xf08>;
153	};
154
155	soc {
156		compatible = "simple-bus";
157		#address-cells = <2>;
158		#size-cells = <2>;
159		ranges;
160
161		clockgen: clocking@1ee1000 {
162			compatible = "fsl,ls1043a-clockgen";
163			reg = <0x0 0x1ee1000 0x0 0x1000>;
164			#clock-cells = <2>;
165			clocks = <&sysclk>;
166		};
167
168		scfg: scfg@1570000 {
169			compatible = "fsl,ls1043a-scfg", "syscon";
170			reg = <0x0 0x1570000 0x0 0x10000>;
171			big-endian;
172		};
173
174		crypto: crypto@1700000 {
175			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
176				     "fsl,sec-v4.0";
177			fsl,sec-era = <3>;
178			#address-cells = <1>;
179			#size-cells = <1>;
180			ranges = <0x0 0x00 0x1700000 0x100000>;
181			reg = <0x00 0x1700000 0x0 0x100000>;
182			interrupts = <0 75 0x4>;
183
184			sec_jr0: jr@10000 {
185				compatible = "fsl,sec-v5.4-job-ring",
186					     "fsl,sec-v5.0-job-ring",
187					     "fsl,sec-v4.0-job-ring";
188				reg	   = <0x10000 0x10000>;
189				interrupts = <0 71 0x4>;
190			};
191
192			sec_jr1: jr@20000 {
193				compatible = "fsl,sec-v5.4-job-ring",
194					     "fsl,sec-v5.0-job-ring",
195					     "fsl,sec-v4.0-job-ring";
196				reg	   = <0x20000 0x10000>;
197				interrupts = <0 72 0x4>;
198			};
199
200			sec_jr2: jr@30000 {
201				compatible = "fsl,sec-v5.4-job-ring",
202					     "fsl,sec-v5.0-job-ring",
203					     "fsl,sec-v4.0-job-ring";
204				reg	   = <0x30000 0x10000>;
205				interrupts = <0 73 0x4>;
206			};
207
208			sec_jr3: jr@40000 {
209				compatible = "fsl,sec-v5.4-job-ring",
210					     "fsl,sec-v5.0-job-ring",
211					     "fsl,sec-v4.0-job-ring";
212				reg	   = <0x40000 0x10000>;
213				interrupts = <0 74 0x4>;
214			};
215		};
216
217		dcfg: dcfg@1ee0000 {
218			compatible = "fsl,ls1043a-dcfg", "syscon";
219			reg = <0x0 0x1ee0000 0x0 0x10000>;
220			big-endian;
221		};
222
223		ifc: ifc@1530000 {
224			compatible = "fsl,ifc", "simple-bus";
225			reg = <0x0 0x1530000 0x0 0x10000>;
226			interrupts = <0 43 0x4>;
227		};
228
229		qspi: quadspi@1550000 {
230			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
231			#address-cells = <1>;
232			#size-cells = <0>;
233			reg = <0x0 0x1550000 0x0 0x10000>,
234				<0x0 0x40000000 0x0 0x4000000>;
235			reg-names = "QuadSPI", "QuadSPI-memory";
236			interrupts = <0 99 0x4>;
237			clock-names = "qspi_en", "qspi";
238			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
239			big-endian;
240			status = "disabled";
241		};
242
243		esdhc: esdhc@1560000 {
244			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
245			reg = <0x0 0x1560000 0x0 0x10000>;
246			interrupts = <0 62 0x4>;
247			clock-frequency = <0>;
248			voltage-ranges = <1800 1800 3300 3300>;
249			sdhci,auto-cmd12;
250			big-endian;
251			bus-width = <4>;
252		};
253
254		ddr: memory-controller@1080000 {
255			compatible = "fsl,qoriq-memory-controller";
256			reg = <0x0 0x1080000 0x0 0x1000>;
257			interrupts = <0 144 0x4>;
258			big-endian;
259		};
260
261		tmu: tmu@1f00000 {
262			compatible = "fsl,qoriq-tmu";
263			reg = <0x0 0x1f00000 0x0 0x10000>;
264			interrupts = <0 33 0x4>;
265			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
266			fsl,tmu-calibration = <0x00000000 0x00000026
267					       0x00000001 0x0000002d
268					       0x00000002 0x00000032
269					       0x00000003 0x00000039
270					       0x00000004 0x0000003f
271					       0x00000005 0x00000046
272					       0x00000006 0x0000004d
273					       0x00000007 0x00000054
274					       0x00000008 0x0000005a
275					       0x00000009 0x00000061
276					       0x0000000a 0x0000006a
277					       0x0000000b 0x00000071
278
279					       0x00010000 0x00000025
280					       0x00010001 0x0000002c
281					       0x00010002 0x00000035
282					       0x00010003 0x0000003d
283					       0x00010004 0x00000045
284					       0x00010005 0x0000004e
285					       0x00010006 0x00000057
286					       0x00010007 0x00000061
287					       0x00010008 0x0000006b
288					       0x00010009 0x00000076
289
290					       0x00020000 0x00000029
291					       0x00020001 0x00000033
292					       0x00020002 0x0000003d
293					       0x00020003 0x00000049
294					       0x00020004 0x00000056
295					       0x00020005 0x00000061
296					       0x00020006 0x0000006d
297
298					       0x00030000 0x00000021
299					       0x00030001 0x0000002a
300					       0x00030002 0x0000003c
301					       0x00030003 0x0000004e>;
302			#thermal-sensor-cells = <1>;
303		};
304
305		thermal-zones {
306			cpu_thermal: cpu-thermal {
307				polling-delay-passive = <1000>;
308				polling-delay = <5000>;
309
310				thermal-sensors = <&tmu 3>;
311
312				trips {
313					cpu_alert: cpu-alert {
314						temperature = <85000>;
315						hysteresis = <2000>;
316						type = "passive";
317					};
318					cpu_crit: cpu-crit {
319						temperature = <95000>;
320						hysteresis = <2000>;
321						type = "critical";
322					};
323				};
324
325				cooling-maps {
326					map0 {
327						trip = <&cpu_alert>;
328						cooling-device =
329							<&cpu0 THERMAL_NO_LIMIT
330							THERMAL_NO_LIMIT>;
331					};
332				};
333			};
334		};
335
336		dspi0: dspi@2100000 {
337			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
338			#address-cells = <1>;
339			#size-cells = <0>;
340			reg = <0x0 0x2100000 0x0 0x10000>;
341			interrupts = <0 64 0x4>;
342			clock-names = "dspi";
343			clocks = <&clockgen 4 0>;
344			spi-num-chipselects = <5>;
345			big-endian;
346			status = "disabled";
347		};
348
349		dspi1: dspi@2110000 {
350			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
351			#address-cells = <1>;
352			#size-cells = <0>;
353			reg = <0x0 0x2110000 0x0 0x10000>;
354			interrupts = <0 65 0x4>;
355			clock-names = "dspi";
356			clocks = <&clockgen 4 0>;
357			spi-num-chipselects = <5>;
358			big-endian;
359			status = "disabled";
360		};
361
362		i2c0: i2c@2180000 {
363			compatible = "fsl,vf610-i2c";
364			#address-cells = <1>;
365			#size-cells = <0>;
366			reg = <0x0 0x2180000 0x0 0x10000>;
367			interrupts = <0 56 0x4>;
368			clock-names = "i2c";
369			clocks = <&clockgen 4 0>;
370			dmas = <&edma0 1 39>,
371			       <&edma0 1 38>;
372			dma-names = "tx", "rx";
373			status = "disabled";
374		};
375
376		i2c1: i2c@2190000 {
377			compatible = "fsl,vf610-i2c";
378			#address-cells = <1>;
379			#size-cells = <0>;
380			reg = <0x0 0x2190000 0x0 0x10000>;
381			interrupts = <0 57 0x4>;
382			clock-names = "i2c";
383			clocks = <&clockgen 4 0>;
384			status = "disabled";
385		};
386
387		i2c2: i2c@21a0000 {
388			compatible = "fsl,vf610-i2c";
389			#address-cells = <1>;
390			#size-cells = <0>;
391			reg = <0x0 0x21a0000 0x0 0x10000>;
392			interrupts = <0 58 0x4>;
393			clock-names = "i2c";
394			clocks = <&clockgen 4 0>;
395			status = "disabled";
396		};
397
398		i2c3: i2c@21b0000 {
399			compatible = "fsl,vf610-i2c";
400			#address-cells = <1>;
401			#size-cells = <0>;
402			reg = <0x0 0x21b0000 0x0 0x10000>;
403			interrupts = <0 59 0x4>;
404			clock-names = "i2c";
405			clocks = <&clockgen 4 0>;
406			status = "disabled";
407		};
408
409		duart0: serial@21c0500 {
410			compatible = "fsl,ns16550", "ns16550a";
411			reg = <0x00 0x21c0500 0x0 0x100>;
412			interrupts = <0 54 0x4>;
413			clocks = <&clockgen 4 0>;
414		};
415
416		duart1: serial@21c0600 {
417			compatible = "fsl,ns16550", "ns16550a";
418			reg = <0x00 0x21c0600 0x0 0x100>;
419			interrupts = <0 54 0x4>;
420			clocks = <&clockgen 4 0>;
421		};
422
423		duart2: serial@21d0500 {
424			compatible = "fsl,ns16550", "ns16550a";
425			reg = <0x0 0x21d0500 0x0 0x100>;
426			interrupts = <0 55 0x4>;
427			clocks = <&clockgen 4 0>;
428		};
429
430		duart3: serial@21d0600 {
431			compatible = "fsl,ns16550", "ns16550a";
432			reg = <0x0 0x21d0600 0x0 0x100>;
433			interrupts = <0 55 0x4>;
434			clocks = <&clockgen 4 0>;
435		};
436
437		gpio1: gpio@2300000 {
438			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
439			reg = <0x0 0x2300000 0x0 0x10000>;
440			interrupts = <0 66 0x4>;
441			gpio-controller;
442			#gpio-cells = <2>;
443			interrupt-controller;
444			#interrupt-cells = <2>;
445		};
446
447		gpio2: gpio@2310000 {
448			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
449			reg = <0x0 0x2310000 0x0 0x10000>;
450			interrupts = <0 67 0x4>;
451			gpio-controller;
452			#gpio-cells = <2>;
453			interrupt-controller;
454			#interrupt-cells = <2>;
455		};
456
457		gpio3: gpio@2320000 {
458			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
459			reg = <0x0 0x2320000 0x0 0x10000>;
460			interrupts = <0 68 0x4>;
461			gpio-controller;
462			#gpio-cells = <2>;
463			interrupt-controller;
464			#interrupt-cells = <2>;
465		};
466
467		gpio4: gpio@2330000 {
468			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
469			reg = <0x0 0x2330000 0x0 0x10000>;
470			interrupts = <0 134 0x4>;
471			gpio-controller;
472			#gpio-cells = <2>;
473			interrupt-controller;
474			#interrupt-cells = <2>;
475		};
476
477		lpuart0: serial@2950000 {
478			compatible = "fsl,ls1021a-lpuart";
479			reg = <0x0 0x2950000 0x0 0x1000>;
480			interrupts = <0 48 0x4>;
481			clocks = <&clockgen 0 0>;
482			clock-names = "ipg";
483			status = "disabled";
484		};
485
486		lpuart1: serial@2960000 {
487			compatible = "fsl,ls1021a-lpuart";
488			reg = <0x0 0x2960000 0x0 0x1000>;
489			interrupts = <0 49 0x4>;
490			clocks = <&clockgen 4 0>;
491			clock-names = "ipg";
492			status = "disabled";
493		};
494
495		lpuart2: serial@2970000 {
496			compatible = "fsl,ls1021a-lpuart";
497			reg = <0x0 0x2970000 0x0 0x1000>;
498			interrupts = <0 50 0x4>;
499			clocks = <&clockgen 4 0>;
500			clock-names = "ipg";
501			status = "disabled";
502		};
503
504		lpuart3: serial@2980000 {
505			compatible = "fsl,ls1021a-lpuart";
506			reg = <0x0 0x2980000 0x0 0x1000>;
507			interrupts = <0 51 0x4>;
508			clocks = <&clockgen 4 0>;
509			clock-names = "ipg";
510			status = "disabled";
511		};
512
513		lpuart4: serial@2990000 {
514			compatible = "fsl,ls1021a-lpuart";
515			reg = <0x0 0x2990000 0x0 0x1000>;
516			interrupts = <0 52 0x4>;
517			clocks = <&clockgen 4 0>;
518			clock-names = "ipg";
519			status = "disabled";
520		};
521
522		lpuart5: serial@29a0000 {
523			compatible = "fsl,ls1021a-lpuart";
524			reg = <0x0 0x29a0000 0x0 0x1000>;
525			interrupts = <0 53 0x4>;
526			clocks = <&clockgen 4 0>;
527			clock-names = "ipg";
528			status = "disabled";
529		};
530
531		wdog0: wdog@2ad0000 {
532			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
533			reg = <0x0 0x2ad0000 0x0 0x10000>;
534			interrupts = <0 83 0x4>;
535			clocks = <&clockgen 4 0>;
536			clock-names = "wdog";
537			big-endian;
538		};
539
540		edma0: edma@2c00000 {
541			#dma-cells = <2>;
542			compatible = "fsl,vf610-edma";
543			reg = <0x0 0x2c00000 0x0 0x10000>,
544			      <0x0 0x2c10000 0x0 0x10000>,
545			      <0x0 0x2c20000 0x0 0x10000>;
546			interrupts = <0 103 0x4>,
547				     <0 103 0x4>;
548			interrupt-names = "edma-tx", "edma-err";
549			dma-channels = <32>;
550			big-endian;
551			clock-names = "dmamux0", "dmamux1";
552			clocks = <&clockgen 4 0>,
553				 <&clockgen 4 0>;
554		};
555
556		usb0: usb3@2f00000 {
557			compatible = "snps,dwc3";
558			reg = <0x0 0x2f00000 0x0 0x10000>;
559			interrupts = <0 60 0x4>;
560			dr_mode = "host";
561			snps,quirk-frame-length-adjustment = <0x20>;
562			snps,dis_rxdet_inp3_quirk;
563		};
564
565		usb1: usb3@3000000 {
566			compatible = "snps,dwc3";
567			reg = <0x0 0x3000000 0x0 0x10000>;
568			interrupts = <0 61 0x4>;
569			dr_mode = "host";
570			snps,quirk-frame-length-adjustment = <0x20>;
571			snps,dis_rxdet_inp3_quirk;
572		};
573
574		usb2: usb3@3100000 {
575			compatible = "snps,dwc3";
576			reg = <0x0 0x3100000 0x0 0x10000>;
577			interrupts = <0 63 0x4>;
578			dr_mode = "host";
579			snps,quirk-frame-length-adjustment = <0x20>;
580			snps,dis_rxdet_inp3_quirk;
581		};
582
583		sata: sata@3200000 {
584			compatible = "fsl,ls1043a-ahci";
585			reg = <0x0 0x3200000 0x0 0x10000>;
586			interrupts = <0 69 0x4>;
587			clocks = <&clockgen 4 0>;
588			dma-coherent;
589		};
590
591		msi1: msi-controller1@1571000 {
592			compatible = "fsl,1s1043a-msi";
593			reg = <0x0 0x1571000 0x0 0x8>;
594			msi-controller;
595			interrupts = <0 116 0x4>;
596		};
597
598		msi2: msi-controller2@1572000 {
599			compatible = "fsl,1s1043a-msi";
600			reg = <0x0 0x1572000 0x0 0x8>;
601			msi-controller;
602			interrupts = <0 126 0x4>;
603		};
604
605		msi3: msi-controller3@1573000 {
606			compatible = "fsl,1s1043a-msi";
607			reg = <0x0 0x1573000 0x0 0x8>;
608			msi-controller;
609			interrupts = <0 160 0x4>;
610		};
611
612		pcie@3400000 {
613			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
614			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
615			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
616			reg-names = "regs", "config";
617			interrupts = <0 118 0x4>, /* controller interrupt */
618				     <0 117 0x4>; /* PME interrupt */
619			interrupt-names = "intr", "pme";
620			#address-cells = <3>;
621			#size-cells = <2>;
622			device_type = "pci";
623			dma-coherent;
624			num-lanes = <4>;
625			bus-range = <0x0 0xff>;
626			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
627				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
628			msi-parent = <&msi1>;
629			#interrupt-cells = <1>;
630			interrupt-map-mask = <0 0 0 7>;
631			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
632					<0000 0 0 2 &gic 0 111 0x4>,
633					<0000 0 0 3 &gic 0 112 0x4>,
634					<0000 0 0 4 &gic 0 113 0x4>;
635		};
636
637		pcie@3500000 {
638			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
639			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
640			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
641			reg-names = "regs", "config";
642			interrupts = <0 128 0x4>,
643				     <0 127 0x4>;
644			interrupt-names = "intr", "pme";
645			#address-cells = <3>;
646			#size-cells = <2>;
647			device_type = "pci";
648			dma-coherent;
649			num-lanes = <2>;
650			bus-range = <0x0 0xff>;
651			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
652				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
653			msi-parent = <&msi2>;
654			#interrupt-cells = <1>;
655			interrupt-map-mask = <0 0 0 7>;
656			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
657					<0000 0 0 2 &gic 0 121 0x4>,
658					<0000 0 0 3 &gic 0 122 0x4>,
659					<0000 0 0 4 &gic 0 123 0x4>;
660		};
661
662		pcie@3600000 {
663			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
664			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
665			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
666			reg-names = "regs", "config";
667			interrupts = <0 162 0x4>,
668				     <0 161 0x4>;
669			interrupt-names = "intr", "pme";
670			#address-cells = <3>;
671			#size-cells = <2>;
672			device_type = "pci";
673			dma-coherent;
674			num-lanes = <2>;
675			bus-range = <0x0 0xff>;
676			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
677				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
678			msi-parent = <&msi3>;
679			#interrupt-cells = <1>;
680			interrupt-map-mask = <0 0 0 7>;
681			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
682					<0000 0 0 2 &gic 0 155 0x4>,
683					<0000 0 0 3 &gic 0 156 0x4>,
684					<0000 0 0 4 &gic 0 157 0x4>;
685		};
686	};
687
688};
689