1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12#include <dt-bindings/thermal/thermal.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15/ {
16	compatible = "fsl,ls1043a";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		crypto = &crypto;
23		fman0 = &fman0;
24		ethernet0 = &enet0;
25		ethernet1 = &enet1;
26		ethernet2 = &enet2;
27		ethernet3 = &enet3;
28		ethernet4 = &enet4;
29		ethernet5 = &enet5;
30		ethernet6 = &enet6;
31		rtc1 = &ftm_alarm0;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		/*
39		 * We expect the enable-method for cpu's to be "psci", but this
40		 * is dependent on the SoC FW, which will fill this in.
41		 *
42		 * Currently supported enable-method is psci v0.2
43		 */
44		cpu0: cpu@0 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a53";
47			reg = <0x0>;
48			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
49			next-level-cache = <&l2>;
50			cpu-idle-states = <&CPU_PH20>;
51			#cooling-cells = <2>;
52		};
53
54		cpu1: cpu@1 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a53";
57			reg = <0x1>;
58			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
59			next-level-cache = <&l2>;
60			cpu-idle-states = <&CPU_PH20>;
61			#cooling-cells = <2>;
62		};
63
64		cpu2: cpu@2 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53";
67			reg = <0x2>;
68			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
69			next-level-cache = <&l2>;
70			cpu-idle-states = <&CPU_PH20>;
71			#cooling-cells = <2>;
72		};
73
74		cpu3: cpu@3 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53";
77			reg = <0x3>;
78			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
79			next-level-cache = <&l2>;
80			cpu-idle-states = <&CPU_PH20>;
81			#cooling-cells = <2>;
82		};
83
84		l2: l2-cache {
85			compatible = "cache";
86		};
87	};
88
89	idle-states {
90		/*
91		 * PSCI node is not added default, U-boot will add missing
92		 * parts if it determines to use PSCI.
93		 */
94		entry-method = "psci";
95
96		CPU_PH20: cpu-ph20 {
97			compatible = "arm,idle-state";
98			idle-state-name = "PH20";
99			arm,psci-suspend-param = <0x0>;
100			entry-latency-us = <1000>;
101			exit-latency-us = <1000>;
102			min-residency-us = <3000>;
103		};
104	};
105
106	memory@80000000 {
107		device_type = "memory";
108		reg = <0x0 0x80000000 0 0x80000000>;
109		      /* DRAM space 1, size: 2GiB DRAM */
110	};
111
112	reserved-memory {
113		#address-cells = <2>;
114		#size-cells = <2>;
115		ranges;
116
117		bman_fbpr: bman-fbpr {
118			compatible = "shared-dma-pool";
119			size = <0 0x1000000>;
120			alignment = <0 0x1000000>;
121			no-map;
122		};
123
124		qman_fqd: qman-fqd {
125			compatible = "shared-dma-pool";
126			size = <0 0x400000>;
127			alignment = <0 0x400000>;
128			no-map;
129		};
130
131		qman_pfdr: qman-pfdr {
132			compatible = "shared-dma-pool";
133			size = <0 0x2000000>;
134			alignment = <0 0x2000000>;
135			no-map;
136		};
137	};
138
139	sysclk: sysclk {
140		compatible = "fixed-clock";
141		#clock-cells = <0>;
142		clock-frequency = <100000000>;
143		clock-output-names = "sysclk";
144	};
145
146	reboot {
147		compatible ="syscon-reboot";
148		regmap = <&dcfg>;
149		offset = <0xb0>;
150		mask = <0x02>;
151	};
152
153	thermal-zones {
154		ddr-controller {
155			polling-delay-passive = <1000>;
156			polling-delay = <5000>;
157			thermal-sensors = <&tmu 0>;
158
159			trips {
160				ddr-ctrler-alert {
161					temperature = <85000>;
162					hysteresis = <2000>;
163					type = "passive";
164				};
165
166				ddr-ctrler-crit {
167					temperature = <95000>;
168					hysteresis = <2000>;
169					type = "critical";
170				};
171			};
172		};
173
174		serdes {
175			polling-delay-passive = <1000>;
176			polling-delay = <5000>;
177			thermal-sensors = <&tmu 1>;
178
179			trips {
180				serdes-alert {
181					temperature = <85000>;
182					hysteresis = <2000>;
183					type = "passive";
184				};
185
186				serdes-crit {
187					temperature = <95000>;
188					hysteresis = <2000>;
189					type = "critical";
190				};
191			};
192		};
193
194		fman {
195			polling-delay-passive = <1000>;
196			polling-delay = <5000>;
197			thermal-sensors = <&tmu 2>;
198
199			trips {
200				fman-alert {
201					temperature = <85000>;
202					hysteresis = <2000>;
203					type = "passive";
204				};
205
206				fman-crit {
207					temperature = <95000>;
208					hysteresis = <2000>;
209					type = "critical";
210				};
211			};
212		};
213
214		core-cluster {
215			polling-delay-passive = <1000>;
216			polling-delay = <5000>;
217			thermal-sensors = <&tmu 3>;
218
219			trips {
220				core_cluster_alert: core-cluster-alert {
221					temperature = <85000>;
222					hysteresis = <2000>;
223					type = "passive";
224				};
225
226				core_cluster_crit: core-cluster-crit {
227					temperature = <95000>;
228					hysteresis = <2000>;
229					type = "critical";
230				};
231			};
232
233			cooling-maps {
234				map0 {
235					trip = <&core_cluster_alert>;
236					cooling-device =
237						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
238						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
239						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
240						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
241				};
242			};
243		};
244
245		sec {
246			polling-delay-passive = <1000>;
247			polling-delay = <5000>;
248			thermal-sensors = <&tmu 4>;
249
250			trips {
251				sec-alert {
252					temperature = <85000>;
253					hysteresis = <2000>;
254					type = "passive";
255				};
256
257				sec-crit {
258					temperature = <95000>;
259					hysteresis = <2000>;
260					type = "critical";
261				};
262			};
263		};
264	};
265
266	timer {
267		compatible = "arm,armv8-timer";
268		interrupts = <1 13 0xf08>, /* Physical Secure PPI */
269			     <1 14 0xf08>, /* Physical Non-Secure PPI */
270			     <1 11 0xf08>, /* Virtual PPI */
271			     <1 10 0xf08>; /* Hypervisor PPI */
272		fsl,erratum-a008585;
273	};
274
275	pmu {
276		compatible = "arm,armv8-pmuv3";
277		interrupts = <0 106 0x4>,
278			     <0 107 0x4>,
279			     <0 95 0x4>,
280			     <0 97 0x4>;
281		interrupt-affinity = <&cpu0>,
282				     <&cpu1>,
283				     <&cpu2>,
284				     <&cpu3>;
285	};
286
287	gic: interrupt-controller@1400000 {
288		compatible = "arm,gic-400";
289		#interrupt-cells = <3>;
290		interrupt-controller;
291		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
292		      <0x0 0x1402000 0 0x2000>, /* GICC */
293		      <0x0 0x1404000 0 0x2000>, /* GICH */
294		      <0x0 0x1406000 0 0x2000>; /* GICV */
295		interrupts = <1 9 0xf08>;
296	};
297
298	soc: soc {
299		compatible = "simple-bus";
300		#address-cells = <2>;
301		#size-cells = <2>;
302		ranges;
303
304		clockgen: clocking@1ee1000 {
305			compatible = "fsl,ls1043a-clockgen";
306			reg = <0x0 0x1ee1000 0x0 0x1000>;
307			#clock-cells = <2>;
308			clocks = <&sysclk>;
309		};
310
311		scfg: scfg@1570000 {
312			compatible = "fsl,ls1043a-scfg", "syscon";
313			reg = <0x0 0x1570000 0x0 0x10000>;
314			big-endian;
315			#address-cells = <1>;
316			#size-cells = <1>;
317			ranges = <0x0 0x0 0x1570000 0x10000>;
318
319			extirq: interrupt-controller@1ac {
320				compatible = "fsl,ls1043a-extirq";
321				#interrupt-cells = <2>;
322				#address-cells = <0>;
323				interrupt-controller;
324				reg = <0x1ac 4>;
325				interrupt-map =
326					<0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
327					<1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
328					<2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
329					<3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
330					<4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
331					<5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
332					<6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
333					<7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
334					<8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
335					<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
336					<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
337					<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
338				interrupt-map-mask = <0xffffffff 0x0>;
339			};
340		};
341
342		crypto: crypto@1700000 {
343			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
344				     "fsl,sec-v4.0";
345			fsl,sec-era = <3>;
346			#address-cells = <1>;
347			#size-cells = <1>;
348			ranges = <0x0 0x00 0x1700000 0x100000>;
349			reg = <0x00 0x1700000 0x0 0x100000>;
350			interrupts = <0 75 0x4>;
351
352			sec_jr0: jr@10000 {
353				compatible = "fsl,sec-v5.4-job-ring",
354					     "fsl,sec-v5.0-job-ring",
355					     "fsl,sec-v4.0-job-ring";
356				reg	   = <0x10000 0x10000>;
357				interrupts = <0 71 0x4>;
358			};
359
360			sec_jr1: jr@20000 {
361				compatible = "fsl,sec-v5.4-job-ring",
362					     "fsl,sec-v5.0-job-ring",
363					     "fsl,sec-v4.0-job-ring";
364				reg	   = <0x20000 0x10000>;
365				interrupts = <0 72 0x4>;
366			};
367
368			sec_jr2: jr@30000 {
369				compatible = "fsl,sec-v5.4-job-ring",
370					     "fsl,sec-v5.0-job-ring",
371					     "fsl,sec-v4.0-job-ring";
372				reg	   = <0x30000 0x10000>;
373				interrupts = <0 73 0x4>;
374			};
375
376			sec_jr3: jr@40000 {
377				compatible = "fsl,sec-v5.4-job-ring",
378					     "fsl,sec-v5.0-job-ring",
379					     "fsl,sec-v4.0-job-ring";
380				reg	   = <0x40000 0x10000>;
381				interrupts = <0 74 0x4>;
382			};
383		};
384
385		dcfg: dcfg@1ee0000 {
386			compatible = "fsl,ls1043a-dcfg", "syscon";
387			reg = <0x0 0x1ee0000 0x0 0x10000>;
388			big-endian;
389		};
390
391		ifc: ifc@1530000 {
392			compatible = "fsl,ifc", "simple-bus";
393			reg = <0x0 0x1530000 0x0 0x10000>;
394			interrupts = <0 43 0x4>;
395		};
396
397		qspi: spi@1550000 {
398			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
399			#address-cells = <1>;
400			#size-cells = <0>;
401			reg = <0x0 0x1550000 0x0 0x10000>,
402				<0x0 0x40000000 0x0 0x4000000>;
403			reg-names = "QuadSPI", "QuadSPI-memory";
404			interrupts = <0 99 0x4>;
405			clock-names = "qspi_en", "qspi";
406			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
407					    QORIQ_CLK_PLL_DIV(1)>,
408				 <&clockgen QORIQ_CLK_PLATFORM_PLL
409					    QORIQ_CLK_PLL_DIV(1)>;
410			status = "disabled";
411		};
412
413		esdhc: esdhc@1560000 {
414			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
415			reg = <0x0 0x1560000 0x0 0x10000>;
416			interrupts = <0 62 0x4>;
417			clock-frequency = <0>;
418			voltage-ranges = <1800 1800 3300 3300>;
419			sdhci,auto-cmd12;
420			big-endian;
421			bus-width = <4>;
422		};
423
424		ddr: memory-controller@1080000 {
425			compatible = "fsl,qoriq-memory-controller";
426			reg = <0x0 0x1080000 0x0 0x1000>;
427			interrupts = <0 144 0x4>;
428			big-endian;
429		};
430
431		tmu: tmu@1f00000 {
432			compatible = "fsl,qoriq-tmu";
433			reg = <0x0 0x1f00000 0x0 0x10000>;
434			interrupts = <0 33 0x4>;
435			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
436			fsl,tmu-calibration = <0x00000000 0x00000023
437					       0x00000001 0x0000002a
438					       0x00000002 0x00000031
439					       0x00000003 0x00000037
440					       0x00000004 0x0000003e
441					       0x00000005 0x00000044
442					       0x00000006 0x0000004b
443					       0x00000007 0x00000051
444					       0x00000008 0x00000058
445					       0x00000009 0x0000005e
446					       0x0000000a 0x00000065
447					       0x0000000b 0x0000006b
448
449					       0x00010000 0x00000023
450					       0x00010001 0x0000002b
451					       0x00010002 0x00000033
452					       0x00010003 0x0000003b
453					       0x00010004 0x00000043
454					       0x00010005 0x0000004b
455					       0x00010006 0x00000054
456					       0x00010007 0x0000005c
457					       0x00010008 0x00000064
458					       0x00010009 0x0000006c
459
460					       0x00020000 0x00000021
461					       0x00020001 0x0000002c
462					       0x00020002 0x00000036
463					       0x00020003 0x00000040
464					       0x00020004 0x0000004b
465					       0x00020005 0x00000055
466					       0x00020006 0x0000005f
467
468					       0x00030000 0x00000013
469					       0x00030001 0x0000001d
470					       0x00030002 0x00000028
471					       0x00030003 0x00000032
472					       0x00030004 0x0000003d
473					       0x00030005 0x00000047
474					       0x00030006 0x00000052
475					       0x00030007 0x0000005c>;
476			#thermal-sensor-cells = <1>;
477		};
478
479		qman: qman@1880000 {
480			compatible = "fsl,qman";
481			reg = <0x0 0x1880000 0x0 0x10000>;
482			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
483			memory-region = <&qman_fqd &qman_pfdr>;
484		};
485
486		bman: bman@1890000 {
487			compatible = "fsl,bman";
488			reg = <0x0 0x1890000 0x0 0x10000>;
489			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
490			memory-region = <&bman_fbpr>;
491		};
492
493		bportals: bman-portals@508000000 {
494			ranges = <0x0 0x5 0x08000000 0x8000000>;
495		};
496
497		qportals: qman-portals@500000000 {
498			ranges = <0x0 0x5 0x00000000 0x8000000>;
499		};
500
501		dspi0: spi@2100000 {
502			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
503			#address-cells = <1>;
504			#size-cells = <0>;
505			reg = <0x0 0x2100000 0x0 0x10000>;
506			interrupts = <0 64 0x4>;
507			clock-names = "dspi";
508			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
509					    QORIQ_CLK_PLL_DIV(1)>;
510			spi-num-chipselects = <5>;
511			big-endian;
512			status = "disabled";
513		};
514
515		dspi1: spi@2110000 {
516			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
517			#address-cells = <1>;
518			#size-cells = <0>;
519			reg = <0x0 0x2110000 0x0 0x10000>;
520			interrupts = <0 65 0x4>;
521			clock-names = "dspi";
522			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
523					    QORIQ_CLK_PLL_DIV(1)>;
524			spi-num-chipselects = <5>;
525			big-endian;
526			status = "disabled";
527		};
528
529		i2c0: i2c@2180000 {
530			compatible = "fsl,vf610-i2c";
531			#address-cells = <1>;
532			#size-cells = <0>;
533			reg = <0x0 0x2180000 0x0 0x10000>;
534			interrupts = <0 56 0x4>;
535			clock-names = "i2c";
536			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
537					    QORIQ_CLK_PLL_DIV(1)>;
538			dmas = <&edma0 1 39>,
539			       <&edma0 1 38>;
540			dma-names = "tx", "rx";
541			status = "disabled";
542		};
543
544		i2c1: i2c@2190000 {
545			compatible = "fsl,vf610-i2c";
546			#address-cells = <1>;
547			#size-cells = <0>;
548			reg = <0x0 0x2190000 0x0 0x10000>;
549			interrupts = <0 57 0x4>;
550			clock-names = "i2c";
551			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
552					    QORIQ_CLK_PLL_DIV(1)>;
553			status = "disabled";
554		};
555
556		i2c2: i2c@21a0000 {
557			compatible = "fsl,vf610-i2c";
558			#address-cells = <1>;
559			#size-cells = <0>;
560			reg = <0x0 0x21a0000 0x0 0x10000>;
561			interrupts = <0 58 0x4>;
562			clock-names = "i2c";
563			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
564					    QORIQ_CLK_PLL_DIV(1)>;
565			status = "disabled";
566		};
567
568		i2c3: i2c@21b0000 {
569			compatible = "fsl,vf610-i2c";
570			#address-cells = <1>;
571			#size-cells = <0>;
572			reg = <0x0 0x21b0000 0x0 0x10000>;
573			interrupts = <0 59 0x4>;
574			clock-names = "i2c";
575			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
576					    QORIQ_CLK_PLL_DIV(1)>;
577			status = "disabled";
578		};
579
580		duart0: serial@21c0500 {
581			compatible = "fsl,ns16550", "ns16550a";
582			reg = <0x00 0x21c0500 0x0 0x100>;
583			interrupts = <0 54 0x4>;
584			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
585					    QORIQ_CLK_PLL_DIV(1)>;
586		};
587
588		duart1: serial@21c0600 {
589			compatible = "fsl,ns16550", "ns16550a";
590			reg = <0x00 0x21c0600 0x0 0x100>;
591			interrupts = <0 54 0x4>;
592			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
593					    QORIQ_CLK_PLL_DIV(1)>;
594		};
595
596		duart2: serial@21d0500 {
597			compatible = "fsl,ns16550", "ns16550a";
598			reg = <0x0 0x21d0500 0x0 0x100>;
599			interrupts = <0 55 0x4>;
600			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
601					    QORIQ_CLK_PLL_DIV(1)>;
602		};
603
604		duart3: serial@21d0600 {
605			compatible = "fsl,ns16550", "ns16550a";
606			reg = <0x0 0x21d0600 0x0 0x100>;
607			interrupts = <0 55 0x4>;
608			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
609					    QORIQ_CLK_PLL_DIV(1)>;
610		};
611
612		gpio1: gpio@2300000 {
613			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
614			reg = <0x0 0x2300000 0x0 0x10000>;
615			interrupts = <0 66 0x4>;
616			gpio-controller;
617			#gpio-cells = <2>;
618			interrupt-controller;
619			#interrupt-cells = <2>;
620		};
621
622		gpio2: gpio@2310000 {
623			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
624			reg = <0x0 0x2310000 0x0 0x10000>;
625			interrupts = <0 67 0x4>;
626			gpio-controller;
627			#gpio-cells = <2>;
628			interrupt-controller;
629			#interrupt-cells = <2>;
630		};
631
632		gpio3: gpio@2320000 {
633			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
634			reg = <0x0 0x2320000 0x0 0x10000>;
635			interrupts = <0 68 0x4>;
636			gpio-controller;
637			#gpio-cells = <2>;
638			interrupt-controller;
639			#interrupt-cells = <2>;
640		};
641
642		gpio4: gpio@2330000 {
643			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
644			reg = <0x0 0x2330000 0x0 0x10000>;
645			interrupts = <0 134 0x4>;
646			gpio-controller;
647			#gpio-cells = <2>;
648			interrupt-controller;
649			#interrupt-cells = <2>;
650		};
651
652		uqe: uqe@2400000 {
653			#address-cells = <1>;
654			#size-cells = <1>;
655			compatible = "fsl,qe", "simple-bus";
656			ranges = <0x0 0x0 0x2400000 0x40000>;
657			reg = <0x0 0x2400000 0x0 0x480>;
658			brg-frequency = <100000000>;
659			bus-frequency = <200000000>;
660			fsl,qe-num-riscs = <1>;
661			fsl,qe-num-snums = <28>;
662
663			qeic: qeic@80 {
664				compatible = "fsl,qe-ic";
665				reg = <0x80 0x80>;
666				#address-cells = <0>;
667				interrupt-controller;
668				#interrupt-cells = <1>;
669				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
670					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
671			};
672
673			si1: si@700 {
674				#address-cells = <1>;
675				#size-cells = <0>;
676				compatible = "fsl,ls1043-qe-si",
677						"fsl,t1040-qe-si";
678				reg = <0x700 0x80>;
679			};
680
681			siram1: siram@1000 {
682				#address-cells = <1>;
683				#size-cells = <1>;
684				compatible = "fsl,ls1043-qe-siram",
685						"fsl,t1040-qe-siram";
686				reg = <0x1000 0x800>;
687			};
688
689			ucc@2000 {
690				cell-index = <1>;
691				reg = <0x2000 0x200>;
692				interrupts = <32>;
693				interrupt-parent = <&qeic>;
694			};
695
696			ucc@2200 {
697				cell-index = <3>;
698				reg = <0x2200 0x200>;
699				interrupts = <34>;
700				interrupt-parent = <&qeic>;
701			};
702
703			muram@10000 {
704				#address-cells = <1>;
705				#size-cells = <1>;
706				compatible = "fsl,qe-muram", "fsl,cpm-muram";
707				ranges = <0x0 0x10000 0x6000>;
708
709				data-only@0 {
710					compatible = "fsl,qe-muram-data",
711					"fsl,cpm-muram-data";
712					reg = <0x0 0x6000>;
713				};
714			};
715		};
716
717		lpuart0: serial@2950000 {
718			compatible = "fsl,ls1021a-lpuart";
719			reg = <0x0 0x2950000 0x0 0x1000>;
720			interrupts = <0 48 0x4>;
721			clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
722			clock-names = "ipg";
723			status = "disabled";
724		};
725
726		lpuart1: serial@2960000 {
727			compatible = "fsl,ls1021a-lpuart";
728			reg = <0x0 0x2960000 0x0 0x1000>;
729			interrupts = <0 49 0x4>;
730			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
731					    QORIQ_CLK_PLL_DIV(1)>;
732			clock-names = "ipg";
733			status = "disabled";
734		};
735
736		lpuart2: serial@2970000 {
737			compatible = "fsl,ls1021a-lpuart";
738			reg = <0x0 0x2970000 0x0 0x1000>;
739			interrupts = <0 50 0x4>;
740			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
741					    QORIQ_CLK_PLL_DIV(1)>;
742			clock-names = "ipg";
743			status = "disabled";
744		};
745
746		lpuart3: serial@2980000 {
747			compatible = "fsl,ls1021a-lpuart";
748			reg = <0x0 0x2980000 0x0 0x1000>;
749			interrupts = <0 51 0x4>;
750			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
751					    QORIQ_CLK_PLL_DIV(1)>;
752			clock-names = "ipg";
753			status = "disabled";
754		};
755
756		lpuart4: serial@2990000 {
757			compatible = "fsl,ls1021a-lpuart";
758			reg = <0x0 0x2990000 0x0 0x1000>;
759			interrupts = <0 52 0x4>;
760			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
761					    QORIQ_CLK_PLL_DIV(1)>;
762			clock-names = "ipg";
763			status = "disabled";
764		};
765
766		lpuart5: serial@29a0000 {
767			compatible = "fsl,ls1021a-lpuart";
768			reg = <0x0 0x29a0000 0x0 0x1000>;
769			interrupts = <0 53 0x4>;
770			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
771					    QORIQ_CLK_PLL_DIV(1)>;
772			clock-names = "ipg";
773			status = "disabled";
774		};
775
776		wdog0: watchdog@2ad0000 {
777			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
778			reg = <0x0 0x2ad0000 0x0 0x10000>;
779			interrupts = <0 83 0x4>;
780			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
781					    QORIQ_CLK_PLL_DIV(1)>;
782			clock-names = "wdog";
783			big-endian;
784		};
785
786		edma0: edma@2c00000 {
787			#dma-cells = <2>;
788			compatible = "fsl,vf610-edma";
789			reg = <0x0 0x2c00000 0x0 0x10000>,
790			      <0x0 0x2c10000 0x0 0x10000>,
791			      <0x0 0x2c20000 0x0 0x10000>;
792			interrupts = <0 103 0x4>,
793				     <0 103 0x4>;
794			interrupt-names = "edma-tx", "edma-err";
795			dma-channels = <32>;
796			big-endian;
797			clock-names = "dmamux0", "dmamux1";
798			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
799					    QORIQ_CLK_PLL_DIV(1)>,
800				 <&clockgen QORIQ_CLK_PLATFORM_PLL
801					    QORIQ_CLK_PLL_DIV(1)>;
802		};
803
804		usb0: usb@2f00000 {
805			compatible = "snps,dwc3";
806			reg = <0x0 0x2f00000 0x0 0x10000>;
807			interrupts = <0 60 0x4>;
808			dr_mode = "host";
809			snps,quirk-frame-length-adjustment = <0x20>;
810			snps,dis_rxdet_inp3_quirk;
811			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
812			status = "disabled";
813		};
814
815		usb1: usb@3000000 {
816			compatible = "snps,dwc3";
817			reg = <0x0 0x3000000 0x0 0x10000>;
818			interrupts = <0 61 0x4>;
819			dr_mode = "host";
820			snps,quirk-frame-length-adjustment = <0x20>;
821			snps,dis_rxdet_inp3_quirk;
822			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
823			status = "disabled";
824		};
825
826		usb2: usb@3100000 {
827			compatible = "snps,dwc3";
828			reg = <0x0 0x3100000 0x0 0x10000>;
829			interrupts = <0 63 0x4>;
830			dr_mode = "host";
831			snps,quirk-frame-length-adjustment = <0x20>;
832			snps,dis_rxdet_inp3_quirk;
833			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
834			status = "disabled";
835		};
836
837		sata: sata@3200000 {
838			compatible = "fsl,ls1043a-ahci";
839			reg = <0x0 0x3200000 0x0 0x10000>,
840				<0x0 0x20140520 0x0 0x4>;
841			reg-names = "ahci", "sata-ecc";
842			interrupts = <0 69 0x4>;
843			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
844					    QORIQ_CLK_PLL_DIV(1)>;
845			dma-coherent;
846		};
847
848		msi1: msi-controller1@1571000 {
849			compatible = "fsl,ls1043a-msi";
850			reg = <0x0 0x1571000 0x0 0x8>;
851			msi-controller;
852			interrupts = <0 116 0x4>;
853		};
854
855		msi2: msi-controller2@1572000 {
856			compatible = "fsl,ls1043a-msi";
857			reg = <0x0 0x1572000 0x0 0x8>;
858			msi-controller;
859			interrupts = <0 126 0x4>;
860		};
861
862		msi3: msi-controller3@1573000 {
863			compatible = "fsl,ls1043a-msi";
864			reg = <0x0 0x1573000 0x0 0x8>;
865			msi-controller;
866			interrupts = <0 160 0x4>;
867		};
868
869		pcie1: pcie@3400000 {
870			compatible = "fsl,ls1043a-pcie";
871			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
872			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
873			reg-names = "regs", "config";
874			interrupts = <0 118 0x4>, /* controller interrupt */
875				     <0 117 0x4>; /* PME interrupt */
876			interrupt-names = "intr", "pme";
877			#address-cells = <3>;
878			#size-cells = <2>;
879			device_type = "pci";
880			dma-coherent;
881			num-viewport = <6>;
882			bus-range = <0x0 0xff>;
883			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
884				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
885			msi-parent = <&msi1>, <&msi2>, <&msi3>;
886			#interrupt-cells = <1>;
887			interrupt-map-mask = <0 0 0 7>;
888			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
889					<0000 0 0 2 &gic 0 111 0x4>,
890					<0000 0 0 3 &gic 0 112 0x4>,
891					<0000 0 0 4 &gic 0 113 0x4>;
892			status = "disabled";
893		};
894
895		pcie2: pcie@3500000 {
896			compatible = "fsl,ls1043a-pcie";
897			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
898			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
899			reg-names = "regs", "config";
900			interrupts = <0 128 0x4>,
901				     <0 127 0x4>;
902			interrupt-names = "intr", "pme";
903			#address-cells = <3>;
904			#size-cells = <2>;
905			device_type = "pci";
906			dma-coherent;
907			num-viewport = <6>;
908			bus-range = <0x0 0xff>;
909			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
910				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
911			msi-parent = <&msi1>, <&msi2>, <&msi3>;
912			#interrupt-cells = <1>;
913			interrupt-map-mask = <0 0 0 7>;
914			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
915					<0000 0 0 2 &gic 0 121 0x4>,
916					<0000 0 0 3 &gic 0 122 0x4>,
917					<0000 0 0 4 &gic 0 123 0x4>;
918			status = "disabled";
919		};
920
921		pcie3: pcie@3600000 {
922			compatible = "fsl,ls1043a-pcie";
923			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
924			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
925			reg-names = "regs", "config";
926			interrupts = <0 162 0x4>,
927				     <0 161 0x4>;
928			interrupt-names = "intr", "pme";
929			#address-cells = <3>;
930			#size-cells = <2>;
931			device_type = "pci";
932			dma-coherent;
933			num-viewport = <6>;
934			bus-range = <0x0 0xff>;
935			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
936				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
937			msi-parent = <&msi1>, <&msi2>, <&msi3>;
938			#interrupt-cells = <1>;
939			interrupt-map-mask = <0 0 0 7>;
940			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
941					<0000 0 0 2 &gic 0 155 0x4>,
942					<0000 0 0 3 &gic 0 156 0x4>,
943					<0000 0 0 4 &gic 0 157 0x4>;
944			status = "disabled";
945		};
946
947		qdma: dma-controller@8380000 {
948			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
949			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
950			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
951			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
952			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
953				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
954				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
955				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
956				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
957			interrupt-names = "qdma-error", "qdma-queue0",
958				"qdma-queue1", "qdma-queue2", "qdma-queue3";
959			dma-channels = <8>;
960			block-number = <1>;
961			block-offset = <0x10000>;
962			fsl,dma-queues = <2>;
963			status-sizes = <64>;
964			queue-sizes = <64 64>;
965			big-endian;
966		};
967
968		rcpm: power-controller@1ee2140 {
969			compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
970			reg = <0x0 0x1ee2140 0x0 0x4>;
971			#fsl,rcpm-wakeup-cells = <1>;
972		};
973
974		ftm_alarm0: timer@29d0000 {
975			compatible = "fsl,ls1043a-ftm-alarm";
976			reg = <0x0 0x29d0000 0x0 0x10000>;
977			fsl,rcpm-wakeup = <&rcpm 0x20000>;
978			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
979			big-endian;
980		};
981	};
982
983	firmware {
984		optee {
985			compatible = "linaro,optee-tz";
986			method = "smc";
987		};
988	};
989
990};
991
992#include "qoriq-qman-portals.dtsi"
993#include "qoriq-bman-portals.dtsi"
994