1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11#include <dt-bindings/thermal/thermal.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15	compatible = "fsl,ls1043a";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		crypto = &crypto;
22		fman0 = &fman0;
23		ethernet0 = &enet0;
24		ethernet1 = &enet1;
25		ethernet2 = &enet2;
26		ethernet3 = &enet3;
27		ethernet4 = &enet4;
28		ethernet5 = &enet5;
29		ethernet6 = &enet6;
30		rtc1 = &ftm_alarm0;
31	};
32
33	cpus {
34		#address-cells = <1>;
35		#size-cells = <0>;
36
37		/*
38		 * We expect the enable-method for cpu's to be "psci", but this
39		 * is dependent on the SoC FW, which will fill this in.
40		 *
41		 * Currently supported enable-method is psci v0.2
42		 */
43		cpu0: cpu@0 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53";
46			reg = <0x0>;
47			clocks = <&clockgen 1 0>;
48			next-level-cache = <&l2>;
49			cpu-idle-states = <&CPU_PH20>;
50			#cooling-cells = <2>;
51		};
52
53		cpu1: cpu@1 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a53";
56			reg = <0x1>;
57			clocks = <&clockgen 1 0>;
58			next-level-cache = <&l2>;
59			cpu-idle-states = <&CPU_PH20>;
60			#cooling-cells = <2>;
61		};
62
63		cpu2: cpu@2 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a53";
66			reg = <0x2>;
67			clocks = <&clockgen 1 0>;
68			next-level-cache = <&l2>;
69			cpu-idle-states = <&CPU_PH20>;
70			#cooling-cells = <2>;
71		};
72
73		cpu3: cpu@3 {
74			device_type = "cpu";
75			compatible = "arm,cortex-a53";
76			reg = <0x3>;
77			clocks = <&clockgen 1 0>;
78			next-level-cache = <&l2>;
79			cpu-idle-states = <&CPU_PH20>;
80			#cooling-cells = <2>;
81		};
82
83		l2: l2-cache {
84			compatible = "cache";
85		};
86	};
87
88	idle-states {
89		/*
90		 * PSCI node is not added default, U-boot will add missing
91		 * parts if it determines to use PSCI.
92		 */
93		entry-method = "psci";
94
95		CPU_PH20: cpu-ph20 {
96			compatible = "arm,idle-state";
97			idle-state-name = "PH20";
98			arm,psci-suspend-param = <0x0>;
99			entry-latency-us = <1000>;
100			exit-latency-us = <1000>;
101			min-residency-us = <3000>;
102		};
103	};
104
105	memory@80000000 {
106		device_type = "memory";
107		reg = <0x0 0x80000000 0 0x80000000>;
108		      /* DRAM space 1, size: 2GiB DRAM */
109	};
110
111	reserved-memory {
112		#address-cells = <2>;
113		#size-cells = <2>;
114		ranges;
115
116		bman_fbpr: bman-fbpr {
117			compatible = "shared-dma-pool";
118			size = <0 0x1000000>;
119			alignment = <0 0x1000000>;
120			no-map;
121		};
122
123		qman_fqd: qman-fqd {
124			compatible = "shared-dma-pool";
125			size = <0 0x400000>;
126			alignment = <0 0x400000>;
127			no-map;
128		};
129
130		qman_pfdr: qman-pfdr {
131			compatible = "shared-dma-pool";
132			size = <0 0x2000000>;
133			alignment = <0 0x2000000>;
134			no-map;
135		};
136	};
137
138	sysclk: sysclk {
139		compatible = "fixed-clock";
140		#clock-cells = <0>;
141		clock-frequency = <100000000>;
142		clock-output-names = "sysclk";
143	};
144
145	reboot {
146		compatible ="syscon-reboot";
147		regmap = <&dcfg>;
148		offset = <0xb0>;
149		mask = <0x02>;
150	};
151
152	thermal-zones {
153		ddr-controller {
154			polling-delay-passive = <1000>;
155			polling-delay = <5000>;
156			thermal-sensors = <&tmu 0>;
157
158			trips {
159				ddr-ctrler-alert {
160					temperature = <85000>;
161					hysteresis = <2000>;
162					type = "passive";
163				};
164
165				ddr-ctrler-crit {
166					temperature = <95000>;
167					hysteresis = <2000>;
168					type = "critical";
169				};
170			};
171		};
172
173		serdes {
174			polling-delay-passive = <1000>;
175			polling-delay = <5000>;
176			thermal-sensors = <&tmu 1>;
177
178			trips {
179				serdes-alert {
180					temperature = <85000>;
181					hysteresis = <2000>;
182					type = "passive";
183				};
184
185				serdes-crit {
186					temperature = <95000>;
187					hysteresis = <2000>;
188					type = "critical";
189				};
190			};
191		};
192
193		fman {
194			polling-delay-passive = <1000>;
195			polling-delay = <5000>;
196			thermal-sensors = <&tmu 2>;
197
198			trips {
199				fman-alert {
200					temperature = <85000>;
201					hysteresis = <2000>;
202					type = "passive";
203				};
204
205				fman-crit {
206					temperature = <95000>;
207					hysteresis = <2000>;
208					type = "critical";
209				};
210			};
211		};
212
213		core-cluster {
214			polling-delay-passive = <1000>;
215			polling-delay = <5000>;
216			thermal-sensors = <&tmu 3>;
217
218			trips {
219				core_cluster_alert: core-cluster-alert {
220					temperature = <85000>;
221					hysteresis = <2000>;
222					type = "passive";
223				};
224
225				core_cluster_crit: core-cluster-crit {
226					temperature = <95000>;
227					hysteresis = <2000>;
228					type = "critical";
229				};
230			};
231
232			cooling-maps {
233				map0 {
234					trip = <&core_cluster_alert>;
235					cooling-device =
236						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
237						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
238						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
239						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
240				};
241			};
242		};
243
244		sec {
245			polling-delay-passive = <1000>;
246			polling-delay = <5000>;
247			thermal-sensors = <&tmu 4>;
248
249			trips {
250				sec-alert {
251					temperature = <85000>;
252					hysteresis = <2000>;
253					type = "passive";
254				};
255
256				sec-crit {
257					temperature = <95000>;
258					hysteresis = <2000>;
259					type = "critical";
260				};
261			};
262		};
263	};
264
265	timer {
266		compatible = "arm,armv8-timer";
267		interrupts = <1 13 0xf08>, /* Physical Secure PPI */
268			     <1 14 0xf08>, /* Physical Non-Secure PPI */
269			     <1 11 0xf08>, /* Virtual PPI */
270			     <1 10 0xf08>; /* Hypervisor PPI */
271		fsl,erratum-a008585;
272	};
273
274	pmu {
275		compatible = "arm,armv8-pmuv3";
276		interrupts = <0 106 0x4>,
277			     <0 107 0x4>,
278			     <0 95 0x4>,
279			     <0 97 0x4>;
280		interrupt-affinity = <&cpu0>,
281				     <&cpu1>,
282				     <&cpu2>,
283				     <&cpu3>;
284	};
285
286	gic: interrupt-controller@1400000 {
287		compatible = "arm,gic-400";
288		#interrupt-cells = <3>;
289		interrupt-controller;
290		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
291		      <0x0 0x1402000 0 0x2000>, /* GICC */
292		      <0x0 0x1404000 0 0x2000>, /* GICH */
293		      <0x0 0x1406000 0 0x2000>; /* GICV */
294		interrupts = <1 9 0xf08>;
295	};
296
297	soc: soc {
298		compatible = "simple-bus";
299		#address-cells = <2>;
300		#size-cells = <2>;
301		ranges;
302
303		clockgen: clocking@1ee1000 {
304			compatible = "fsl,ls1043a-clockgen";
305			reg = <0x0 0x1ee1000 0x0 0x1000>;
306			#clock-cells = <2>;
307			clocks = <&sysclk>;
308		};
309
310		scfg: scfg@1570000 {
311			compatible = "fsl,ls1043a-scfg", "syscon";
312			reg = <0x0 0x1570000 0x0 0x10000>;
313			big-endian;
314		};
315
316		crypto: crypto@1700000 {
317			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
318				     "fsl,sec-v4.0";
319			fsl,sec-era = <3>;
320			#address-cells = <1>;
321			#size-cells = <1>;
322			ranges = <0x0 0x00 0x1700000 0x100000>;
323			reg = <0x00 0x1700000 0x0 0x100000>;
324			interrupts = <0 75 0x4>;
325
326			sec_jr0: jr@10000 {
327				compatible = "fsl,sec-v5.4-job-ring",
328					     "fsl,sec-v5.0-job-ring",
329					     "fsl,sec-v4.0-job-ring";
330				reg	   = <0x10000 0x10000>;
331				interrupts = <0 71 0x4>;
332			};
333
334			sec_jr1: jr@20000 {
335				compatible = "fsl,sec-v5.4-job-ring",
336					     "fsl,sec-v5.0-job-ring",
337					     "fsl,sec-v4.0-job-ring";
338				reg	   = <0x20000 0x10000>;
339				interrupts = <0 72 0x4>;
340			};
341
342			sec_jr2: jr@30000 {
343				compatible = "fsl,sec-v5.4-job-ring",
344					     "fsl,sec-v5.0-job-ring",
345					     "fsl,sec-v4.0-job-ring";
346				reg	   = <0x30000 0x10000>;
347				interrupts = <0 73 0x4>;
348			};
349
350			sec_jr3: jr@40000 {
351				compatible = "fsl,sec-v5.4-job-ring",
352					     "fsl,sec-v5.0-job-ring",
353					     "fsl,sec-v4.0-job-ring";
354				reg	   = <0x40000 0x10000>;
355				interrupts = <0 74 0x4>;
356			};
357		};
358
359		dcfg: dcfg@1ee0000 {
360			compatible = "fsl,ls1043a-dcfg", "syscon";
361			reg = <0x0 0x1ee0000 0x0 0x10000>;
362			big-endian;
363		};
364
365		ifc: ifc@1530000 {
366			compatible = "fsl,ifc", "simple-bus";
367			reg = <0x0 0x1530000 0x0 0x10000>;
368			interrupts = <0 43 0x4>;
369		};
370
371		qspi: spi@1550000 {
372			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
373			#address-cells = <1>;
374			#size-cells = <0>;
375			reg = <0x0 0x1550000 0x0 0x10000>,
376				<0x0 0x40000000 0x0 0x4000000>;
377			reg-names = "QuadSPI", "QuadSPI-memory";
378			interrupts = <0 99 0x4>;
379			clock-names = "qspi_en", "qspi";
380			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
381			status = "disabled";
382		};
383
384		esdhc: esdhc@1560000 {
385			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
386			reg = <0x0 0x1560000 0x0 0x10000>;
387			interrupts = <0 62 0x4>;
388			clock-frequency = <0>;
389			voltage-ranges = <1800 1800 3300 3300>;
390			sdhci,auto-cmd12;
391			big-endian;
392			bus-width = <4>;
393		};
394
395		ddr: memory-controller@1080000 {
396			compatible = "fsl,qoriq-memory-controller";
397			reg = <0x0 0x1080000 0x0 0x1000>;
398			interrupts = <0 144 0x4>;
399			big-endian;
400		};
401
402		tmu: tmu@1f00000 {
403			compatible = "fsl,qoriq-tmu";
404			reg = <0x0 0x1f00000 0x0 0x10000>;
405			interrupts = <0 33 0x4>;
406			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
407			fsl,tmu-calibration = <0x00000000 0x00000023
408					       0x00000001 0x0000002a
409					       0x00000002 0x00000031
410					       0x00000003 0x00000037
411					       0x00000004 0x0000003e
412					       0x00000005 0x00000044
413					       0x00000006 0x0000004b
414					       0x00000007 0x00000051
415					       0x00000008 0x00000058
416					       0x00000009 0x0000005e
417					       0x0000000a 0x00000065
418					       0x0000000b 0x0000006b
419
420					       0x00010000 0x00000023
421					       0x00010001 0x0000002b
422					       0x00010002 0x00000033
423					       0x00010003 0x0000003b
424					       0x00010004 0x00000043
425					       0x00010005 0x0000004b
426					       0x00010006 0x00000054
427					       0x00010007 0x0000005c
428					       0x00010008 0x00000064
429					       0x00010009 0x0000006c
430
431					       0x00020000 0x00000021
432					       0x00020001 0x0000002c
433					       0x00020002 0x00000036
434					       0x00020003 0x00000040
435					       0x00020004 0x0000004b
436					       0x00020005 0x00000055
437					       0x00020006 0x0000005f
438
439					       0x00030000 0x00000013
440					       0x00030001 0x0000001d
441					       0x00030002 0x00000028
442					       0x00030003 0x00000032
443					       0x00030004 0x0000003d
444					       0x00030005 0x00000047
445					       0x00030006 0x00000052
446					       0x00030007 0x0000005c>;
447			#thermal-sensor-cells = <1>;
448		};
449
450		qman: qman@1880000 {
451			compatible = "fsl,qman";
452			reg = <0x0 0x1880000 0x0 0x10000>;
453			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
454			memory-region = <&qman_fqd &qman_pfdr>;
455		};
456
457		bman: bman@1890000 {
458			compatible = "fsl,bman";
459			reg = <0x0 0x1890000 0x0 0x10000>;
460			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
461			memory-region = <&bman_fbpr>;
462		};
463
464		bportals: bman-portals@508000000 {
465			ranges = <0x0 0x5 0x08000000 0x8000000>;
466		};
467
468		qportals: qman-portals@500000000 {
469			ranges = <0x0 0x5 0x00000000 0x8000000>;
470		};
471
472		dspi0: spi@2100000 {
473			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
474			#address-cells = <1>;
475			#size-cells = <0>;
476			reg = <0x0 0x2100000 0x0 0x10000>;
477			interrupts = <0 64 0x4>;
478			clock-names = "dspi";
479			clocks = <&clockgen 4 0>;
480			spi-num-chipselects = <5>;
481			big-endian;
482			status = "disabled";
483		};
484
485		dspi1: spi@2110000 {
486			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
487			#address-cells = <1>;
488			#size-cells = <0>;
489			reg = <0x0 0x2110000 0x0 0x10000>;
490			interrupts = <0 65 0x4>;
491			clock-names = "dspi";
492			clocks = <&clockgen 4 0>;
493			spi-num-chipselects = <5>;
494			big-endian;
495			status = "disabled";
496		};
497
498		i2c0: i2c@2180000 {
499			compatible = "fsl,vf610-i2c";
500			#address-cells = <1>;
501			#size-cells = <0>;
502			reg = <0x0 0x2180000 0x0 0x10000>;
503			interrupts = <0 56 0x4>;
504			clock-names = "i2c";
505			clocks = <&clockgen 4 0>;
506			dmas = <&edma0 1 39>,
507			       <&edma0 1 38>;
508			dma-names = "tx", "rx";
509			status = "disabled";
510		};
511
512		i2c1: i2c@2190000 {
513			compatible = "fsl,vf610-i2c";
514			#address-cells = <1>;
515			#size-cells = <0>;
516			reg = <0x0 0x2190000 0x0 0x10000>;
517			interrupts = <0 57 0x4>;
518			clock-names = "i2c";
519			clocks = <&clockgen 4 0>;
520			status = "disabled";
521		};
522
523		i2c2: i2c@21a0000 {
524			compatible = "fsl,vf610-i2c";
525			#address-cells = <1>;
526			#size-cells = <0>;
527			reg = <0x0 0x21a0000 0x0 0x10000>;
528			interrupts = <0 58 0x4>;
529			clock-names = "i2c";
530			clocks = <&clockgen 4 0>;
531			status = "disabled";
532		};
533
534		i2c3: i2c@21b0000 {
535			compatible = "fsl,vf610-i2c";
536			#address-cells = <1>;
537			#size-cells = <0>;
538			reg = <0x0 0x21b0000 0x0 0x10000>;
539			interrupts = <0 59 0x4>;
540			clock-names = "i2c";
541			clocks = <&clockgen 4 0>;
542			status = "disabled";
543		};
544
545		duart0: serial@21c0500 {
546			compatible = "fsl,ns16550", "ns16550a";
547			reg = <0x00 0x21c0500 0x0 0x100>;
548			interrupts = <0 54 0x4>;
549			clocks = <&clockgen 4 0>;
550		};
551
552		duart1: serial@21c0600 {
553			compatible = "fsl,ns16550", "ns16550a";
554			reg = <0x00 0x21c0600 0x0 0x100>;
555			interrupts = <0 54 0x4>;
556			clocks = <&clockgen 4 0>;
557		};
558
559		duart2: serial@21d0500 {
560			compatible = "fsl,ns16550", "ns16550a";
561			reg = <0x0 0x21d0500 0x0 0x100>;
562			interrupts = <0 55 0x4>;
563			clocks = <&clockgen 4 0>;
564		};
565
566		duart3: serial@21d0600 {
567			compatible = "fsl,ns16550", "ns16550a";
568			reg = <0x0 0x21d0600 0x0 0x100>;
569			interrupts = <0 55 0x4>;
570			clocks = <&clockgen 4 0>;
571		};
572
573		gpio1: gpio@2300000 {
574			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
575			reg = <0x0 0x2300000 0x0 0x10000>;
576			interrupts = <0 66 0x4>;
577			gpio-controller;
578			#gpio-cells = <2>;
579			interrupt-controller;
580			#interrupt-cells = <2>;
581		};
582
583		gpio2: gpio@2310000 {
584			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
585			reg = <0x0 0x2310000 0x0 0x10000>;
586			interrupts = <0 67 0x4>;
587			gpio-controller;
588			#gpio-cells = <2>;
589			interrupt-controller;
590			#interrupt-cells = <2>;
591		};
592
593		gpio3: gpio@2320000 {
594			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
595			reg = <0x0 0x2320000 0x0 0x10000>;
596			interrupts = <0 68 0x4>;
597			gpio-controller;
598			#gpio-cells = <2>;
599			interrupt-controller;
600			#interrupt-cells = <2>;
601		};
602
603		gpio4: gpio@2330000 {
604			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
605			reg = <0x0 0x2330000 0x0 0x10000>;
606			interrupts = <0 134 0x4>;
607			gpio-controller;
608			#gpio-cells = <2>;
609			interrupt-controller;
610			#interrupt-cells = <2>;
611		};
612
613		uqe: uqe@2400000 {
614			#address-cells = <1>;
615			#size-cells = <1>;
616			compatible = "fsl,qe", "simple-bus";
617			ranges = <0x0 0x0 0x2400000 0x40000>;
618			reg = <0x0 0x2400000 0x0 0x480>;
619			brg-frequency = <100000000>;
620			bus-frequency = <200000000>;
621			fsl,qe-num-riscs = <1>;
622			fsl,qe-num-snums = <28>;
623
624			qeic: qeic@80 {
625				compatible = "fsl,qe-ic";
626				reg = <0x80 0x80>;
627				#address-cells = <0>;
628				interrupt-controller;
629				#interrupt-cells = <1>;
630				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
631					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
632			};
633
634			si1: si@700 {
635				#address-cells = <1>;
636				#size-cells = <0>;
637				compatible = "fsl,ls1043-qe-si",
638						"fsl,t1040-qe-si";
639				reg = <0x700 0x80>;
640			};
641
642			siram1: siram@1000 {
643				#address-cells = <1>;
644				#size-cells = <1>;
645				compatible = "fsl,ls1043-qe-siram",
646						"fsl,t1040-qe-siram";
647				reg = <0x1000 0x800>;
648			};
649
650			ucc@2000 {
651				cell-index = <1>;
652				reg = <0x2000 0x200>;
653				interrupts = <32>;
654				interrupt-parent = <&qeic>;
655			};
656
657			ucc@2200 {
658				cell-index = <3>;
659				reg = <0x2200 0x200>;
660				interrupts = <34>;
661				interrupt-parent = <&qeic>;
662			};
663
664			muram@10000 {
665				#address-cells = <1>;
666				#size-cells = <1>;
667				compatible = "fsl,qe-muram", "fsl,cpm-muram";
668				ranges = <0x0 0x10000 0x6000>;
669
670				data-only@0 {
671					compatible = "fsl,qe-muram-data",
672					"fsl,cpm-muram-data";
673					reg = <0x0 0x6000>;
674				};
675			};
676		};
677
678		lpuart0: serial@2950000 {
679			compatible = "fsl,ls1021a-lpuart";
680			reg = <0x0 0x2950000 0x0 0x1000>;
681			interrupts = <0 48 0x4>;
682			clocks = <&clockgen 0 0>;
683			clock-names = "ipg";
684			status = "disabled";
685		};
686
687		lpuart1: serial@2960000 {
688			compatible = "fsl,ls1021a-lpuart";
689			reg = <0x0 0x2960000 0x0 0x1000>;
690			interrupts = <0 49 0x4>;
691			clocks = <&clockgen 4 0>;
692			clock-names = "ipg";
693			status = "disabled";
694		};
695
696		lpuart2: serial@2970000 {
697			compatible = "fsl,ls1021a-lpuart";
698			reg = <0x0 0x2970000 0x0 0x1000>;
699			interrupts = <0 50 0x4>;
700			clocks = <&clockgen 4 0>;
701			clock-names = "ipg";
702			status = "disabled";
703		};
704
705		lpuart3: serial@2980000 {
706			compatible = "fsl,ls1021a-lpuart";
707			reg = <0x0 0x2980000 0x0 0x1000>;
708			interrupts = <0 51 0x4>;
709			clocks = <&clockgen 4 0>;
710			clock-names = "ipg";
711			status = "disabled";
712		};
713
714		lpuart4: serial@2990000 {
715			compatible = "fsl,ls1021a-lpuart";
716			reg = <0x0 0x2990000 0x0 0x1000>;
717			interrupts = <0 52 0x4>;
718			clocks = <&clockgen 4 0>;
719			clock-names = "ipg";
720			status = "disabled";
721		};
722
723		lpuart5: serial@29a0000 {
724			compatible = "fsl,ls1021a-lpuart";
725			reg = <0x0 0x29a0000 0x0 0x1000>;
726			interrupts = <0 53 0x4>;
727			clocks = <&clockgen 4 0>;
728			clock-names = "ipg";
729			status = "disabled";
730		};
731
732		wdog0: watchdog@2ad0000 {
733			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
734			reg = <0x0 0x2ad0000 0x0 0x10000>;
735			interrupts = <0 83 0x4>;
736			clocks = <&clockgen 4 0>;
737			clock-names = "wdog";
738			big-endian;
739		};
740
741		edma0: edma@2c00000 {
742			#dma-cells = <2>;
743			compatible = "fsl,vf610-edma";
744			reg = <0x0 0x2c00000 0x0 0x10000>,
745			      <0x0 0x2c10000 0x0 0x10000>,
746			      <0x0 0x2c20000 0x0 0x10000>;
747			interrupts = <0 103 0x4>,
748				     <0 103 0x4>;
749			interrupt-names = "edma-tx", "edma-err";
750			dma-channels = <32>;
751			big-endian;
752			clock-names = "dmamux0", "dmamux1";
753			clocks = <&clockgen 4 0>,
754				 <&clockgen 4 0>;
755		};
756
757		usb0: usb@2f00000 {
758			compatible = "snps,dwc3";
759			reg = <0x0 0x2f00000 0x0 0x10000>;
760			interrupts = <0 60 0x4>;
761			dr_mode = "host";
762			snps,quirk-frame-length-adjustment = <0x20>;
763			snps,dis_rxdet_inp3_quirk;
764			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
765			status = "disabled";
766		};
767
768		usb1: usb@3000000 {
769			compatible = "snps,dwc3";
770			reg = <0x0 0x3000000 0x0 0x10000>;
771			interrupts = <0 61 0x4>;
772			dr_mode = "host";
773			snps,quirk-frame-length-adjustment = <0x20>;
774			snps,dis_rxdet_inp3_quirk;
775			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
776			status = "disabled";
777		};
778
779		usb2: usb@3100000 {
780			compatible = "snps,dwc3";
781			reg = <0x0 0x3100000 0x0 0x10000>;
782			interrupts = <0 63 0x4>;
783			dr_mode = "host";
784			snps,quirk-frame-length-adjustment = <0x20>;
785			snps,dis_rxdet_inp3_quirk;
786			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
787			status = "disabled";
788		};
789
790		sata: sata@3200000 {
791			compatible = "fsl,ls1043a-ahci";
792			reg = <0x0 0x3200000 0x0 0x10000>,
793				<0x0 0x20140520 0x0 0x4>;
794			reg-names = "ahci", "sata-ecc";
795			interrupts = <0 69 0x4>;
796			clocks = <&clockgen 4 0>;
797			dma-coherent;
798		};
799
800		msi1: msi-controller1@1571000 {
801			compatible = "fsl,ls1043a-msi";
802			reg = <0x0 0x1571000 0x0 0x8>;
803			msi-controller;
804			interrupts = <0 116 0x4>;
805		};
806
807		msi2: msi-controller2@1572000 {
808			compatible = "fsl,ls1043a-msi";
809			reg = <0x0 0x1572000 0x0 0x8>;
810			msi-controller;
811			interrupts = <0 126 0x4>;
812		};
813
814		msi3: msi-controller3@1573000 {
815			compatible = "fsl,ls1043a-msi";
816			reg = <0x0 0x1573000 0x0 0x8>;
817			msi-controller;
818			interrupts = <0 160 0x4>;
819		};
820
821		pcie1: pcie@3400000 {
822			compatible = "fsl,ls1043a-pcie";
823			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
824			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
825			reg-names = "regs", "config";
826			interrupts = <0 118 0x4>, /* controller interrupt */
827				     <0 117 0x4>; /* PME interrupt */
828			interrupt-names = "intr", "pme";
829			#address-cells = <3>;
830			#size-cells = <2>;
831			device_type = "pci";
832			dma-coherent;
833			num-viewport = <6>;
834			bus-range = <0x0 0xff>;
835			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
836				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
837			msi-parent = <&msi1>, <&msi2>, <&msi3>;
838			#interrupt-cells = <1>;
839			interrupt-map-mask = <0 0 0 7>;
840			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
841					<0000 0 0 2 &gic 0 111 0x4>,
842					<0000 0 0 3 &gic 0 112 0x4>,
843					<0000 0 0 4 &gic 0 113 0x4>;
844			status = "disabled";
845		};
846
847		pcie2: pcie@3500000 {
848			compatible = "fsl,ls1043a-pcie";
849			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
850			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
851			reg-names = "regs", "config";
852			interrupts = <0 128 0x4>,
853				     <0 127 0x4>;
854			interrupt-names = "intr", "pme";
855			#address-cells = <3>;
856			#size-cells = <2>;
857			device_type = "pci";
858			dma-coherent;
859			num-viewport = <6>;
860			bus-range = <0x0 0xff>;
861			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
862				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
863			msi-parent = <&msi1>, <&msi2>, <&msi3>;
864			#interrupt-cells = <1>;
865			interrupt-map-mask = <0 0 0 7>;
866			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
867					<0000 0 0 2 &gic 0 121 0x4>,
868					<0000 0 0 3 &gic 0 122 0x4>,
869					<0000 0 0 4 &gic 0 123 0x4>;
870			status = "disabled";
871		};
872
873		pcie3: pcie@3600000 {
874			compatible = "fsl,ls1043a-pcie";
875			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
876			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
877			reg-names = "regs", "config";
878			interrupts = <0 162 0x4>,
879				     <0 161 0x4>;
880			interrupt-names = "intr", "pme";
881			#address-cells = <3>;
882			#size-cells = <2>;
883			device_type = "pci";
884			dma-coherent;
885			num-viewport = <6>;
886			bus-range = <0x0 0xff>;
887			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
888				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
889			msi-parent = <&msi1>, <&msi2>, <&msi3>;
890			#interrupt-cells = <1>;
891			interrupt-map-mask = <0 0 0 7>;
892			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
893					<0000 0 0 2 &gic 0 155 0x4>,
894					<0000 0 0 3 &gic 0 156 0x4>,
895					<0000 0 0 4 &gic 0 157 0x4>;
896			status = "disabled";
897		};
898
899		qdma: dma-controller@8380000 {
900			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
901			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
902			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
903			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
904			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
905				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
906				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
907				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
908				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
909			interrupt-names = "qdma-error", "qdma-queue0",
910				"qdma-queue1", "qdma-queue2", "qdma-queue3";
911			dma-channels = <8>;
912			block-number = <1>;
913			block-offset = <0x10000>;
914			fsl,dma-queues = <2>;
915			status-sizes = <64>;
916			queue-sizes = <64 64>;
917			big-endian;
918		};
919
920		rcpm: power-controller@1ee2140 {
921			compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
922			reg = <0x0 0x1ee2140 0x0 0x4>;
923			#fsl,rcpm-wakeup-cells = <1>;
924		};
925
926		ftm_alarm0: timer@29d0000 {
927			compatible = "fsl,ls1043a-ftm-alarm";
928			reg = <0x0 0x29d0000 0x0 0x10000>;
929			fsl,rcpm-wakeup = <&rcpm 0x20000>;
930			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
931			big-endian;
932		};
933	};
934
935	firmware {
936		optee {
937			compatible = "linaro,optee-tz";
938			method = "smc";
939		};
940	};
941
942};
943
944#include "qoriq-qman-portals.dtsi"
945#include "qoriq-bman-portals.dtsi"
946