1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11/dts-v1/;
12#include "fsl-ls1043a.dtsi"
13
14/ {
15	model = "LS1043A RDB Board";
16
17	aliases {
18		serial0 = &duart0;
19		serial1 = &duart1;
20		serial2 = &duart2;
21		serial3 = &duart3;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27};
28
29&i2c0 {
30	status = "okay";
31	ina220@40 {
32		compatible = "ti,ina220";
33		reg = <0x40>;
34		shunt-resistor = <1000>;
35	};
36	adt7461a@4c {
37		compatible = "adi,adt7461";
38		reg = <0x4c>;
39	};
40	eeprom@52 {
41		compatible = "atmel,24c512";
42		reg = <0x52>;
43	};
44	eeprom@53 {
45		compatible = "atmel,24c512";
46		reg = <0x53>;
47	};
48	rtc@68 {
49		compatible = "pericom,pt7c4338";
50		reg = <0x68>;
51	};
52};
53
54&ifc {
55	status = "okay";
56	#address-cells = <2>;
57	#size-cells = <1>;
58	/* NOR, NAND Flashes and FPGA on board */
59	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
60		  0x1 0x0 0x0 0x7e800000 0x00010000
61		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
62
63		nor@0,0 {
64			compatible = "cfi-flash";
65			#address-cells = <1>;
66			#size-cells = <1>;
67			reg = <0x0 0x0 0x8000000>;
68			big-endian;
69			bank-width = <2>;
70			device-width = <1>;
71		};
72
73		nand@1,0 {
74			compatible = "fsl,ifc-nand";
75			#address-cells = <1>;
76			#size-cells = <1>;
77			reg = <0x1 0x0 0x10000>;
78		};
79
80		cpld: board-control@2,0 {
81			compatible = "fsl,ls1043ardb-cpld";
82			reg = <0x2 0x0 0x0000100>;
83		};
84};
85
86&dspi0 {
87	bus-num = <0>;
88	status = "okay";
89
90	flash@0 {
91		#address-cells = <1>;
92		#size-cells = <1>;
93		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
94		reg = <0>;
95		spi-max-frequency = <1000000>; /* input clock */
96	};
97};
98
99&duart0 {
100	status = "okay";
101};
102
103&duart1 {
104	status = "okay";
105};
106
107#include "fsl-ls1043-post.dtsi"
108
109&fman0 {
110	ethernet@e0000 {
111		phy-handle = <&qsgmii_phy1>;
112		phy-connection-type = "qsgmii";
113	};
114
115	ethernet@e2000 {
116		phy-handle = <&qsgmii_phy2>;
117		phy-connection-type = "qsgmii";
118	};
119
120	ethernet@e4000 {
121		phy-handle = <&rgmii_phy1>;
122		phy-connection-type = "rgmii-id";
123	};
124
125	ethernet@e6000 {
126		phy-handle = <&rgmii_phy2>;
127		phy-connection-type = "rgmii-id";
128	};
129
130	ethernet@e8000 {
131		phy-handle = <&qsgmii_phy3>;
132		phy-connection-type = "qsgmii";
133	};
134
135	ethernet@ea000 {
136		phy-handle = <&qsgmii_phy4>;
137		phy-connection-type = "qsgmii";
138	};
139
140	ethernet@f0000 { /* 10GEC1 */
141		phy-handle = <&aqr105_phy>;
142		phy-connection-type = "xgmii";
143	};
144
145	mdio@fc000 {
146		rgmii_phy1: ethernet-phy@1 {
147			reg = <0x1>;
148		};
149
150		rgmii_phy2: ethernet-phy@2 {
151			reg = <0x2>;
152		};
153
154		qsgmii_phy1: ethernet-phy@4 {
155			reg = <0x4>;
156		};
157
158		qsgmii_phy2: ethernet-phy@5 {
159			reg = <0x5>;
160		};
161
162		qsgmii_phy3: ethernet-phy@6 {
163			reg = <0x6>;
164		};
165
166		qsgmii_phy4: ethernet-phy@7 {
167			reg = <0x7>;
168		};
169	};
170
171	mdio@fd000 {
172		aqr105_phy: ethernet-phy@1 {
173			compatible = "ethernet-phy-ieee802.3-c45";
174			interrupts = <0 132 4>;
175			reg = <0x1>;
176		};
177	};
178};
179