1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11/dts-v1/;
12#include "fsl-ls1043a.dtsi"
13
14/ {
15	model = "LS1043A RDB Board";
16
17	aliases {
18		crypto = &crypto;
19		serial0 = &duart0;
20		serial1 = &duart1;
21		serial2 = &duart2;
22		serial3 = &duart3;
23	};
24
25	chosen {
26		stdout-path = "serial0:115200n8";
27	};
28};
29
30&i2c0 {
31	status = "okay";
32	ina220@40 {
33		compatible = "ti,ina220";
34		reg = <0x40>;
35		shunt-resistor = <1000>;
36	};
37	adt7461a@4c {
38		compatible = "adi,adt7461";
39		reg = <0x4c>;
40	};
41	eeprom@52 {
42		compatible = "atmel,24c512";
43		reg = <0x52>;
44	};
45	eeprom@53 {
46		compatible = "atmel,24c512";
47		reg = <0x53>;
48	};
49	rtc@68 {
50		compatible = "pericom,pt7c4338";
51		reg = <0x68>;
52	};
53};
54
55&ifc {
56	status = "okay";
57	#address-cells = <2>;
58	#size-cells = <1>;
59	/* NOR, NAND Flashes and FPGA on board */
60	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
61		  0x1 0x0 0x0 0x7e800000 0x00010000
62		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
63
64		nor@0,0 {
65			compatible = "cfi-flash";
66			#address-cells = <1>;
67			#size-cells = <1>;
68			reg = <0x0 0x0 0x8000000>;
69			big-endian;
70			bank-width = <2>;
71			device-width = <1>;
72		};
73
74		nand@1,0 {
75			compatible = "fsl,ifc-nand";
76			#address-cells = <1>;
77			#size-cells = <1>;
78			reg = <0x1 0x0 0x10000>;
79		};
80
81		cpld: board-control@2,0 {
82			compatible = "fsl,ls1043ardb-cpld";
83			reg = <0x2 0x0 0x0000100>;
84		};
85};
86
87&dspi0 {
88	bus-num = <0>;
89	status = "okay";
90
91	flash@0 {
92		#address-cells = <1>;
93		#size-cells = <1>;
94		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
95		reg = <0>;
96		spi-max-frequency = <1000000>; /* input clock */
97	};
98};
99
100&duart0 {
101	status = "okay";
102};
103
104&duart1 {
105	status = "okay";
106};
107
108#include "fsl-ls1043-post.dtsi"
109
110&fman0 {
111	ethernet@e0000 {
112		phy-handle = <&qsgmii_phy1>;
113		phy-connection-type = "qsgmii";
114	};
115
116	ethernet@e2000 {
117		phy-handle = <&qsgmii_phy2>;
118		phy-connection-type = "qsgmii";
119	};
120
121	ethernet@e4000 {
122		phy-handle = <&rgmii_phy1>;
123		phy-connection-type = "rgmii-txid";
124	};
125
126	ethernet@e6000 {
127		phy-handle = <&rgmii_phy2>;
128		phy-connection-type = "rgmii-txid";
129	};
130
131	ethernet@e8000 {
132		phy-handle = <&qsgmii_phy3>;
133		phy-connection-type = "qsgmii";
134	};
135
136	ethernet@ea000 {
137		phy-handle = <&qsgmii_phy4>;
138		phy-connection-type = "qsgmii";
139	};
140
141	ethernet@f0000 { /* 10GEC1 */
142		phy-handle = <&aqr105_phy>;
143		phy-connection-type = "xgmii";
144	};
145
146	mdio@fc000 {
147		rgmii_phy1: ethernet-phy@1 {
148			reg = <0x1>;
149		};
150
151		rgmii_phy2: ethernet-phy@2 {
152			reg = <0x2>;
153		};
154
155		qsgmii_phy1: ethernet-phy@4 {
156			reg = <0x4>;
157		};
158
159		qsgmii_phy2: ethernet-phy@5 {
160			reg = <0x5>;
161		};
162
163		qsgmii_phy3: ethernet-phy@6 {
164			reg = <0x6>;
165		};
166
167		qsgmii_phy4: ethernet-phy@7 {
168			reg = <0x7>;
169		};
170	};
171
172	mdio@fd000 {
173		aqr105_phy: ethernet-phy@1 {
174			compatible = "ethernet-phy-ieee802.3-c45";
175			interrupts = <0 132 4>;
176			reg = <0x1>;
177		};
178	};
179};
180