17a2aeb91SLi Yang// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2ac0ca416SShaohui Xie/* 3ac0ca416SShaohui Xie * Device Tree Include file for Freescale Layerscape-1043A family SoC. 4ac0ca416SShaohui Xie * 58637f58bSLi Yang * Copyright 2014-2015 Freescale Semiconductor, Inc. 6ac0ca416SShaohui Xie * 7ac0ca416SShaohui Xie * Mingkai Hu <Mingkai.hu@freescale.com> 8ac0ca416SShaohui Xie */ 9ac0ca416SShaohui Xie 10ac0ca416SShaohui Xie/dts-v1/; 1118486552SHongtao Jia#include "fsl-ls1043a.dtsi" 12ac0ca416SShaohui Xie 13ac0ca416SShaohui Xie/ { 14ac0ca416SShaohui Xie model = "LS1043A RDB Board"; 1563dac35bSHoria Geantă 1663dac35bSHoria Geantă aliases { 1763dac35bSHoria Geantă crypto = &crypto; 1844605b65SStuart Yoder serial0 = &duart0; 1944605b65SStuart Yoder serial1 = &duart1; 2044605b65SStuart Yoder serial2 = &duart2; 2144605b65SStuart Yoder serial3 = &duart3; 2263dac35bSHoria Geantă }; 23d5c8b122SStuart Yoder 24d5c8b122SStuart Yoder chosen { 25d5c8b122SStuart Yoder stdout-path = "serial0:115200n8"; 26d5c8b122SStuart Yoder }; 27ac0ca416SShaohui Xie}; 28ac0ca416SShaohui Xie 29ac0ca416SShaohui Xie&i2c0 { 30ac0ca416SShaohui Xie status = "okay"; 31ac0ca416SShaohui Xie ina220@40 { 32ac0ca416SShaohui Xie compatible = "ti,ina220"; 33ac0ca416SShaohui Xie reg = <0x40>; 34ac0ca416SShaohui Xie shunt-resistor = <1000>; 35ac0ca416SShaohui Xie }; 36ac0ca416SShaohui Xie adt7461a@4c { 37ac0ca416SShaohui Xie compatible = "adi,adt7461"; 38ac0ca416SShaohui Xie reg = <0x4c>; 39ac0ca416SShaohui Xie }; 40ac0ca416SShaohui Xie eeprom@52 { 41f218868bSJavier Martinez Canillas compatible = "atmel,24c512"; 42ac0ca416SShaohui Xie reg = <0x52>; 43ac0ca416SShaohui Xie }; 44ac0ca416SShaohui Xie eeprom@53 { 45f218868bSJavier Martinez Canillas compatible = "atmel,24c512"; 46ac0ca416SShaohui Xie reg = <0x53>; 47ac0ca416SShaohui Xie }; 48ac0ca416SShaohui Xie rtc@68 { 49ac0ca416SShaohui Xie compatible = "pericom,pt7c4338"; 50ac0ca416SShaohui Xie reg = <0x68>; 51ac0ca416SShaohui Xie }; 52ac0ca416SShaohui Xie}; 53ac0ca416SShaohui Xie 54ac0ca416SShaohui Xie&ifc { 55ac0ca416SShaohui Xie status = "okay"; 56ac0ca416SShaohui Xie #address-cells = <2>; 57ac0ca416SShaohui Xie #size-cells = <1>; 58ac0ca416SShaohui Xie /* NOR, NAND Flashes and FPGA on board */ 59ac0ca416SShaohui Xie ranges = <0x0 0x0 0x0 0x60000000 0x08000000 60ac0ca416SShaohui Xie 0x1 0x0 0x0 0x7e800000 0x00010000 61ac0ca416SShaohui Xie 0x2 0x0 0x0 0x7fb00000 0x00000100>; 62ac0ca416SShaohui Xie 63ac0ca416SShaohui Xie nor@0,0 { 64ac0ca416SShaohui Xie compatible = "cfi-flash"; 65ac0ca416SShaohui Xie #address-cells = <1>; 66ac0ca416SShaohui Xie #size-cells = <1>; 67ac0ca416SShaohui Xie reg = <0x0 0x0 0x8000000>; 68ac0ca416SShaohui Xie bank-width = <2>; 69ac0ca416SShaohui Xie device-width = <1>; 70ac0ca416SShaohui Xie }; 71ac0ca416SShaohui Xie 72ac0ca416SShaohui Xie nand@1,0 { 73ac0ca416SShaohui Xie compatible = "fsl,ifc-nand"; 74ac0ca416SShaohui Xie #address-cells = <1>; 75ac0ca416SShaohui Xie #size-cells = <1>; 76ac0ca416SShaohui Xie reg = <0x1 0x0 0x10000>; 77ac0ca416SShaohui Xie }; 78ac0ca416SShaohui Xie 79ac0ca416SShaohui Xie cpld: board-control@2,0 { 80ac0ca416SShaohui Xie compatible = "fsl,ls1043ardb-cpld"; 81ac0ca416SShaohui Xie reg = <0x2 0x0 0x0000100>; 82ac0ca416SShaohui Xie }; 83ac0ca416SShaohui Xie}; 84ac0ca416SShaohui Xie 85730628f0SYunhui Cui&dspi0 { 86730628f0SYunhui Cui bus-num = <0>; 87730628f0SYunhui Cui status = "okay"; 88730628f0SYunhui Cui 89730628f0SYunhui Cui flash@0 { 90730628f0SYunhui Cui #address-cells = <1>; 91730628f0SYunhui Cui #size-cells = <1>; 92730628f0SYunhui Cui compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ 93730628f0SYunhui Cui reg = <0>; 94730628f0SYunhui Cui spi-max-frequency = <1000000>; /* input clock */ 95730628f0SYunhui Cui }; 96730628f0SYunhui Cui}; 97730628f0SYunhui Cui 98ac0ca416SShaohui Xie&duart0 { 99ac0ca416SShaohui Xie status = "okay"; 100ac0ca416SShaohui Xie}; 101ac0ca416SShaohui Xie 102ac0ca416SShaohui Xie&duart1 { 103ac0ca416SShaohui Xie status = "okay"; 104ac0ca416SShaohui Xie}; 105bf02f2ffSMadalin Bucur 106bf02f2ffSMadalin Bucur#include "fsl-ls1043-post.dtsi" 107bf02f2ffSMadalin Bucur 108bf02f2ffSMadalin Bucur&fman0 { 109bf02f2ffSMadalin Bucur ethernet@e0000 { 110bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy1>; 111bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 112bf02f2ffSMadalin Bucur }; 113bf02f2ffSMadalin Bucur 114bf02f2ffSMadalin Bucur ethernet@e2000 { 115bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy2>; 116bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 117bf02f2ffSMadalin Bucur }; 118bf02f2ffSMadalin Bucur 119bf02f2ffSMadalin Bucur ethernet@e4000 { 120bf02f2ffSMadalin Bucur phy-handle = <&rgmii_phy1>; 121bf02f2ffSMadalin Bucur phy-connection-type = "rgmii-txid"; 122bf02f2ffSMadalin Bucur }; 123bf02f2ffSMadalin Bucur 124bf02f2ffSMadalin Bucur ethernet@e6000 { 125bf02f2ffSMadalin Bucur phy-handle = <&rgmii_phy2>; 126bf02f2ffSMadalin Bucur phy-connection-type = "rgmii-txid"; 127bf02f2ffSMadalin Bucur }; 128bf02f2ffSMadalin Bucur 129bf02f2ffSMadalin Bucur ethernet@e8000 { 130bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy3>; 131bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 132bf02f2ffSMadalin Bucur }; 133bf02f2ffSMadalin Bucur 134bf02f2ffSMadalin Bucur ethernet@ea000 { 135bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy4>; 136bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 137bf02f2ffSMadalin Bucur }; 138bf02f2ffSMadalin Bucur 139bf02f2ffSMadalin Bucur ethernet@f0000 { /* 10GEC1 */ 140bf02f2ffSMadalin Bucur phy-handle = <&aqr105_phy>; 141bf02f2ffSMadalin Bucur phy-connection-type = "xgmii"; 142bf02f2ffSMadalin Bucur }; 143bf02f2ffSMadalin Bucur 144bf02f2ffSMadalin Bucur mdio@fc000 { 145bf02f2ffSMadalin Bucur rgmii_phy1: ethernet-phy@1 { 146bf02f2ffSMadalin Bucur reg = <0x1>; 147bf02f2ffSMadalin Bucur }; 148bf02f2ffSMadalin Bucur 149bf02f2ffSMadalin Bucur rgmii_phy2: ethernet-phy@2 { 150bf02f2ffSMadalin Bucur reg = <0x2>; 151bf02f2ffSMadalin Bucur }; 152bf02f2ffSMadalin Bucur 153bf02f2ffSMadalin Bucur qsgmii_phy1: ethernet-phy@4 { 154bf02f2ffSMadalin Bucur reg = <0x4>; 155bf02f2ffSMadalin Bucur }; 156bf02f2ffSMadalin Bucur 157bf02f2ffSMadalin Bucur qsgmii_phy2: ethernet-phy@5 { 158bf02f2ffSMadalin Bucur reg = <0x5>; 159bf02f2ffSMadalin Bucur }; 160bf02f2ffSMadalin Bucur 161bf02f2ffSMadalin Bucur qsgmii_phy3: ethernet-phy@6 { 162bf02f2ffSMadalin Bucur reg = <0x6>; 163bf02f2ffSMadalin Bucur }; 164bf02f2ffSMadalin Bucur 165bf02f2ffSMadalin Bucur qsgmii_phy4: ethernet-phy@7 { 166bf02f2ffSMadalin Bucur reg = <0x7>; 167bf02f2ffSMadalin Bucur }; 168bf02f2ffSMadalin Bucur }; 169bf02f2ffSMadalin Bucur 170bf02f2ffSMadalin Bucur mdio@fd000 { 171bf02f2ffSMadalin Bucur aqr105_phy: ethernet-phy@1 { 172bf02f2ffSMadalin Bucur compatible = "ethernet-phy-ieee802.3-c45"; 173bf02f2ffSMadalin Bucur interrupts = <0 132 4>; 174bf02f2ffSMadalin Bucur reg = <0x1>; 175bf02f2ffSMadalin Bucur }; 176bf02f2ffSMadalin Bucur }; 177bf02f2ffSMadalin Bucur}; 178