17a2aeb91SLi Yang// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2ac0ca416SShaohui Xie/* 3ac0ca416SShaohui Xie * Device Tree Include file for Freescale Layerscape-1043A family SoC. 4ac0ca416SShaohui Xie * 58637f58bSLi Yang * Copyright 2014-2015 Freescale Semiconductor, Inc. 603444ad8SPrabhakar Kushwaha * Copyright 2018 NXP 7ac0ca416SShaohui Xie * 8ac0ca416SShaohui Xie * Mingkai Hu <Mingkai.hu@freescale.com> 9ac0ca416SShaohui Xie */ 10ac0ca416SShaohui Xie 11ac0ca416SShaohui Xie/dts-v1/; 1218486552SHongtao Jia#include "fsl-ls1043a.dtsi" 13ac0ca416SShaohui Xie 14ac0ca416SShaohui Xie/ { 15ac0ca416SShaohui Xie model = "LS1043A RDB Board"; 16fa578d4eSYangbo Lu compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; 1763dac35bSHoria Geantă 1863dac35bSHoria Geantă aliases { 1944605b65SStuart Yoder serial0 = &duart0; 2044605b65SStuart Yoder serial1 = &duart1; 2144605b65SStuart Yoder serial2 = &duart2; 2244605b65SStuart Yoder serial3 = &duart3; 2363dac35bSHoria Geantă }; 24d5c8b122SStuart Yoder 25d5c8b122SStuart Yoder chosen { 26d5c8b122SStuart Yoder stdout-path = "serial0:115200n8"; 27d5c8b122SStuart Yoder }; 28ac0ca416SShaohui Xie}; 29ac0ca416SShaohui Xie 30ac0ca416SShaohui Xie&i2c0 { 31ac0ca416SShaohui Xie status = "okay"; 32ac0ca416SShaohui Xie ina220@40 { 33ac0ca416SShaohui Xie compatible = "ti,ina220"; 34ac0ca416SShaohui Xie reg = <0x40>; 35ac0ca416SShaohui Xie shunt-resistor = <1000>; 36ac0ca416SShaohui Xie }; 37ac0ca416SShaohui Xie adt7461a@4c { 38ac0ca416SShaohui Xie compatible = "adi,adt7461"; 39ac0ca416SShaohui Xie reg = <0x4c>; 40ac0ca416SShaohui Xie }; 41ac0ca416SShaohui Xie eeprom@52 { 42f218868bSJavier Martinez Canillas compatible = "atmel,24c512"; 43ac0ca416SShaohui Xie reg = <0x52>; 44ac0ca416SShaohui Xie }; 45ac0ca416SShaohui Xie eeprom@53 { 46f218868bSJavier Martinez Canillas compatible = "atmel,24c512"; 47ac0ca416SShaohui Xie reg = <0x53>; 48ac0ca416SShaohui Xie }; 49ac0ca416SShaohui Xie rtc@68 { 50ac0ca416SShaohui Xie compatible = "pericom,pt7c4338"; 51ac0ca416SShaohui Xie reg = <0x68>; 52ac0ca416SShaohui Xie }; 53ac0ca416SShaohui Xie}; 54ac0ca416SShaohui Xie 55ac0ca416SShaohui Xie&ifc { 56ac0ca416SShaohui Xie status = "okay"; 57ac0ca416SShaohui Xie #address-cells = <2>; 58ac0ca416SShaohui Xie #size-cells = <1>; 59ac0ca416SShaohui Xie /* NOR, NAND Flashes and FPGA on board */ 60ac0ca416SShaohui Xie ranges = <0x0 0x0 0x0 0x60000000 0x08000000 61ac0ca416SShaohui Xie 0x1 0x0 0x0 0x7e800000 0x00010000 62ac0ca416SShaohui Xie 0x2 0x0 0x0 0x7fb00000 0x00000100>; 63ac0ca416SShaohui Xie 64ac0ca416SShaohui Xie nor@0,0 { 65ac0ca416SShaohui Xie compatible = "cfi-flash"; 66ac0ca416SShaohui Xie #address-cells = <1>; 67ac0ca416SShaohui Xie #size-cells = <1>; 68ac0ca416SShaohui Xie reg = <0x0 0x0 0x8000000>; 6903444ad8SPrabhakar Kushwaha big-endian; 70ac0ca416SShaohui Xie bank-width = <2>; 71ac0ca416SShaohui Xie device-width = <1>; 72ac0ca416SShaohui Xie }; 73ac0ca416SShaohui Xie 74ac0ca416SShaohui Xie nand@1,0 { 75ac0ca416SShaohui Xie compatible = "fsl,ifc-nand"; 76ac0ca416SShaohui Xie #address-cells = <1>; 77ac0ca416SShaohui Xie #size-cells = <1>; 78ac0ca416SShaohui Xie reg = <0x1 0x0 0x10000>; 79ac0ca416SShaohui Xie }; 80ac0ca416SShaohui Xie 81ac0ca416SShaohui Xie cpld: board-control@2,0 { 82ac0ca416SShaohui Xie compatible = "fsl,ls1043ardb-cpld"; 83ac0ca416SShaohui Xie reg = <0x2 0x0 0x0000100>; 84ac0ca416SShaohui Xie }; 85ac0ca416SShaohui Xie}; 86ac0ca416SShaohui Xie 87730628f0SYunhui Cui&dspi0 { 88730628f0SYunhui Cui bus-num = <0>; 89730628f0SYunhui Cui status = "okay"; 90730628f0SYunhui Cui 91730628f0SYunhui Cui flash@0 { 92730628f0SYunhui Cui #address-cells = <1>; 93730628f0SYunhui Cui #size-cells = <1>; 94730628f0SYunhui Cui compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ 95730628f0SYunhui Cui reg = <0>; 96730628f0SYunhui Cui spi-max-frequency = <1000000>; /* input clock */ 97730628f0SYunhui Cui }; 98730628f0SYunhui Cui}; 99730628f0SYunhui Cui 100ac0ca416SShaohui Xie&duart0 { 101ac0ca416SShaohui Xie status = "okay"; 102ac0ca416SShaohui Xie}; 103ac0ca416SShaohui Xie 104ac0ca416SShaohui Xie&duart1 { 105ac0ca416SShaohui Xie status = "okay"; 106ac0ca416SShaohui Xie}; 107bf02f2ffSMadalin Bucur 108bf02f2ffSMadalin Bucur#include "fsl-ls1043-post.dtsi" 109bf02f2ffSMadalin Bucur 110bf02f2ffSMadalin Bucur&fman0 { 111bf02f2ffSMadalin Bucur ethernet@e0000 { 112bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy1>; 113bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 114bf02f2ffSMadalin Bucur }; 115bf02f2ffSMadalin Bucur 116bf02f2ffSMadalin Bucur ethernet@e2000 { 117bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy2>; 118bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 119bf02f2ffSMadalin Bucur }; 120bf02f2ffSMadalin Bucur 121bf02f2ffSMadalin Bucur ethernet@e4000 { 122bf02f2ffSMadalin Bucur phy-handle = <&rgmii_phy1>; 1234022d808SMadalin Bucur phy-connection-type = "rgmii-id"; 124bf02f2ffSMadalin Bucur }; 125bf02f2ffSMadalin Bucur 126bf02f2ffSMadalin Bucur ethernet@e6000 { 127bf02f2ffSMadalin Bucur phy-handle = <&rgmii_phy2>; 1284022d808SMadalin Bucur phy-connection-type = "rgmii-id"; 129bf02f2ffSMadalin Bucur }; 130bf02f2ffSMadalin Bucur 131bf02f2ffSMadalin Bucur ethernet@e8000 { 132bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy3>; 133bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 134bf02f2ffSMadalin Bucur }; 135bf02f2ffSMadalin Bucur 136bf02f2ffSMadalin Bucur ethernet@ea000 { 137bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy4>; 138bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 139bf02f2ffSMadalin Bucur }; 140bf02f2ffSMadalin Bucur 141bf02f2ffSMadalin Bucur ethernet@f0000 { /* 10GEC1 */ 142bf02f2ffSMadalin Bucur phy-handle = <&aqr105_phy>; 143bf02f2ffSMadalin Bucur phy-connection-type = "xgmii"; 144bf02f2ffSMadalin Bucur }; 145bf02f2ffSMadalin Bucur 146bf02f2ffSMadalin Bucur mdio@fc000 { 147bf02f2ffSMadalin Bucur rgmii_phy1: ethernet-phy@1 { 148bf02f2ffSMadalin Bucur reg = <0x1>; 149bf02f2ffSMadalin Bucur }; 150bf02f2ffSMadalin Bucur 151bf02f2ffSMadalin Bucur rgmii_phy2: ethernet-phy@2 { 152bf02f2ffSMadalin Bucur reg = <0x2>; 153bf02f2ffSMadalin Bucur }; 154bf02f2ffSMadalin Bucur 155bf02f2ffSMadalin Bucur qsgmii_phy1: ethernet-phy@4 { 156bf02f2ffSMadalin Bucur reg = <0x4>; 157bf02f2ffSMadalin Bucur }; 158bf02f2ffSMadalin Bucur 159bf02f2ffSMadalin Bucur qsgmii_phy2: ethernet-phy@5 { 160bf02f2ffSMadalin Bucur reg = <0x5>; 161bf02f2ffSMadalin Bucur }; 162bf02f2ffSMadalin Bucur 163bf02f2ffSMadalin Bucur qsgmii_phy3: ethernet-phy@6 { 164bf02f2ffSMadalin Bucur reg = <0x6>; 165bf02f2ffSMadalin Bucur }; 166bf02f2ffSMadalin Bucur 167bf02f2ffSMadalin Bucur qsgmii_phy4: ethernet-phy@7 { 168bf02f2ffSMadalin Bucur reg = <0x7>; 169bf02f2ffSMadalin Bucur }; 170bf02f2ffSMadalin Bucur }; 171bf02f2ffSMadalin Bucur 172bf02f2ffSMadalin Bucur mdio@fd000 { 173bf02f2ffSMadalin Bucur aqr105_phy: ethernet-phy@1 { 174bf02f2ffSMadalin Bucur compatible = "ethernet-phy-ieee802.3-c45"; 175bf02f2ffSMadalin Bucur interrupts = <0 132 4>; 176bf02f2ffSMadalin Bucur reg = <0x1>; 177bf02f2ffSMadalin Bucur }; 178bf02f2ffSMadalin Bucur }; 179bf02f2ffSMadalin Bucur}; 18076afd7dbSZhao Qiang 18176afd7dbSZhao Qiang&uqe { 18276afd7dbSZhao Qiang ucc_hdlc: ucc@2000 { 18376afd7dbSZhao Qiang compatible = "fsl,ucc-hdlc"; 18476afd7dbSZhao Qiang rx-clock-name = "clk8"; 18576afd7dbSZhao Qiang tx-clock-name = "clk9"; 18676afd7dbSZhao Qiang fsl,rx-sync-clock = "rsync_pin"; 18776afd7dbSZhao Qiang fsl,tx-sync-clock = "tsync_pin"; 18876afd7dbSZhao Qiang fsl,tx-timeslot-mask = <0xfffffffe>; 18976afd7dbSZhao Qiang fsl,rx-timeslot-mask = <0xfffffffe>; 19076afd7dbSZhao Qiang fsl,tdm-framer-type = "e1"; 19176afd7dbSZhao Qiang fsl,tdm-id = <0>; 19276afd7dbSZhao Qiang fsl,siram-entry-id = <0>; 19376afd7dbSZhao Qiang fsl,tdm-interface; 19476afd7dbSZhao Qiang }; 19576afd7dbSZhao Qiang}; 196