1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a72"; 28 reg = <0x0>; 29 enable-method = "psci"; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 next-level-cache = <&l2>; 32 cpu-idle-states = <&CPU_PW20>; 33 #cooling-cells = <2>; 34 }; 35 36 cpu1: cpu@1 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a72"; 39 reg = <0x1>; 40 enable-method = "psci"; 41 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 42 next-level-cache = <&l2>; 43 cpu-idle-states = <&CPU_PW20>; 44 #cooling-cells = <2>; 45 }; 46 47 l2: l2-cache { 48 compatible = "cache"; 49 }; 50 }; 51 52 idle-states { 53 /* 54 * PSCI node is not added default, U-boot will add missing 55 * parts if it determines to use PSCI. 56 */ 57 entry-method = "psci"; 58 59 CPU_PW20: cpu-pw20 { 60 compatible = "arm,idle-state"; 61 idle-state-name = "PW20"; 62 arm,psci-suspend-param = <0x0>; 63 entry-latency-us = <2000>; 64 exit-latency-us = <2000>; 65 min-residency-us = <6000>; 66 }; 67 }; 68 69 rtc_clk: rtc-clk { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <32768>; 73 clock-output-names = "rtc_clk"; 74 }; 75 76 sysclk: sysclk { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <100000000>; 80 clock-output-names = "sysclk"; 81 }; 82 83 osc_27m: clock-osc-27m { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <27000000>; 87 clock-output-names = "phy_27m"; 88 }; 89 90 firmware { 91 optee: optee { 92 compatible = "linaro,optee-tz"; 93 method = "smc"; 94 status = "disabled"; 95 }; 96 }; 97 98 reboot { 99 compatible = "syscon-reboot"; 100 regmap = <&rst>; 101 offset = <0>; 102 mask = <0x02>; 103 }; 104 105 timer { 106 compatible = "arm,armv8-timer"; 107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 108 IRQ_TYPE_LEVEL_LOW)>, 109 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 110 IRQ_TYPE_LEVEL_LOW)>, 111 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 112 IRQ_TYPE_LEVEL_LOW)>, 113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 114 IRQ_TYPE_LEVEL_LOW)>; 115 }; 116 117 pmu { 118 compatible = "arm,cortex-a72-pmu"; 119 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 120 }; 121 122 gic: interrupt-controller@6000000 { 123 compatible = "arm,gic-v3"; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges; 127 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 128 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 129 #interrupt-cells = <3>; 130 interrupt-controller; 131 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 132 IRQ_TYPE_LEVEL_LOW)>; 133 its: gic-its@6020000 { 134 compatible = "arm,gic-v3-its"; 135 msi-controller; 136 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 137 }; 138 }; 139 140 thermal-zones { 141 ddr-controller { 142 polling-delay-passive = <1000>; 143 polling-delay = <5000>; 144 thermal-sensors = <&tmu 0>; 145 146 trips { 147 ddr-ctrler-alert { 148 temperature = <85000>; 149 hysteresis = <2000>; 150 type = "passive"; 151 }; 152 153 ddr-ctrler-crit { 154 temperature = <95000>; 155 hysteresis = <2000>; 156 type = "critical"; 157 }; 158 }; 159 }; 160 161 core-cluster { 162 polling-delay-passive = <1000>; 163 polling-delay = <5000>; 164 thermal-sensors = <&tmu 1>; 165 166 trips { 167 core_cluster_alert: core-cluster-alert { 168 temperature = <85000>; 169 hysteresis = <2000>; 170 type = "passive"; 171 }; 172 173 core_cluster_crit: core-cluster-crit { 174 temperature = <95000>; 175 hysteresis = <2000>; 176 type = "critical"; 177 }; 178 }; 179 180 cooling-maps { 181 map0 { 182 trip = <&core_cluster_alert>; 183 cooling-device = 184 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 186 }; 187 }; 188 }; 189 }; 190 191 soc: soc { 192 compatible = "simple-bus"; 193 #address-cells = <2>; 194 #size-cells = <2>; 195 ranges; 196 197 ddr: memory-controller@1080000 { 198 compatible = "fsl,qoriq-memory-controller"; 199 reg = <0x0 0x1080000 0x0 0x1000>; 200 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 201 little-endian; 202 }; 203 204 dcfg: syscon@1e00000 { 205 #address-cells = <1>; 206 #size-cells = <1>; 207 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 208 reg = <0x0 0x1e00000 0x0 0x10000>; 209 ranges = <0x0 0x0 0x1e00000 0x10000>; 210 little-endian; 211 212 fspi_clk: clock-controller@900 { 213 compatible = "fsl,ls1028a-flexspi-clk"; 214 reg = <0x900 0x4>; 215 #clock-cells = <0>; 216 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 217 clock-output-names = "fspi_clk"; 218 }; 219 }; 220 221 rst: syscon@1e60000 { 222 compatible = "syscon"; 223 reg = <0x0 0x1e60000 0x0 0x10000>; 224 little-endian; 225 }; 226 227 sfp: efuse@1e80000 { 228 compatible = "fsl,ls1028a-sfp"; 229 reg = <0x0 0x1e80000 0x0 0x10000>; 230 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 231 QORIQ_CLK_PLL_DIV(4)>; 232 clock-names = "sfp"; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 236 ls1028a_uid: unique-id@1c { 237 reg = <0x1c 0x8>; 238 }; 239 }; 240 241 scfg: syscon@1fc0000 { 242 compatible = "fsl,ls1028a-scfg", "syscon"; 243 reg = <0x0 0x1fc0000 0x0 0x10000>; 244 big-endian; 245 }; 246 247 clockgen: clock-controller@1300000 { 248 compatible = "fsl,ls1028a-clockgen"; 249 reg = <0x0 0x1300000 0x0 0xa0000>; 250 #clock-cells = <2>; 251 clocks = <&sysclk>; 252 }; 253 254 i2c0: i2c@2000000 { 255 compatible = "fsl,vf610-i2c"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 reg = <0x0 0x2000000 0x0 0x10000>; 259 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 261 QORIQ_CLK_PLL_DIV(4)>; 262 status = "disabled"; 263 }; 264 265 i2c1: i2c@2010000 { 266 compatible = "fsl,vf610-i2c"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 reg = <0x0 0x2010000 0x0 0x10000>; 270 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 272 QORIQ_CLK_PLL_DIV(4)>; 273 status = "disabled"; 274 }; 275 276 i2c2: i2c@2020000 { 277 compatible = "fsl,vf610-i2c"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <0x0 0x2020000 0x0 0x10000>; 281 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 283 QORIQ_CLK_PLL_DIV(4)>; 284 status = "disabled"; 285 }; 286 287 i2c3: i2c@2030000 { 288 compatible = "fsl,vf610-i2c"; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 reg = <0x0 0x2030000 0x0 0x10000>; 292 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 294 QORIQ_CLK_PLL_DIV(4)>; 295 status = "disabled"; 296 }; 297 298 i2c4: i2c@2040000 { 299 compatible = "fsl,vf610-i2c"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 reg = <0x0 0x2040000 0x0 0x10000>; 303 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 305 QORIQ_CLK_PLL_DIV(4)>; 306 status = "disabled"; 307 }; 308 309 i2c5: i2c@2050000 { 310 compatible = "fsl,vf610-i2c"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 reg = <0x0 0x2050000 0x0 0x10000>; 314 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 316 QORIQ_CLK_PLL_DIV(4)>; 317 status = "disabled"; 318 }; 319 320 i2c6: i2c@2060000 { 321 compatible = "fsl,vf610-i2c"; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 reg = <0x0 0x2060000 0x0 0x10000>; 325 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 327 QORIQ_CLK_PLL_DIV(4)>; 328 status = "disabled"; 329 }; 330 331 i2c7: i2c@2070000 { 332 compatible = "fsl,vf610-i2c"; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 reg = <0x0 0x2070000 0x0 0x10000>; 336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 338 QORIQ_CLK_PLL_DIV(4)>; 339 status = "disabled"; 340 }; 341 342 fspi: spi@20c0000 { 343 compatible = "nxp,lx2160a-fspi"; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 reg = <0x0 0x20c0000 0x0 0x10000>, 347 <0x0 0x20000000 0x0 0x10000000>; 348 reg-names = "fspi_base", "fspi_mmap"; 349 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&fspi_clk>, <&fspi_clk>; 351 clock-names = "fspi_en", "fspi"; 352 status = "disabled"; 353 }; 354 355 dspi0: spi@2100000 { 356 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 reg = <0x0 0x2100000 0x0 0x10000>; 360 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 361 clock-names = "dspi"; 362 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 363 QORIQ_CLK_PLL_DIV(2)>; 364 dmas = <&edma0 0 62>, <&edma0 0 60>; 365 dma-names = "tx", "rx"; 366 spi-num-chipselects = <4>; 367 little-endian; 368 status = "disabled"; 369 }; 370 371 dspi1: spi@2110000 { 372 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 reg = <0x0 0x2110000 0x0 0x10000>; 376 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 377 clock-names = "dspi"; 378 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 379 QORIQ_CLK_PLL_DIV(2)>; 380 dmas = <&edma0 0 58>, <&edma0 0 56>; 381 dma-names = "tx", "rx"; 382 spi-num-chipselects = <4>; 383 little-endian; 384 status = "disabled"; 385 }; 386 387 dspi2: spi@2120000 { 388 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 reg = <0x0 0x2120000 0x0 0x10000>; 392 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 393 clock-names = "dspi"; 394 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 395 QORIQ_CLK_PLL_DIV(2)>; 396 dmas = <&edma0 0 54>, <&edma0 0 2>; 397 dma-names = "tx", "rx"; 398 spi-num-chipselects = <3>; 399 little-endian; 400 status = "disabled"; 401 }; 402 403 esdhc: mmc@2140000 { 404 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 405 reg = <0x0 0x2140000 0x0 0x10000>; 406 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 407 clock-frequency = <0>; /* fixed up by bootloader */ 408 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 409 voltage-ranges = <1800 1800 3300 3300>; 410 sdhci,auto-cmd12; 411 little-endian; 412 bus-width = <4>; 413 status = "disabled"; 414 }; 415 416 esdhc1: mmc@2150000 { 417 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 418 reg = <0x0 0x2150000 0x0 0x10000>; 419 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 420 clock-frequency = <0>; /* fixed up by bootloader */ 421 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 422 voltage-ranges = <1800 1800>; 423 sdhci,auto-cmd12; 424 non-removable; 425 little-endian; 426 bus-width = <4>; 427 status = "disabled"; 428 }; 429 430 can0: can@2180000 { 431 compatible = "fsl,lx2160ar1-flexcan"; 432 reg = <0x0 0x2180000 0x0 0x10000>; 433 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 435 QORIQ_CLK_PLL_DIV(2)>, 436 <&clockgen QORIQ_CLK_PLATFORM_PLL 437 QORIQ_CLK_PLL_DIV(2)>; 438 clock-names = "ipg", "per"; 439 status = "disabled"; 440 }; 441 442 can1: can@2190000 { 443 compatible = "fsl,lx2160ar1-flexcan"; 444 reg = <0x0 0x2190000 0x0 0x10000>; 445 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 447 QORIQ_CLK_PLL_DIV(2)>, 448 <&clockgen QORIQ_CLK_PLATFORM_PLL 449 QORIQ_CLK_PLL_DIV(2)>; 450 clock-names = "ipg", "per"; 451 status = "disabled"; 452 }; 453 454 duart0: serial@21c0500 { 455 compatible = "fsl,ns16550", "ns16550a"; 456 reg = <0x00 0x21c0500 0x0 0x100>; 457 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 459 QORIQ_CLK_PLL_DIV(2)>; 460 status = "disabled"; 461 }; 462 463 duart1: serial@21c0600 { 464 compatible = "fsl,ns16550", "ns16550a"; 465 reg = <0x00 0x21c0600 0x0 0x100>; 466 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 468 QORIQ_CLK_PLL_DIV(2)>; 469 status = "disabled"; 470 }; 471 472 473 lpuart0: serial@2260000 { 474 compatible = "fsl,ls1028a-lpuart"; 475 reg = <0x0 0x2260000 0x0 0x1000>; 476 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 478 QORIQ_CLK_PLL_DIV(2)>; 479 clock-names = "ipg"; 480 dma-names = "rx","tx"; 481 dmas = <&edma0 1 32>, 482 <&edma0 1 33>; 483 status = "disabled"; 484 }; 485 486 lpuart1: serial@2270000 { 487 compatible = "fsl,ls1028a-lpuart"; 488 reg = <0x0 0x2270000 0x0 0x1000>; 489 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 491 QORIQ_CLK_PLL_DIV(2)>; 492 clock-names = "ipg"; 493 dma-names = "rx","tx"; 494 dmas = <&edma0 1 30>, 495 <&edma0 1 31>; 496 status = "disabled"; 497 }; 498 499 lpuart2: serial@2280000 { 500 compatible = "fsl,ls1028a-lpuart"; 501 reg = <0x0 0x2280000 0x0 0x1000>; 502 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 504 QORIQ_CLK_PLL_DIV(2)>; 505 clock-names = "ipg"; 506 dma-names = "rx","tx"; 507 dmas = <&edma0 1 28>, 508 <&edma0 1 29>; 509 status = "disabled"; 510 }; 511 512 lpuart3: serial@2290000 { 513 compatible = "fsl,ls1028a-lpuart"; 514 reg = <0x0 0x2290000 0x0 0x1000>; 515 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 517 QORIQ_CLK_PLL_DIV(2)>; 518 clock-names = "ipg"; 519 dma-names = "rx","tx"; 520 dmas = <&edma0 1 26>, 521 <&edma0 1 27>; 522 status = "disabled"; 523 }; 524 525 lpuart4: serial@22a0000 { 526 compatible = "fsl,ls1028a-lpuart"; 527 reg = <0x0 0x22a0000 0x0 0x1000>; 528 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 530 QORIQ_CLK_PLL_DIV(2)>; 531 clock-names = "ipg"; 532 dma-names = "rx","tx"; 533 dmas = <&edma0 1 24>, 534 <&edma0 1 25>; 535 status = "disabled"; 536 }; 537 538 lpuart5: serial@22b0000 { 539 compatible = "fsl,ls1028a-lpuart"; 540 reg = <0x0 0x22b0000 0x0 0x1000>; 541 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 543 QORIQ_CLK_PLL_DIV(2)>; 544 clock-names = "ipg"; 545 dma-names = "rx","tx"; 546 dmas = <&edma0 1 22>, 547 <&edma0 1 23>; 548 status = "disabled"; 549 }; 550 551 edma0: dma-controller@22c0000 { 552 #dma-cells = <2>; 553 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 554 reg = <0x0 0x22c0000 0x0 0x10000>, 555 <0x0 0x22d0000 0x0 0x10000>, 556 <0x0 0x22e0000 0x0 0x10000>; 557 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 559 interrupt-names = "edma-tx", "edma-err"; 560 dma-channels = <32>; 561 clock-names = "dmamux0", "dmamux1"; 562 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 563 QORIQ_CLK_PLL_DIV(2)>, 564 <&clockgen QORIQ_CLK_PLATFORM_PLL 565 QORIQ_CLK_PLL_DIV(2)>; 566 }; 567 568 gpio1: gpio@2300000 { 569 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 570 reg = <0x0 0x2300000 0x0 0x10000>; 571 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 572 gpio-controller; 573 #gpio-cells = <2>; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 little-endian; 577 }; 578 579 gpio2: gpio@2310000 { 580 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 581 reg = <0x0 0x2310000 0x0 0x10000>; 582 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 583 gpio-controller; 584 #gpio-cells = <2>; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 little-endian; 588 }; 589 590 gpio3: gpio@2320000 { 591 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 592 reg = <0x0 0x2320000 0x0 0x10000>; 593 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 594 gpio-controller; 595 #gpio-cells = <2>; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 little-endian; 599 }; 600 601 usb0: usb@3100000 { 602 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 603 reg = <0x0 0x3100000 0x0 0x10000>; 604 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 605 snps,dis_rxdet_inp3_quirk; 606 snps,quirk-frame-length-adjustment = <0x20>; 607 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 608 status = "disabled"; 609 }; 610 611 usb1: usb@3110000 { 612 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 613 reg = <0x0 0x3110000 0x0 0x10000>; 614 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 615 snps,dis_rxdet_inp3_quirk; 616 snps,quirk-frame-length-adjustment = <0x20>; 617 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 618 status = "disabled"; 619 }; 620 621 sata: sata@3200000 { 622 compatible = "fsl,ls1028a-ahci"; 623 reg = <0x0 0x3200000 0x0 0x10000>, 624 <0x7 0x100520 0x0 0x4>; 625 reg-names = "ahci", "sata-ecc"; 626 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 628 QORIQ_CLK_PLL_DIV(2)>; 629 status = "disabled"; 630 }; 631 632 pcie1: pcie@3400000 { 633 compatible = "fsl,ls1028a-pcie"; 634 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 635 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 636 reg-names = "regs", "config"; 637 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 638 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 639 interrupt-names = "pme", "aer"; 640 #address-cells = <3>; 641 #size-cells = <2>; 642 device_type = "pci"; 643 dma-coherent; 644 num-viewport = <8>; 645 bus-range = <0x0 0xff>; 646 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 647 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 648 msi-parent = <&its>; 649 #interrupt-cells = <1>; 650 interrupt-map-mask = <0 0 0 7>; 651 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 652 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 653 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 654 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 655 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 656 status = "disabled"; 657 }; 658 659 pcie_ep1: pcie-ep@3400000 { 660 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 661 reg = <0x00 0x03400000 0x0 0x00100000 662 0x80 0x00000000 0x8 0x00000000>; 663 reg-names = "regs", "addr_space"; 664 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 665 interrupt-names = "pme"; 666 num-ib-windows = <6>; 667 num-ob-windows = <8>; 668 status = "disabled"; 669 }; 670 671 pcie2: pcie@3500000 { 672 compatible = "fsl,ls1028a-pcie"; 673 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 674 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 675 reg-names = "regs", "config"; 676 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 678 interrupt-names = "pme", "aer"; 679 #address-cells = <3>; 680 #size-cells = <2>; 681 device_type = "pci"; 682 dma-coherent; 683 num-viewport = <8>; 684 bus-range = <0x0 0xff>; 685 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 686 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 687 msi-parent = <&its>; 688 #interrupt-cells = <1>; 689 interrupt-map-mask = <0 0 0 7>; 690 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 691 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 692 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 693 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 694 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 695 status = "disabled"; 696 }; 697 698 pcie_ep2: pcie-ep@3500000 { 699 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 700 reg = <0x00 0x03500000 0x0 0x00100000 701 0x88 0x00000000 0x8 0x00000000>; 702 reg-names = "regs", "addr_space"; 703 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 704 interrupt-names = "pme"; 705 num-ib-windows = <6>; 706 num-ob-windows = <8>; 707 status = "disabled"; 708 }; 709 710 smmu: iommu@5000000 { 711 compatible = "arm,mmu-500"; 712 reg = <0 0x5000000 0 0x800000>; 713 #global-interrupts = <8>; 714 #iommu-cells = <1>; 715 stream-match-mask = <0x7c00>; 716 /* global secure fault */ 717 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 718 /* combined secure interrupt */ 719 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 720 /* global non-secure fault */ 721 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 722 /* combined non-secure interrupt */ 723 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 724 /* performance counter interrupts 0-7 */ 725 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 727 /* per context interrupt, 64 interrupts */ 728 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 760 }; 761 762 crypto: crypto@8000000 { 763 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 764 fsl,sec-era = <10>; 765 #address-cells = <1>; 766 #size-cells = <1>; 767 ranges = <0x0 0x00 0x8000000 0x100000>; 768 reg = <0x00 0x8000000 0x0 0x100000>; 769 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 770 dma-coherent; 771 772 sec_jr0: jr@10000 { 773 compatible = "fsl,sec-v5.0-job-ring", 774 "fsl,sec-v4.0-job-ring"; 775 reg = <0x10000 0x10000>; 776 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 777 }; 778 779 sec_jr1: jr@20000 { 780 compatible = "fsl,sec-v5.0-job-ring", 781 "fsl,sec-v4.0-job-ring"; 782 reg = <0x20000 0x10000>; 783 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 784 }; 785 786 sec_jr2: jr@30000 { 787 compatible = "fsl,sec-v5.0-job-ring", 788 "fsl,sec-v4.0-job-ring"; 789 reg = <0x30000 0x10000>; 790 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 791 }; 792 793 sec_jr3: jr@40000 { 794 compatible = "fsl,sec-v5.0-job-ring", 795 "fsl,sec-v4.0-job-ring"; 796 reg = <0x40000 0x10000>; 797 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 798 }; 799 }; 800 801 qdma: dma-controller@8380000 { 802 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 803 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 804 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 805 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 806 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 811 interrupt-names = "qdma-error", "qdma-queue0", 812 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 813 dma-channels = <8>; 814 block-number = <1>; 815 block-offset = <0x10000>; 816 fsl,dma-queues = <2>; 817 status-sizes = <64>; 818 queue-sizes = <64 64>; 819 }; 820 821 cluster1_core0_watchdog: watchdog@c000000 { 822 compatible = "arm,sp805", "arm,primecell"; 823 reg = <0x0 0xc000000 0x0 0x1000>; 824 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 825 QORIQ_CLK_PLL_DIV(16)>, 826 <&clockgen QORIQ_CLK_PLATFORM_PLL 827 QORIQ_CLK_PLL_DIV(16)>; 828 clock-names = "wdog_clk", "apb_pclk"; 829 }; 830 831 cluster1_core1_watchdog: watchdog@c010000 { 832 compatible = "arm,sp805", "arm,primecell"; 833 reg = <0x0 0xc010000 0x0 0x1000>; 834 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 835 QORIQ_CLK_PLL_DIV(16)>, 836 <&clockgen QORIQ_CLK_PLATFORM_PLL 837 QORIQ_CLK_PLL_DIV(16)>; 838 clock-names = "wdog_clk", "apb_pclk"; 839 }; 840 841 malidp0: display@f080000 { 842 compatible = "arm,mali-dp500"; 843 reg = <0x0 0xf080000 0x0 0x10000>; 844 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 845 <0 223 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "DE", "SE"; 847 clocks = <&dpclk>, 848 <&clockgen QORIQ_CLK_HWACCEL 2>, 849 <&clockgen QORIQ_CLK_HWACCEL 2>, 850 <&clockgen QORIQ_CLK_HWACCEL 2>; 851 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 852 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 853 arm,malidp-arqos-value = <0xd000d000>; 854 855 port { 856 dpi0_out: endpoint { 857 858 }; 859 }; 860 }; 861 862 gpu: gpu@f0c0000 { 863 compatible = "vivante,gc"; 864 reg = <0x0 0xf0c0000 0x0 0x10000>; 865 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 867 <&clockgen QORIQ_CLK_HWACCEL 2>, 868 <&clockgen QORIQ_CLK_HWACCEL 2>; 869 clock-names = "core", "shader", "bus"; 870 #cooling-cells = <2>; 871 }; 872 873 sai1: audio-controller@f100000 { 874 #sound-dai-cells = <0>; 875 compatible = "fsl,vf610-sai"; 876 reg = <0x0 0xf100000 0x0 0x10000>; 877 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 879 QORIQ_CLK_PLL_DIV(2)>, 880 <&clockgen QORIQ_CLK_PLATFORM_PLL 881 QORIQ_CLK_PLL_DIV(2)>, 882 <&clockgen QORIQ_CLK_PLATFORM_PLL 883 QORIQ_CLK_PLL_DIV(2)>, 884 <&clockgen QORIQ_CLK_PLATFORM_PLL 885 QORIQ_CLK_PLL_DIV(2)>; 886 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 887 dma-names = "tx", "rx"; 888 dmas = <&edma0 1 4>, 889 <&edma0 1 3>; 890 fsl,sai-asynchronous; 891 status = "disabled"; 892 }; 893 894 sai2: audio-controller@f110000 { 895 #sound-dai-cells = <0>; 896 compatible = "fsl,vf610-sai"; 897 reg = <0x0 0xf110000 0x0 0x10000>; 898 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 900 QORIQ_CLK_PLL_DIV(2)>, 901 <&clockgen QORIQ_CLK_PLATFORM_PLL 902 QORIQ_CLK_PLL_DIV(2)>, 903 <&clockgen QORIQ_CLK_PLATFORM_PLL 904 QORIQ_CLK_PLL_DIV(2)>, 905 <&clockgen QORIQ_CLK_PLATFORM_PLL 906 QORIQ_CLK_PLL_DIV(2)>; 907 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 908 dma-names = "tx", "rx"; 909 dmas = <&edma0 1 6>, 910 <&edma0 1 5>; 911 fsl,sai-asynchronous; 912 status = "disabled"; 913 }; 914 915 sai3: audio-controller@f120000 { 916 #sound-dai-cells = <0>; 917 compatible = "fsl,vf610-sai"; 918 reg = <0x0 0xf120000 0x0 0x10000>; 919 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 921 QORIQ_CLK_PLL_DIV(2)>, 922 <&clockgen QORIQ_CLK_PLATFORM_PLL 923 QORIQ_CLK_PLL_DIV(2)>, 924 <&clockgen QORIQ_CLK_PLATFORM_PLL 925 QORIQ_CLK_PLL_DIV(2)>, 926 <&clockgen QORIQ_CLK_PLATFORM_PLL 927 QORIQ_CLK_PLL_DIV(2)>; 928 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 929 dma-names = "tx", "rx"; 930 dmas = <&edma0 1 8>, 931 <&edma0 1 7>; 932 fsl,sai-asynchronous; 933 status = "disabled"; 934 }; 935 936 sai4: audio-controller@f130000 { 937 #sound-dai-cells = <0>; 938 compatible = "fsl,vf610-sai"; 939 reg = <0x0 0xf130000 0x0 0x10000>; 940 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 942 QORIQ_CLK_PLL_DIV(2)>, 943 <&clockgen QORIQ_CLK_PLATFORM_PLL 944 QORIQ_CLK_PLL_DIV(2)>, 945 <&clockgen QORIQ_CLK_PLATFORM_PLL 946 QORIQ_CLK_PLL_DIV(2)>, 947 <&clockgen QORIQ_CLK_PLATFORM_PLL 948 QORIQ_CLK_PLL_DIV(2)>; 949 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 950 dma-names = "tx", "rx"; 951 dmas = <&edma0 1 10>, 952 <&edma0 1 9>; 953 fsl,sai-asynchronous; 954 status = "disabled"; 955 }; 956 957 sai5: audio-controller@f140000 { 958 #sound-dai-cells = <0>; 959 compatible = "fsl,vf610-sai"; 960 reg = <0x0 0xf140000 0x0 0x10000>; 961 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 963 QORIQ_CLK_PLL_DIV(2)>, 964 <&clockgen QORIQ_CLK_PLATFORM_PLL 965 QORIQ_CLK_PLL_DIV(2)>, 966 <&clockgen QORIQ_CLK_PLATFORM_PLL 967 QORIQ_CLK_PLL_DIV(2)>, 968 <&clockgen QORIQ_CLK_PLATFORM_PLL 969 QORIQ_CLK_PLL_DIV(2)>; 970 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 971 dma-names = "tx", "rx"; 972 dmas = <&edma0 1 12>, 973 <&edma0 1 11>; 974 fsl,sai-asynchronous; 975 status = "disabled"; 976 }; 977 978 sai6: audio-controller@f150000 { 979 #sound-dai-cells = <0>; 980 compatible = "fsl,vf610-sai"; 981 reg = <0x0 0xf150000 0x0 0x10000>; 982 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 984 QORIQ_CLK_PLL_DIV(2)>, 985 <&clockgen QORIQ_CLK_PLATFORM_PLL 986 QORIQ_CLK_PLL_DIV(2)>, 987 <&clockgen QORIQ_CLK_PLATFORM_PLL 988 QORIQ_CLK_PLL_DIV(2)>, 989 <&clockgen QORIQ_CLK_PLATFORM_PLL 990 QORIQ_CLK_PLL_DIV(2)>; 991 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 992 dma-names = "tx", "rx"; 993 dmas = <&edma0 1 14>, 994 <&edma0 1 13>; 995 fsl,sai-asynchronous; 996 status = "disabled"; 997 }; 998 999 dpclk: clock-controller@f1f0000 { 1000 compatible = "fsl,ls1028a-plldig"; 1001 reg = <0x0 0xf1f0000 0x0 0x10000>; 1002 #clock-cells = <0>; 1003 clocks = <&osc_27m>; 1004 }; 1005 1006 tmu: tmu@1f80000 { 1007 compatible = "fsl,qoriq-tmu"; 1008 reg = <0x0 0x1f80000 0x0 0x10000>; 1009 interrupts = <0 23 0x4>; 1010 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 1011 fsl,tmu-calibration = <0x00000000 0x00000024 1012 0x00000001 0x0000002b 1013 0x00000002 0x00000031 1014 0x00000003 0x00000038 1015 0x00000004 0x0000003f 1016 0x00000005 0x00000045 1017 0x00000006 0x0000004c 1018 0x00000007 0x00000053 1019 0x00000008 0x00000059 1020 0x00000009 0x00000060 1021 0x0000000a 0x00000066 1022 0x0000000b 0x0000006d 1023 1024 0x00010000 0x0000001c 1025 0x00010001 0x00000024 1026 0x00010002 0x0000002c 1027 0x00010003 0x00000035 1028 0x00010004 0x0000003d 1029 0x00010005 0x00000045 1030 0x00010006 0x0000004d 1031 0x00010007 0x00000055 1032 0x00010008 0x0000005e 1033 0x00010009 0x00000066 1034 0x0001000a 0x0000006e 1035 1036 0x00020000 0x00000018 1037 0x00020001 0x00000022 1038 0x00020002 0x0000002d 1039 0x00020003 0x00000038 1040 0x00020004 0x00000043 1041 0x00020005 0x0000004d 1042 0x00020006 0x00000058 1043 0x00020007 0x00000063 1044 0x00020008 0x0000006e 1045 1046 0x00030000 0x00000010 1047 0x00030001 0x0000001c 1048 0x00030002 0x00000029 1049 0x00030003 0x00000036 1050 0x00030004 0x00000042 1051 0x00030005 0x0000004f 1052 0x00030006 0x0000005b 1053 0x00030007 0x00000068>; 1054 little-endian; 1055 #thermal-sensor-cells = <1>; 1056 }; 1057 1058 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 1059 compatible = "pci-host-ecam-generic"; 1060 reg = <0x01 0xf0000000 0x0 0x100000>; 1061 #address-cells = <3>; 1062 #size-cells = <2>; 1063 msi-parent = <&its>; 1064 device_type = "pci"; 1065 bus-range = <0x0 0x0>; 1066 dma-coherent; 1067 msi-map = <0 &its 0x17 0xe>; 1068 iommu-map = <0 &smmu 0x17 0xe>; 1069 /* PF0-6 BAR0 - non-prefetchable memory */ 1070 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 1071 /* PF0-6 BAR2 - prefetchable memory */ 1072 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 1073 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 1074 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 1075 /* PF0: VF0-1 BAR2 - prefetchable memory */ 1076 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 1077 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 1078 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 1079 /* PF1: VF0-1 BAR2 - prefetchable memory */ 1080 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1081 /* BAR4 (PF5) - non-prefetchable memory */ 1082 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 1083 1084 enetc_port0: ethernet@0,0 { 1085 compatible = "fsl,enetc"; 1086 reg = <0x000000 0 0 0 0>; 1087 status = "disabled"; 1088 }; 1089 1090 enetc_port1: ethernet@0,1 { 1091 compatible = "fsl,enetc"; 1092 reg = <0x000100 0 0 0 0>; 1093 status = "disabled"; 1094 }; 1095 1096 enetc_port2: ethernet@0,2 { 1097 compatible = "fsl,enetc"; 1098 reg = <0x000200 0 0 0 0>; 1099 phy-mode = "internal"; 1100 status = "disabled"; 1101 1102 fixed-link { 1103 speed = <2500>; 1104 full-duplex; 1105 pause; 1106 }; 1107 }; 1108 1109 enetc_mdio_pf3: mdio@0,3 { 1110 compatible = "fsl,enetc-mdio"; 1111 reg = <0x000300 0 0 0 0>; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 }; 1115 1116 ethernet@0,4 { 1117 compatible = "fsl,enetc-ptp"; 1118 reg = <0x000400 0 0 0 0>; 1119 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 1120 little-endian; 1121 fsl,extts-fifo; 1122 }; 1123 1124 mscc_felix: ethernet-switch@0,5 { 1125 reg = <0x000500 0 0 0 0>; 1126 /* IEP INT_B */ 1127 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1128 status = "disabled"; 1129 1130 mscc_felix_ports: ports { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 1134 /* External ports */ 1135 mscc_felix_port0: port@0 { 1136 reg = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 mscc_felix_port1: port@1 { 1141 reg = <1>; 1142 status = "disabled"; 1143 }; 1144 1145 mscc_felix_port2: port@2 { 1146 reg = <2>; 1147 status = "disabled"; 1148 }; 1149 1150 mscc_felix_port3: port@3 { 1151 reg = <3>; 1152 status = "disabled"; 1153 }; 1154 1155 /* Internal ports */ 1156 mscc_felix_port4: port@4 { 1157 reg = <4>; 1158 phy-mode = "internal"; 1159 status = "disabled"; 1160 1161 fixed-link { 1162 speed = <2500>; 1163 full-duplex; 1164 pause; 1165 }; 1166 }; 1167 1168 mscc_felix_port5: port@5 { 1169 reg = <5>; 1170 phy-mode = "internal"; 1171 status = "disabled"; 1172 1173 fixed-link { 1174 speed = <1000>; 1175 full-duplex; 1176 pause; 1177 }; 1178 }; 1179 }; 1180 }; 1181 1182 enetc_port3: ethernet@0,6 { 1183 compatible = "fsl,enetc"; 1184 reg = <0x000600 0 0 0 0>; 1185 phy-mode = "internal"; 1186 status = "disabled"; 1187 1188 fixed-link { 1189 speed = <1000>; 1190 full-duplex; 1191 pause; 1192 }; 1193 }; 1194 1195 rcec@1f,0 { 1196 reg = <0x00f800 0 0 0 0>; 1197 /* IEP INT_A */ 1198 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1199 }; 1200 }; 1201 1202 /* Integrated Endpoint Register Block */ 1203 ierb@1f0800000 { 1204 compatible = "fsl,ls1028a-enetc-ierb"; 1205 reg = <0x01 0xf0800000 0x0 0x10000>; 1206 }; 1207 1208 pwm0: pwm@2800000 { 1209 compatible = "fsl,vf610-ftm-pwm"; 1210 #pwm-cells = <3>; 1211 reg = <0x0 0x2800000 0x0 0x10000>; 1212 clock-names = "ftm_sys", "ftm_ext", 1213 "ftm_fix", "ftm_cnt_clk_en"; 1214 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1215 <&rtc_clk>, <&clockgen 4 1>; 1216 status = "disabled"; 1217 }; 1218 1219 pwm1: pwm@2810000 { 1220 compatible = "fsl,vf610-ftm-pwm"; 1221 #pwm-cells = <3>; 1222 reg = <0x0 0x2810000 0x0 0x10000>; 1223 clock-names = "ftm_sys", "ftm_ext", 1224 "ftm_fix", "ftm_cnt_clk_en"; 1225 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1226 <&rtc_clk>, <&clockgen 4 1>; 1227 status = "disabled"; 1228 }; 1229 1230 pwm2: pwm@2820000 { 1231 compatible = "fsl,vf610-ftm-pwm"; 1232 #pwm-cells = <3>; 1233 reg = <0x0 0x2820000 0x0 0x10000>; 1234 clock-names = "ftm_sys", "ftm_ext", 1235 "ftm_fix", "ftm_cnt_clk_en"; 1236 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1237 <&rtc_clk>, <&clockgen 4 1>; 1238 status = "disabled"; 1239 }; 1240 1241 pwm3: pwm@2830000 { 1242 compatible = "fsl,vf610-ftm-pwm"; 1243 #pwm-cells = <3>; 1244 reg = <0x0 0x2830000 0x0 0x10000>; 1245 clock-names = "ftm_sys", "ftm_ext", 1246 "ftm_fix", "ftm_cnt_clk_en"; 1247 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1248 <&rtc_clk>, <&clockgen 4 1>; 1249 status = "disabled"; 1250 }; 1251 1252 pwm4: pwm@2840000 { 1253 compatible = "fsl,vf610-ftm-pwm"; 1254 #pwm-cells = <3>; 1255 reg = <0x0 0x2840000 0x0 0x10000>; 1256 clock-names = "ftm_sys", "ftm_ext", 1257 "ftm_fix", "ftm_cnt_clk_en"; 1258 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1259 <&rtc_clk>, <&clockgen 4 1>; 1260 status = "disabled"; 1261 }; 1262 1263 pwm5: pwm@2850000 { 1264 compatible = "fsl,vf610-ftm-pwm"; 1265 #pwm-cells = <3>; 1266 reg = <0x0 0x2850000 0x0 0x10000>; 1267 clock-names = "ftm_sys", "ftm_ext", 1268 "ftm_fix", "ftm_cnt_clk_en"; 1269 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1270 <&rtc_clk>, <&clockgen 4 1>; 1271 status = "disabled"; 1272 }; 1273 1274 pwm6: pwm@2860000 { 1275 compatible = "fsl,vf610-ftm-pwm"; 1276 #pwm-cells = <3>; 1277 reg = <0x0 0x2860000 0x0 0x10000>; 1278 clock-names = "ftm_sys", "ftm_ext", 1279 "ftm_fix", "ftm_cnt_clk_en"; 1280 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1281 <&rtc_clk>, <&clockgen 4 1>; 1282 status = "disabled"; 1283 }; 1284 1285 pwm7: pwm@2870000 { 1286 compatible = "fsl,vf610-ftm-pwm"; 1287 #pwm-cells = <3>; 1288 reg = <0x0 0x2870000 0x0 0x10000>; 1289 clock-names = "ftm_sys", "ftm_ext", 1290 "ftm_fix", "ftm_cnt_clk_en"; 1291 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1292 <&rtc_clk>, <&clockgen 4 1>; 1293 status = "disabled"; 1294 }; 1295 1296 rcpm: power-controller@1e34040 { 1297 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1298 reg = <0x0 0x1e34040 0x0 0x1c>; 1299 #fsl,rcpm-wakeup-cells = <7>; 1300 little-endian; 1301 }; 1302 1303 ftm_alarm0: timer@2800000 { 1304 compatible = "fsl,ls1028a-ftm-alarm"; 1305 reg = <0x0 0x2800000 0x0 0x10000>; 1306 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1307 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1308 status = "disabled"; 1309 }; 1310 1311 ftm_alarm1: timer@2810000 { 1312 compatible = "fsl,ls1028a-ftm-alarm"; 1313 reg = <0x0 0x2810000 0x0 0x10000>; 1314 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1315 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1316 status = "disabled"; 1317 }; 1318 }; 1319 1320}; 1321