1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for NXP LS1028A RDB Board.
4 *
5 * Copyright 2018 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
10
11/dts-v1/;
12#include "fsl-ls1028a.dtsi"
13
14/ {
15	model = "LS1028A RDB Board";
16	compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
17
18	aliases {
19		crypto = &crypto;
20		serial0 = &duart0;
21		serial1 = &duart1;
22		mmc0 = &esdhc;
23		mmc1 = &esdhc1;
24	};
25
26	chosen {
27		stdout-path = "serial0:115200n8";
28	};
29
30	memory@80000000 {
31		device_type = "memory";
32		reg = <0x0 0x80000000 0x1 0x0000000>;
33	};
34
35	sys_mclk: clock-mclk {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-frequency = <25000000>;
39	};
40
41	reg_1p8v: regulator-1p8v {
42		compatible = "regulator-fixed";
43		regulator-name = "1P8V";
44		regulator-min-microvolt = <1800000>;
45		regulator-max-microvolt = <1800000>;
46		regulator-always-on;
47	};
48
49	sb_3v3: regulator-sb3v3 {
50		compatible = "regulator-fixed";
51		regulator-name = "3v3_vbus";
52		regulator-min-microvolt = <3300000>;
53		regulator-max-microvolt = <3300000>;
54		regulator-boot-on;
55		regulator-always-on;
56	};
57
58	sound {
59		compatible = "simple-audio-card";
60		simple-audio-card,format = "i2s";
61		simple-audio-card,widgets =
62			"Microphone", "Microphone Jack",
63			"Headphone", "Headphone Jack",
64			"Speaker", "Speaker Ext",
65			"Line", "Line In Jack";
66		simple-audio-card,routing =
67			"MIC_IN", "Microphone Jack",
68			"Microphone Jack", "Mic Bias",
69			"LINE_IN", "Line In Jack",
70			"Headphone Jack", "HP_OUT",
71			"Speaker Ext", "LINE_OUT";
72
73		simple-audio-card,cpu {
74			sound-dai = <&sai4>;
75			frame-master;
76			bitclock-master;
77		};
78
79		simple-audio-card,codec {
80			sound-dai = <&sgtl5000>;
81			frame-master;
82			bitclock-master;
83			system-clock-frequency = <25000000>;
84		};
85	};
86};
87
88&can0 {
89	status = "okay";
90
91	can-transceiver {
92		max-bitrate = <5000000>;
93	};
94};
95
96&can1 {
97	status = "okay";
98
99	can-transceiver {
100		max-bitrate = <5000000>;
101	};
102};
103
104&esdhc {
105	sd-uhs-sdr104;
106	sd-uhs-sdr50;
107	sd-uhs-sdr25;
108	sd-uhs-sdr12;
109	status = "okay";
110};
111
112&esdhc1 {
113	mmc-hs200-1_8v;
114	mmc-hs400-1_8v;
115	bus-width = <8>;
116	status = "okay";
117};
118
119&fspi {
120	status = "okay";
121
122	mt35xu02g0: flash@0 {
123		compatible = "jedec,spi-nor";
124		#address-cells = <1>;
125		#size-cells = <1>;
126		spi-max-frequency = <50000000>;
127		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
128		spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
129		spi-tx-bus-width = <1>; /* 1 SPI Tx line */
130		reg = <0>;
131	};
132};
133
134&i2c0 {
135	status = "okay";
136
137	i2c-mux@77 {
138		compatible = "nxp,pca9847";
139		reg = <0x77>;
140		#address-cells = <1>;
141		#size-cells = <0>;
142
143		i2c@1 {
144			#address-cells = <1>;
145			#size-cells = <0>;
146			reg = <0x1>;
147
148			sgtl5000: audio-codec@a {
149				#sound-dai-cells = <0>;
150				compatible = "fsl,sgtl5000";
151				reg = <0xa>;
152				VDDA-supply = <&reg_1p8v>;
153				VDDIO-supply = <&reg_1p8v>;
154				clocks = <&sys_mclk>;
155				sclk-strength = <3>;
156			};
157		};
158
159		i2c@2 {
160			#address-cells = <1>;
161			#size-cells = <0>;
162			reg = <0x02>;
163
164			current-monitor@40 {
165				compatible = "ti,ina220";
166				reg = <0x40>;
167				shunt-resistor = <500>;
168			};
169		};
170
171		i2c@3 {
172			#address-cells = <1>;
173			#size-cells = <0>;
174			reg = <0x3>;
175
176			temperature-sensor@4c {
177				compatible = "nxp,sa56004";
178				reg = <0x4c>;
179				vcc-supply = <&sb_3v3>;
180			};
181
182			rtc@51 {
183				compatible = "nxp,pcf2129";
184				reg = <0x51>;
185			};
186		};
187	};
188};
189
190&duart0 {
191	status = "okay";
192};
193
194&duart1 {
195	status = "okay";
196};
197
198&enetc_mdio_pf3 {
199	/* VSC8514 QSGMII quad PHY */
200	qsgmii_phy0: ethernet-phy@10 {
201		reg = <0x10>;
202	};
203
204	qsgmii_phy1: ethernet-phy@11 {
205		reg = <0x11>;
206	};
207
208	qsgmii_phy2: ethernet-phy@12 {
209		reg = <0x12>;
210	};
211
212	qsgmii_phy3: ethernet-phy@13 {
213		reg = <0x13>;
214	};
215};
216
217&enetc_port0 {
218	phy-handle = <&sgmii_phy0>;
219	phy-connection-type = "sgmii";
220	managed = "in-band-status";
221	status = "okay";
222
223	mdio {
224		#address-cells = <1>;
225		#size-cells = <0>;
226		sgmii_phy0: ethernet-phy@2 {
227			reg = <0x2>;
228		};
229	};
230};
231
232&enetc_port2 {
233	status = "okay";
234};
235
236&mscc_felix {
237	status = "okay";
238};
239
240&mscc_felix_port0 {
241	label = "swp0";
242	managed = "in-band-status";
243	phy-handle = <&qsgmii_phy0>;
244	phy-mode = "qsgmii";
245	status = "okay";
246};
247
248&mscc_felix_port1 {
249	label = "swp1";
250	managed = "in-band-status";
251	phy-handle = <&qsgmii_phy1>;
252	phy-mode = "qsgmii";
253	status = "okay";
254};
255
256&mscc_felix_port2 {
257	label = "swp2";
258	managed = "in-band-status";
259	phy-handle = <&qsgmii_phy2>;
260	phy-mode = "qsgmii";
261	status = "okay";
262};
263
264&mscc_felix_port3 {
265	label = "swp3";
266	managed = "in-band-status";
267	phy-handle = <&qsgmii_phy3>;
268	phy-mode = "qsgmii";
269	status = "okay";
270};
271
272&mscc_felix_port4 {
273	ethernet = <&enetc_port2>;
274	status = "okay";
275};
276
277&sai4 {
278	status = "okay";
279};
280
281&sata {
282	status = "okay";
283};
284
285&usb1 {
286	dr_mode = "otg";
287};
288