1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for NXP LS1028A RDB Board.
4 *
5 * Copyright 2018 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
10
11/dts-v1/;
12#include "fsl-ls1028a.dtsi"
13
14/ {
15	model = "LS1028A RDB Board";
16	compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
17
18	aliases {
19		crypto = &crypto;
20		serial0 = &duart0;
21		serial1 = &duart1;
22		mmc0 = &esdhc;
23		mmc1 = &esdhc1;
24	};
25
26	chosen {
27		stdout-path = "serial0:115200n8";
28	};
29
30	memory@80000000 {
31		device_type = "memory";
32		reg = <0x0 0x80000000 0x1 0x0000000>;
33	};
34
35	sys_mclk: clock-mclk {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-frequency = <25000000>;
39	};
40
41	reg_1p8v: regulator-1p8v {
42		compatible = "regulator-fixed";
43		regulator-name = "1P8V";
44		regulator-min-microvolt = <1800000>;
45		regulator-max-microvolt = <1800000>;
46		regulator-always-on;
47	};
48
49	sb_3v3: regulator-sb3v3 {
50		compatible = "regulator-fixed";
51		regulator-name = "3v3_vbus";
52		regulator-min-microvolt = <3300000>;
53		regulator-max-microvolt = <3300000>;
54		regulator-boot-on;
55		regulator-always-on;
56	};
57
58	sound {
59		compatible = "simple-audio-card";
60		simple-audio-card,format = "i2s";
61		simple-audio-card,widgets =
62			"Microphone", "Microphone Jack",
63			"Headphone", "Headphone Jack",
64			"Speaker", "Speaker Ext",
65			"Line", "Line In Jack";
66		simple-audio-card,routing =
67			"MIC_IN", "Microphone Jack",
68			"Microphone Jack", "Mic Bias",
69			"LINE_IN", "Line In Jack",
70			"Headphone Jack", "HP_OUT",
71			"Speaker Ext", "LINE_OUT";
72
73		simple-audio-card,cpu {
74			sound-dai = <&sai4>;
75			frame-master;
76			bitclock-master;
77		};
78
79		simple-audio-card,codec {
80			sound-dai = <&sgtl5000>;
81			frame-master;
82			bitclock-master;
83			system-clock-frequency = <25000000>;
84		};
85	};
86};
87
88&esdhc {
89	sd-uhs-sdr104;
90	sd-uhs-sdr50;
91	sd-uhs-sdr25;
92	sd-uhs-sdr12;
93	status = "okay";
94};
95
96&esdhc1 {
97	mmc-hs200-1_8v;
98	mmc-hs400-1_8v;
99	bus-width = <8>;
100	status = "okay";
101};
102
103&fspi {
104	status = "okay";
105
106	mt35xu02g0: flash@0 {
107		compatible = "jedec,spi-nor";
108		#address-cells = <1>;
109		#size-cells = <1>;
110		spi-max-frequency = <50000000>;
111		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
112		spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
113		spi-tx-bus-width = <1>; /* 1 SPI Tx line */
114		reg = <0>;
115	};
116};
117
118&i2c0 {
119	status = "okay";
120
121	i2c-mux@77 {
122		compatible = "nxp,pca9847";
123		reg = <0x77>;
124		#address-cells = <1>;
125		#size-cells = <0>;
126
127		i2c@1 {
128			#address-cells = <1>;
129			#size-cells = <0>;
130			reg = <0x1>;
131
132			sgtl5000: audio-codec@a {
133				#sound-dai-cells = <0>;
134				compatible = "fsl,sgtl5000";
135				reg = <0xa>;
136				VDDA-supply = <&reg_1p8v>;
137				VDDIO-supply = <&reg_1p8v>;
138				clocks = <&sys_mclk>;
139				sclk-strength = <3>;
140			};
141		};
142
143		i2c@2 {
144			#address-cells = <1>;
145			#size-cells = <0>;
146			reg = <0x02>;
147
148			current-monitor@40 {
149				compatible = "ti,ina220";
150				reg = <0x40>;
151				shunt-resistor = <500>;
152			};
153		};
154
155		i2c@3 {
156			#address-cells = <1>;
157			#size-cells = <0>;
158			reg = <0x3>;
159
160			temperature-sensor@4c {
161				compatible = "nxp,sa56004";
162				reg = <0x4c>;
163				vcc-supply = <&sb_3v3>;
164			};
165
166			rtc@51 {
167				compatible = "nxp,pcf2129";
168				reg = <0x51>;
169			};
170		};
171	};
172};
173
174&duart0 {
175	status = "okay";
176};
177
178&duart1 {
179	status = "okay";
180};
181
182&enetc_mdio_pf3 {
183	/* VSC8514 QSGMII quad PHY */
184	qsgmii_phy0: ethernet-phy@10 {
185		reg = <0x10>;
186	};
187
188	qsgmii_phy1: ethernet-phy@11 {
189		reg = <0x11>;
190	};
191
192	qsgmii_phy2: ethernet-phy@12 {
193		reg = <0x12>;
194	};
195
196	qsgmii_phy3: ethernet-phy@13 {
197		reg = <0x13>;
198	};
199};
200
201&enetc_port0 {
202	phy-handle = <&sgmii_phy0>;
203	phy-connection-type = "sgmii";
204	managed = "in-band-status";
205	status = "okay";
206
207	mdio {
208		#address-cells = <1>;
209		#size-cells = <0>;
210		sgmii_phy0: ethernet-phy@2 {
211			reg = <0x2>;
212		};
213	};
214};
215
216&enetc_port2 {
217	status = "okay";
218};
219
220&mscc_felix {
221	status = "okay";
222};
223
224&mscc_felix_port0 {
225	label = "swp0";
226	managed = "in-band-status";
227	phy-handle = <&qsgmii_phy0>;
228	phy-mode = "qsgmii";
229	status = "okay";
230};
231
232&mscc_felix_port1 {
233	label = "swp1";
234	managed = "in-band-status";
235	phy-handle = <&qsgmii_phy1>;
236	phy-mode = "qsgmii";
237	status = "okay";
238};
239
240&mscc_felix_port2 {
241	label = "swp2";
242	managed = "in-band-status";
243	phy-handle = <&qsgmii_phy2>;
244	phy-mode = "qsgmii";
245	status = "okay";
246};
247
248&mscc_felix_port3 {
249	label = "swp3";
250	managed = "in-band-status";
251	phy-handle = <&qsgmii_phy3>;
252	phy-mode = "qsgmii";
253	status = "okay";
254};
255
256&mscc_felix_port4 {
257	ethernet = <&enetc_port2>;
258	status = "okay";
259};
260
261&sai4 {
262	status = "okay";
263};
264
265&sata {
266	status = "okay";
267};
268
269&usb1 {
270	dr_mode = "otg";
271};
272