1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for NXP LS1028A QDS Board.
4 *
5 * Copyright 2018 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
10
11/dts-v1/;
12
13#include "fsl-ls1028a.dtsi"
14
15/ {
16	model = "LS1028A QDS Board";
17	compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
18
19	aliases {
20		crypto = &crypto;
21		gpio0 = &gpio1;
22		gpio1 = &gpio2;
23		gpio2 = &gpio3;
24		serial0 = &duart0;
25		serial1 = &duart1;
26	};
27
28	chosen {
29		stdout-path = "serial0:115200n8";
30	};
31
32	memory@80000000 {
33		device_type = "memory";
34		reg = <0x0 0x80000000 0x1 0x00000000>;
35	};
36
37	sys_mclk: clock-mclk {
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		clock-frequency = <25000000>;
41	};
42
43	reg_1p8v: regulator-1p8v {
44		compatible = "regulator-fixed";
45		regulator-name = "1P8V";
46		regulator-min-microvolt = <1800000>;
47		regulator-max-microvolt = <1800000>;
48		regulator-always-on;
49	};
50
51	sb_3v3: regulator-sb3v3 {
52		compatible = "regulator-fixed";
53		regulator-name = "3v3_vbus";
54		regulator-min-microvolt = <3300000>;
55		regulator-max-microvolt = <3300000>;
56		regulator-boot-on;
57		regulator-always-on;
58	};
59
60	sound {
61		compatible = "simple-audio-card";
62		simple-audio-card,format = "i2s";
63		simple-audio-card,widgets =
64			"Microphone", "Microphone Jack",
65			"Headphone", "Headphone Jack",
66			"Speaker", "Speaker Ext",
67			"Line", "Line In Jack";
68		simple-audio-card,routing =
69			"MIC_IN", "Microphone Jack",
70			"Microphone Jack", "Mic Bias",
71			"LINE_IN", "Line In Jack",
72			"Headphone Jack", "HP_OUT",
73			"Speaker Ext", "LINE_OUT";
74
75		simple-audio-card,cpu {
76			sound-dai = <&sai1>;
77			frame-master;
78			bitclock-master;
79		};
80
81		simple-audio-card,codec {
82			sound-dai = <&sgtl5000>;
83			frame-master;
84			bitclock-master;
85			system-clock-frequency = <25000000>;
86		};
87	};
88
89	mdio-mux {
90		compatible = "mdio-mux-multiplexer";
91		mux-controls = <&mux 0>;
92		mdio-parent-bus = <&enetc_mdio_pf3>;
93		#address-cells=<1>;
94		#size-cells = <0>;
95
96		/* on-board RGMII PHY */
97		mdio@0 {
98			#address-cells = <1>;
99			#size-cells = <0>;
100			reg = <0>;
101
102			qds_phy1: ethernet-phy@5 {
103				/* Atheros 8035 */
104				reg = <5>;
105			};
106		};
107	};
108};
109
110&duart0 {
111	status = "okay";
112};
113
114&duart1 {
115	status = "okay";
116};
117
118&esdhc {
119	status = "okay";
120};
121
122&esdhc1 {
123	status = "okay";
124};
125
126&i2c0 {
127	status = "okay";
128
129	i2c-mux@77 {
130		compatible = "nxp,pca9847";
131		reg = <0x77>;
132		#address-cells = <1>;
133		#size-cells = <0>;
134
135		i2c@2 {
136			#address-cells = <1>;
137			#size-cells = <0>;
138			reg = <0x2>;
139
140			current-monitor@40 {
141				compatible = "ti,ina220";
142				reg = <0x40>;
143				shunt-resistor = <1000>;
144			};
145
146			current-monitor@41 {
147				compatible = "ti,ina220";
148				reg = <0x41>;
149				shunt-resistor = <1000>;
150			};
151		};
152
153		i2c@3 {
154			#address-cells = <1>;
155			#size-cells = <0>;
156			reg = <0x3>;
157
158			temperature-sensor@4c {
159				compatible = "nxp,sa56004";
160				reg = <0x4c>;
161				vcc-supply = <&sb_3v3>;
162			};
163
164			rtc@51 {
165				compatible = "nxp,pcf2129";
166				reg = <0x51>;
167			};
168
169			eeprom@56 {
170				compatible = "atmel,24c512";
171				reg = <0x56>;
172			};
173
174			eeprom@57 {
175				compatible = "atmel,24c512";
176				reg = <0x57>;
177			};
178		};
179
180		i2c@5 {
181			#address-cells = <1>;
182			#size-cells = <0>;
183			reg = <0x5>;
184
185			sgtl5000: audio-codec@a {
186				#sound-dai-cells = <0>;
187				compatible = "fsl,sgtl5000";
188				reg = <0xa>;
189				VDDA-supply = <&reg_1p8v>;
190				VDDIO-supply = <&reg_1p8v>;
191				clocks = <&sys_mclk>;
192			};
193		};
194	};
195
196	fpga@66 {
197		#address-cells = <1>;
198		#size-cells = <0>;
199		compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
200			     "simple-mfd";
201		reg = <0x66>;
202
203		mux: mux-controller {
204			compatible = "reg-mux";
205			#mux-control-cells = <1>;
206			mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
207		};
208	};
209
210};
211
212&enetc_port1 {
213	phy-handle = <&qds_phy1>;
214	phy-connection-type = "rgmii-id";
215};
216
217&sai1 {
218	status = "okay";
219};
220
221&sata {
222	status = "okay";
223};
224