1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for NXP LS1028A QDS Board.
4 *
5 * Copyright 2018 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
10
11/dts-v1/;
12
13#include "fsl-ls1028a.dtsi"
14
15/ {
16	model = "LS1028A QDS Board";
17	compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
18
19	aliases {
20		crypto = &crypto;
21		gpio0 = &gpio1;
22		gpio1 = &gpio2;
23		gpio2 = &gpio3;
24		serial0 = &duart0;
25		serial1 = &duart1;
26		mmc0 = &esdhc;
27		mmc1 = &esdhc1;
28	};
29
30	chosen {
31		stdout-path = "serial0:115200n8";
32	};
33
34	memory@80000000 {
35		device_type = "memory";
36		reg = <0x0 0x80000000 0x1 0x00000000>;
37	};
38
39	sys_mclk: clock-mclk {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <25000000>;
43	};
44
45	reg_1p8v: regulator-1p8v {
46		compatible = "regulator-fixed";
47		regulator-name = "1P8V";
48		regulator-min-microvolt = <1800000>;
49		regulator-max-microvolt = <1800000>;
50		regulator-always-on;
51	};
52
53	sb_3v3: regulator-sb3v3 {
54		compatible = "regulator-fixed";
55		regulator-name = "3v3_vbus";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-boot-on;
59		regulator-always-on;
60	};
61
62	sound {
63		compatible = "simple-audio-card";
64		simple-audio-card,format = "i2s";
65		simple-audio-card,widgets =
66			"Microphone", "Microphone Jack",
67			"Headphone", "Headphone Jack",
68			"Speaker", "Speaker Ext",
69			"Line", "Line In Jack";
70		simple-audio-card,routing =
71			"MIC_IN", "Microphone Jack",
72			"Microphone Jack", "Mic Bias",
73			"LINE_IN", "Line In Jack",
74			"Headphone Jack", "HP_OUT",
75			"Speaker Ext", "LINE_OUT";
76
77		simple-audio-card,cpu {
78			sound-dai = <&sai1>;
79			frame-master;
80			bitclock-master;
81		};
82
83		simple-audio-card,codec {
84			sound-dai = <&sgtl5000>;
85			frame-master;
86			bitclock-master;
87			system-clock-frequency = <25000000>;
88		};
89	};
90
91	mdio-mux {
92		compatible = "mdio-mux-multiplexer";
93		mux-controls = <&mux 0>;
94		mdio-parent-bus = <&enetc_mdio_pf3>;
95		#address-cells=<1>;
96		#size-cells = <0>;
97
98		/* on-board RGMII PHY */
99		mdio@0 {
100			#address-cells = <1>;
101			#size-cells = <0>;
102			reg = <0>;
103
104			qds_phy1: ethernet-phy@5 {
105				/* Atheros 8035 */
106				reg = <5>;
107			};
108		};
109	};
110};
111
112&can0 {
113	status = "okay";
114};
115
116&can1 {
117	status = "okay";
118};
119
120&dspi0 {
121	bus-num = <0>;
122	status = "okay";
123
124	flash@0 {
125		#address-cells = <1>;
126		#size-cells = <1>;
127		compatible = "jedec,spi-nor";
128		spi-cpol;
129		spi-cpha;
130		reg = <0>;
131		spi-max-frequency = <10000000>;
132	};
133
134	flash@1 {
135		#address-cells = <1>;
136		#size-cells = <1>;
137		compatible = "jedec,spi-nor";
138		spi-cpol;
139		spi-cpha;
140		reg = <1>;
141		spi-max-frequency = <10000000>;
142	};
143
144	flash@2 {
145		#address-cells = <1>;
146		#size-cells = <1>;
147		compatible = "jedec,spi-nor";
148		spi-cpol;
149		spi-cpha;
150		reg = <2>;
151		spi-max-frequency = <10000000>;
152	};
153};
154
155&dspi1 {
156	bus-num = <1>;
157	status = "okay";
158
159	flash@0 {
160		#address-cells = <1>;
161		#size-cells = <1>;
162		compatible = "jedec,spi-nor";
163		spi-cpol;
164		spi-cpha;
165		reg = <0>;
166		spi-max-frequency = <10000000>;
167	};
168
169	flash@1 {
170		#address-cells = <1>;
171		#size-cells = <1>;
172		compatible = "jedec,spi-nor";
173		spi-cpol;
174		spi-cpha;
175		reg = <1>;
176		spi-max-frequency = <10000000>;
177	};
178
179	flash@2 {
180		#address-cells = <1>;
181		#size-cells = <1>;
182		compatible = "jedec,spi-nor";
183		spi-cpol;
184		spi-cpha;
185		reg = <2>;
186		spi-max-frequency = <10000000>;
187	};
188};
189
190&dspi2 {
191	bus-num = <2>;
192	status = "okay";
193
194	flash@0 {
195		#address-cells = <1>;
196		#size-cells = <1>;
197		compatible = "jedec,spi-nor";
198		spi-cpol;
199		spi-cpha;
200		reg = <0>;
201		spi-max-frequency = <10000000>;
202	};
203};
204
205&duart0 {
206	status = "okay";
207};
208
209&duart1 {
210	status = "okay";
211};
212
213&esdhc {
214	status = "okay";
215};
216
217&esdhc1 {
218	status = "okay";
219};
220
221&fspi {
222	status = "okay";
223
224	mt35xu02g0: flash@0 {
225		compatible = "jedec,spi-nor";
226		#address-cells = <1>;
227		#size-cells = <1>;
228		spi-max-frequency = <50000000>;
229		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
230		spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
231		spi-tx-bus-width = <1>; /* 1 SPI Tx line */
232		reg = <0>;
233	};
234};
235
236&i2c0 {
237	status = "okay";
238
239	i2c-mux@77 {
240		compatible = "nxp,pca9547";
241		reg = <0x77>;
242		#address-cells = <1>;
243		#size-cells = <0>;
244
245		i2c@2 {
246			#address-cells = <1>;
247			#size-cells = <0>;
248			reg = <0x2>;
249
250			current-monitor@40 {
251				compatible = "ti,ina220";
252				reg = <0x40>;
253				shunt-resistor = <1000>;
254			};
255
256			current-monitor@41 {
257				compatible = "ti,ina220";
258				reg = <0x41>;
259				shunt-resistor = <1000>;
260			};
261		};
262
263		i2c@3 {
264			#address-cells = <1>;
265			#size-cells = <0>;
266			reg = <0x3>;
267
268			temperature-sensor@4c {
269				compatible = "nxp,sa56004";
270				reg = <0x4c>;
271				vcc-supply = <&sb_3v3>;
272			};
273
274			rtc@51 {
275				compatible = "nxp,pcf2129";
276				reg = <0x51>;
277			};
278
279			eeprom@56 {
280				compatible = "atmel,24c512";
281				reg = <0x56>;
282			};
283
284			eeprom@57 {
285				compatible = "atmel,24c512";
286				reg = <0x57>;
287			};
288		};
289
290		i2c@5 {
291			#address-cells = <1>;
292			#size-cells = <0>;
293			reg = <0x5>;
294
295			sgtl5000: audio-codec@a {
296				#sound-dai-cells = <0>;
297				compatible = "fsl,sgtl5000";
298				reg = <0xa>;
299				VDDA-supply = <&reg_1p8v>;
300				VDDIO-supply = <&reg_1p8v>;
301				clocks = <&sys_mclk>;
302			};
303		};
304	};
305
306	fpga@66 {
307		compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
308			     "simple-mfd";
309		reg = <0x66>;
310
311		mux: mux-controller {
312			compatible = "reg-mux";
313			#mux-control-cells = <1>;
314			mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
315		};
316	};
317
318};
319
320&enetc_port1 {
321	phy-handle = <&qds_phy1>;
322	phy-connection-type = "rgmii-id";
323	status = "okay";
324};
325
326&lpuart0 {
327	status = "okay";
328};
329
330&sai1 {
331	status = "okay";
332};
333
334&sata {
335	status = "okay";
336};
337