1*4c33cb31SAndrew Davis// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4c33cb31SAndrew Davis/*
3*4c33cb31SAndrew Davis * Device Tree fragment for LS1028A QDS board, serdes 69xx
4*4c33cb31SAndrew Davis *
5*4c33cb31SAndrew Davis * Copyright 2019-2021 NXP
6*4c33cb31SAndrew Davis *
7*4c33cb31SAndrew Davis * Requires a LS1028A QDS board with lane B rework.
8*4c33cb31SAndrew Davis * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
9*4c33cb31SAndrew Davis */
10*4c33cb31SAndrew Davis
11*4c33cb31SAndrew Davis/dts-v1/;
12*4c33cb31SAndrew Davis/plugin/;
13*4c33cb31SAndrew Davis
14*4c33cb31SAndrew Davis&mdio_slot1 {
15*4c33cb31SAndrew Davis	#address-cells = <1>;
16*4c33cb31SAndrew Davis	#size-cells = <0>;
17*4c33cb31SAndrew Davis
18*4c33cb31SAndrew Davis	slot1_sgmii: ethernet-phy@2 {
19*4c33cb31SAndrew Davis		/* AQR112 */
20*4c33cb31SAndrew Davis		reg = <0x2>;
21*4c33cb31SAndrew Davis		compatible = "ethernet-phy-ieee802.3-c45";
22*4c33cb31SAndrew Davis	};
23*4c33cb31SAndrew Davis};
24*4c33cb31SAndrew Davis
25*4c33cb31SAndrew Davis&enetc_port0 {
26*4c33cb31SAndrew Davis	phy-handle = <&slot1_sgmii>;
27*4c33cb31SAndrew Davis	phy-mode = "2500base-x";
28*4c33cb31SAndrew Davis	status = "okay";
29*4c33cb31SAndrew Davis};
30*4c33cb31SAndrew Davis
31*4c33cb31SAndrew Davis&mdio_slot2 {
32*4c33cb31SAndrew Davis	#address-cells = <1>;
33*4c33cb31SAndrew Davis	#size-cells = <0>;
34*4c33cb31SAndrew Davis
35*4c33cb31SAndrew Davis	/* 4 ports on VSC8514 */
36*4c33cb31SAndrew Davis	slot2_qsgmii0: ethernet-phy@8 {
37*4c33cb31SAndrew Davis		reg = <0x8>;
38*4c33cb31SAndrew Davis	};
39*4c33cb31SAndrew Davis
40*4c33cb31SAndrew Davis	slot2_qsgmii1: ethernet-phy@9 {
41*4c33cb31SAndrew Davis		reg = <0x9>;
42*4c33cb31SAndrew Davis	};
43*4c33cb31SAndrew Davis
44*4c33cb31SAndrew Davis	slot2_qsgmii2: ethernet-phy@a {
45*4c33cb31SAndrew Davis		reg = <0xa>;
46*4c33cb31SAndrew Davis	};
47*4c33cb31SAndrew Davis
48*4c33cb31SAndrew Davis	slot2_qsgmii3: ethernet-phy@b {
49*4c33cb31SAndrew Davis		reg = <0xb>;
50*4c33cb31SAndrew Davis	};
51*4c33cb31SAndrew Davis};
52*4c33cb31SAndrew Davis
53*4c33cb31SAndrew Davis&mscc_felix_ports {
54*4c33cb31SAndrew Davis	port@0 {
55*4c33cb31SAndrew Davis		status = "okay";
56*4c33cb31SAndrew Davis		phy-handle = <&slot2_qsgmii0>;
57*4c33cb31SAndrew Davis		phy-mode = "qsgmii";
58*4c33cb31SAndrew Davis		managed = "in-band-status";
59*4c33cb31SAndrew Davis	};
60*4c33cb31SAndrew Davis
61*4c33cb31SAndrew Davis	port@1 {
62*4c33cb31SAndrew Davis		status = "okay";
63*4c33cb31SAndrew Davis		phy-handle = <&slot2_qsgmii1>;
64*4c33cb31SAndrew Davis		phy-mode = "qsgmii";
65*4c33cb31SAndrew Davis		managed = "in-band-status";
66*4c33cb31SAndrew Davis	};
67*4c33cb31SAndrew Davis
68*4c33cb31SAndrew Davis	port@2 {
69*4c33cb31SAndrew Davis		status = "okay";
70*4c33cb31SAndrew Davis		phy-handle = <&slot2_qsgmii2>;
71*4c33cb31SAndrew Davis		phy-mode = "qsgmii";
72*4c33cb31SAndrew Davis		managed = "in-band-status";
73*4c33cb31SAndrew Davis	};
74*4c33cb31SAndrew Davis
75*4c33cb31SAndrew Davis	port@3 {
76*4c33cb31SAndrew Davis		status = "okay";
77*4c33cb31SAndrew Davis		phy-handle = <&slot2_qsgmii3>;
78*4c33cb31SAndrew Davis		phy-mode = "qsgmii";
79*4c33cb31SAndrew Davis		managed = "in-band-status";
80*4c33cb31SAndrew Davis	};
81*4c33cb31SAndrew Davis};
82*4c33cb31SAndrew Davis
83*4c33cb31SAndrew Davis&mscc_felix {
84*4c33cb31SAndrew Davis	status = "okay";
85*4c33cb31SAndrew Davis};
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