1/*
2 * Device Tree Include file for Freescale Layerscape-1012A family SoC.
3 *
4 * Copyright 2016 Freescale Semiconductor, Inc.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPLv2 or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This library is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This library is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/thermal/thermal.h>
47
48/ {
49	compatible = "fsl,ls1012a";
50	interrupt-parent = <&gic>;
51	#address-cells = <2>;
52	#size-cells = <2>;
53
54	aliases {
55		crypto = &crypto;
56		rtic_a = &rtic_a;
57		rtic_b = &rtic_b;
58		rtic_c = &rtic_c;
59		rtic_d = &rtic_d;
60		sec_mon = &sec_mon;
61	};
62
63	cpus {
64		#address-cells = <1>;
65		#size-cells = <0>;
66
67		cpu0: cpu@0 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a53";
70			reg = <0x0>;
71			clocks = <&clockgen 1 0>;
72			#cooling-cells = <2>;
73		};
74	};
75
76	sysclk: sysclk {
77		compatible = "fixed-clock";
78		#clock-cells = <0>;
79		clock-frequency = <125000000>;
80		clock-output-names = "sysclk";
81	};
82
83	coreclk: coreclk {
84		compatible = "fixed-clock";
85		#clock-cells = <0>;
86		clock-frequency = <100000000>;
87		clock-output-names = "coreclk";
88	};
89
90	timer {
91		compatible = "arm,armv8-timer";
92		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
93			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
94			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
95			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
96	};
97
98	pmu {
99		compatible = "arm,armv8-pmuv3";
100		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
101	};
102
103	gic: interrupt-controller@1400000 {
104		compatible = "arm,gic-400";
105		#interrupt-cells = <3>;
106		interrupt-controller;
107		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
108		      <0x0 0x1402000 0 0x2000>, /* GICC */
109		      <0x0 0x1404000 0 0x2000>, /* GICH */
110		      <0x0 0x1406000 0 0x2000>; /* GICV */
111		interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
112	};
113
114	reboot {
115		compatible = "syscon-reboot";
116		regmap = <&dcfg>;
117		offset = <0xb0>;
118		mask = <0x02>;
119	};
120
121	soc {
122		compatible = "simple-bus";
123		#address-cells = <2>;
124		#size-cells = <2>;
125		ranges;
126
127		esdhc0: esdhc@1560000 {
128			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
129			reg = <0x0 0x1560000 0x0 0x10000>;
130			interrupts = <0 62 0x4>;
131			clocks = <&clockgen 4 0>;
132			voltage-ranges = <1800 1800 3300 3300>;
133			sdhci,auto-cmd12;
134			big-endian;
135			bus-width = <4>;
136			status = "disabled";
137		};
138
139		scfg: scfg@1570000 {
140			compatible = "fsl,ls1012a-scfg", "syscon";
141			reg = <0x0 0x1570000 0x0 0x10000>;
142			big-endian;
143		};
144
145		esdhc1: esdhc@1580000 {
146			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
147			reg = <0x0 0x1580000 0x0 0x10000>;
148			interrupts = <0 65 0x4>;
149			clocks = <&clockgen 4 0>;
150			voltage-ranges = <1800 1800 3300 3300>;
151			sdhci,auto-cmd12;
152			big-endian;
153			broken-cd;
154			bus-width = <4>;
155			status = "disabled";
156		};
157
158		crypto: crypto@1700000 {
159			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
160				     "fsl,sec-v4.0";
161			fsl,sec-era = <8>;
162			#address-cells = <1>;
163			#size-cells = <1>;
164			ranges = <0x0 0x00 0x1700000 0x100000>;
165			reg = <0x00 0x1700000 0x0 0x100000>;
166			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
167
168			sec_jr0: jr@10000 {
169				compatible = "fsl,sec-v5.4-job-ring",
170					     "fsl,sec-v5.0-job-ring",
171					     "fsl,sec-v4.0-job-ring";
172				reg	   = <0x10000 0x10000>;
173				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
174			};
175
176			sec_jr1: jr@20000 {
177				compatible = "fsl,sec-v5.4-job-ring",
178					     "fsl,sec-v5.0-job-ring",
179					     "fsl,sec-v4.0-job-ring";
180				reg	   = <0x20000 0x10000>;
181				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
182			};
183
184			sec_jr2: jr@30000 {
185				compatible = "fsl,sec-v5.4-job-ring",
186					     "fsl,sec-v5.0-job-ring",
187					     "fsl,sec-v4.0-job-ring";
188				reg	   = <0x30000 0x10000>;
189				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
190			};
191
192			sec_jr3: jr@40000 {
193				compatible = "fsl,sec-v5.4-job-ring",
194					     "fsl,sec-v5.0-job-ring",
195					     "fsl,sec-v4.0-job-ring";
196				reg	   = <0x40000 0x10000>;
197				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
198			};
199
200			rtic@60000 {
201				compatible = "fsl,sec-v5.4-rtic",
202					     "fsl,sec-v5.0-rtic",
203					     "fsl,sec-v4.0-rtic";
204				#address-cells = <1>;
205				#size-cells = <1>;
206				reg = <0x60000 0x100 0x60e00 0x18>;
207				ranges = <0x0 0x60100 0x500>;
208
209				rtic_a: rtic-a@0 {
210					compatible = "fsl,sec-v5.4-rtic-memory",
211						     "fsl,sec-v5.0-rtic-memory",
212						     "fsl,sec-v4.0-rtic-memory";
213					reg = <0x00 0x20 0x100 0x100>;
214				};
215
216				rtic_b: rtic-b@20 {
217					compatible = "fsl,sec-v5.4-rtic-memory",
218						     "fsl,sec-v5.0-rtic-memory",
219						     "fsl,sec-v4.0-rtic-memory";
220					reg = <0x20 0x20 0x200 0x100>;
221				};
222
223				rtic_c: rtic-c@40 {
224					compatible = "fsl,sec-v5.4-rtic-memory",
225						     "fsl,sec-v5.0-rtic-memory",
226						     "fsl,sec-v4.0-rtic-memory";
227					reg = <0x40 0x20 0x300 0x100>;
228				};
229
230				rtic_d: rtic-d@60 {
231					compatible = "fsl,sec-v5.4-rtic-memory",
232						     "fsl,sec-v5.0-rtic-memory",
233						     "fsl,sec-v4.0-rtic-memory";
234					reg = <0x60 0x20 0x400 0x100>;
235				};
236			};
237		};
238
239		sec_mon: sec_mon@1e90000 {
240			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
241				     "fsl,sec-v4.0-mon";
242			reg = <0x0 0x1e90000 0x0 0x10000>;
243			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
244				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
245		};
246
247		dcfg: dcfg@1ee0000 {
248			compatible = "fsl,ls1012a-dcfg",
249				     "syscon";
250			reg = <0x0 0x1ee0000 0x0 0x10000>;
251			big-endian;
252		};
253
254		clockgen: clocking@1ee1000 {
255			compatible = "fsl,ls1012a-clockgen";
256			reg = <0x0 0x1ee1000 0x0 0x1000>;
257			#clock-cells = <2>;
258			clocks = <&sysclk &coreclk>;
259			clock-names = "sysclk", "coreclk";
260		};
261
262		tmu: tmu@1f00000 {
263			compatible = "fsl,qoriq-tmu";
264			reg = <0x0 0x1f00000 0x0 0x10000>;
265			interrupts = <0 33 0x4>;
266			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
267			fsl,tmu-calibration = <0x00000000 0x00000026
268					       0x00000001 0x0000002d
269					       0x00000002 0x00000032
270					       0x00000003 0x00000039
271					       0x00000004 0x0000003f
272					       0x00000005 0x00000046
273					       0x00000006 0x0000004d
274					       0x00000007 0x00000054
275					       0x00000008 0x0000005a
276					       0x00000009 0x00000061
277					       0x0000000a 0x0000006a
278					       0x0000000b 0x00000071
279
280					       0x00010000 0x00000025
281					       0x00010001 0x0000002c
282					       0x00010002 0x00000035
283					       0x00010003 0x0000003d
284					       0x00010004 0x00000045
285					       0x00010005 0x0000004e
286					       0x00010006 0x00000057
287					       0x00010007 0x00000061
288					       0x00010008 0x0000006b
289					       0x00010009 0x00000076
290
291					       0x00020000 0x00000029
292					       0x00020001 0x00000033
293					       0x00020002 0x0000003d
294					       0x00020003 0x00000049
295					       0x00020004 0x00000056
296					       0x00020005 0x00000061
297					       0x00020006 0x0000006d
298
299					       0x00030000 0x00000021
300					       0x00030001 0x0000002a
301					       0x00030002 0x0000003c
302					       0x00030003 0x0000004e>;
303			big-endian;
304			#thermal-sensor-cells = <1>;
305		};
306
307		thermal-zones {
308			cpu_thermal: cpu-thermal {
309				polling-delay-passive = <1000>;
310				polling-delay = <5000>;
311				thermal-sensors = <&tmu 0>;
312
313				trips {
314					cpu_alert: cpu-alert {
315						temperature = <85000>;
316						hysteresis = <2000>;
317						type = "passive";
318					};
319
320					cpu_crit: cpu-crit {
321						temperature = <95000>;
322						hysteresis = <2000>;
323						type = "critical";
324					};
325				};
326
327				cooling-maps {
328					map0 {
329						trip = <&cpu_alert>;
330						cooling-device =
331							<&cpu0 THERMAL_NO_LIMIT
332							THERMAL_NO_LIMIT>;
333					};
334				};
335			};
336		};
337
338		i2c0: i2c@2180000 {
339			compatible = "fsl,vf610-i2c";
340			#address-cells = <1>;
341			#size-cells = <0>;
342			reg = <0x0 0x2180000 0x0 0x10000>;
343			interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
344			clocks = <&clockgen 4 0>;
345			status = "disabled";
346		};
347
348		i2c1: i2c@2190000 {
349			compatible = "fsl,vf610-i2c";
350			#address-cells = <1>;
351			#size-cells = <0>;
352			reg = <0x0 0x2190000 0x0 0x10000>;
353			interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
354			clocks = <&clockgen 4 0>;
355			status = "disabled";
356		};
357
358		duart0: serial@21c0500 {
359			compatible = "fsl,ns16550", "ns16550a";
360			reg = <0x00 0x21c0500 0x0 0x100>;
361			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
362			clocks = <&clockgen 4 0>;
363			status = "disabled";
364		};
365
366		duart1: serial@21c0600 {
367			compatible = "fsl,ns16550", "ns16550a";
368			reg = <0x00 0x21c0600 0x0 0x100>;
369			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
370			clocks = <&clockgen 4 0>;
371			status = "disabled";
372		};
373
374		gpio0: gpio@2300000 {
375			compatible = "fsl,qoriq-gpio";
376			reg = <0x0 0x2300000 0x0 0x10000>;
377			interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
378			gpio-controller;
379			#gpio-cells = <2>;
380			interrupt-controller;
381			#interrupt-cells = <2>;
382		};
383
384		gpio1: gpio@2310000 {
385			compatible = "fsl,qoriq-gpio";
386			reg = <0x0 0x2310000 0x0 0x10000>;
387			interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
388			gpio-controller;
389			#gpio-cells = <2>;
390			interrupt-controller;
391			#interrupt-cells = <2>;
392		};
393
394		wdog0: wdog@2ad0000 {
395			compatible = "fsl,ls1012a-wdt",
396				     "fsl,imx21-wdt";
397			reg = <0x0 0x2ad0000 0x0 0x10000>;
398			interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
399			clocks = <&clockgen 4 0>;
400			big-endian;
401		};
402
403		sai1: sai@2b50000 {
404			#sound-dai-cells = <0>;
405			compatible = "fsl,vf610-sai";
406			reg = <0x0 0x2b50000 0x0 0x10000>;
407			interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
408			clocks = <&clockgen 4 3>, <&clockgen 4 3>,
409				 <&clockgen 4 3>, <&clockgen 4 3>;
410			clock-names = "bus", "mclk1", "mclk2", "mclk3";
411			dma-names = "tx", "rx";
412			dmas = <&edma0 1 47>,
413			       <&edma0 1 46>;
414			status = "disabled";
415		};
416
417		sai2: sai@2b60000 {
418			#sound-dai-cells = <0>;
419			compatible = "fsl,vf610-sai";
420			reg = <0x0 0x2b60000 0x0 0x10000>;
421			interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
422			clocks = <&clockgen 4 3>, <&clockgen 4 3>,
423				 <&clockgen 4 3>, <&clockgen 4 3>;
424			clock-names = "bus", "mclk1", "mclk2", "mclk3";
425			dma-names = "tx", "rx";
426			dmas = <&edma0 1 45>,
427			       <&edma0 1 44>;
428			status = "disabled";
429		};
430
431		edma0: edma@2c00000 {
432			#dma-cells = <2>;
433			compatible = "fsl,vf610-edma";
434			reg = <0x0 0x2c00000 0x0 0x10000>,
435			      <0x0 0x2c10000 0x0 0x10000>,
436			      <0x0 0x2c20000 0x0 0x10000>;
437			interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
438				     <0 103 IRQ_TYPE_LEVEL_HIGH>;
439			interrupt-names = "edma-tx", "edma-err";
440			dma-channels = <32>;
441			big-endian;
442			clock-names = "dmamux0", "dmamux1";
443			clocks = <&clockgen 4 3>,
444				 <&clockgen 4 3>;
445		};
446
447		usb0: usb3@2f00000 {
448			compatible = "snps,dwc3";
449			reg = <0x0 0x2f00000 0x0 0x10000>;
450			interrupts = <0 60 0x4>;
451			dr_mode = "host";
452			snps,quirk-frame-length-adjustment = <0x20>;
453			snps,dis_rxdet_inp3_quirk;
454		};
455
456		sata: sata@3200000 {
457			compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
458			reg = <0x0 0x3200000 0x0 0x10000>,
459				<0x0 0x20140520 0x0 0x4>;
460			reg-names = "ahci", "sata-ecc";
461			interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
462			clocks = <&clockgen 4 0>;
463			dma-coherent;
464			status = "disabled";
465		};
466
467		usb1: usb2@8600000 {
468			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
469			reg = <0x0 0x8600000 0x0 0x1000>;
470			interrupts = <0 139 0x4>;
471			dr_mode = "host";
472			phy_type = "ulpi";
473		};
474	};
475};
476