1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1012A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 *
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/thermal/thermal.h>
11
12/ {
13	compatible = "fsl,ls1012a";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	aliases {
19		crypto = &crypto;
20		rtc1 = &ftm_alarm0;
21		rtic-a = &rtic_a;
22		rtic-b = &rtic_b;
23		rtic-c = &rtic_c;
24		rtic-d = &rtic_d;
25		sec-mon = &sec_mon;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a53";
35			reg = <0x0>;
36			clocks = <&clockgen 1 0>;
37			#cooling-cells = <2>;
38			cpu-idle-states = <&CPU_PH20>;
39		};
40	};
41
42	idle-states {
43		/*
44		 * PSCI node is not added default, U-boot will add missing
45		 * parts if it determines to use PSCI.
46		 */
47		entry-method = "psci";
48
49		CPU_PH20: cpu-ph20 {
50			compatible = "arm,idle-state";
51			idle-state-name = "PH20";
52			arm,psci-suspend-param = <0x0>;
53			entry-latency-us = <1000>;
54			exit-latency-us = <1000>;
55			min-residency-us = <3000>;
56		};
57	};
58
59	sysclk: sysclk {
60		compatible = "fixed-clock";
61		#clock-cells = <0>;
62		clock-frequency = <125000000>;
63		clock-output-names = "sysclk";
64	};
65
66	coreclk: coreclk {
67		compatible = "fixed-clock";
68		#clock-cells = <0>;
69		clock-frequency = <100000000>;
70		clock-output-names = "coreclk";
71	};
72
73	timer {
74		compatible = "arm,armv8-timer";
75		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
76			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
77			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
78			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
79	};
80
81	pmu {
82		compatible = "arm,armv8-pmuv3";
83		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
84	};
85
86	gic: interrupt-controller@1400000 {
87		compatible = "arm,gic-400";
88		#interrupt-cells = <3>;
89		interrupt-controller;
90		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
91		      <0x0 0x1402000 0 0x2000>, /* GICC */
92		      <0x0 0x1404000 0 0x2000>, /* GICH */
93		      <0x0 0x1406000 0 0x2000>; /* GICV */
94		interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
95	};
96
97	reboot {
98		compatible = "syscon-reboot";
99		regmap = <&dcfg>;
100		offset = <0xb0>;
101		mask = <0x02>;
102	};
103
104	thermal-zones {
105		cpu_thermal: cpu-thermal {
106			polling-delay-passive = <1000>;
107			polling-delay = <5000>;
108			thermal-sensors = <&tmu 0>;
109
110			trips {
111				cpu_alert: cpu-alert {
112					temperature = <85000>;
113					hysteresis = <2000>;
114					type = "passive";
115				};
116
117				cpu_crit: cpu-crit {
118					temperature = <95000>;
119					hysteresis = <2000>;
120					type = "critical";
121				};
122			};
123
124			cooling-maps {
125				map0 {
126					trip = <&cpu_alert>;
127					cooling-device =
128						<&cpu0 THERMAL_NO_LIMIT
129						THERMAL_NO_LIMIT>;
130				};
131			};
132		};
133	};
134
135	soc {
136		compatible = "simple-bus";
137		#address-cells = <2>;
138		#size-cells = <2>;
139		ranges;
140
141		qspi: spi@1550000 {
142			compatible = "fsl,ls1021a-qspi";
143			#address-cells = <1>;
144			#size-cells = <0>;
145			reg = <0x0 0x1550000 0x0 0x10000>,
146				<0x0 0x40000000 0x0 0x10000000>;
147			reg-names = "QuadSPI", "QuadSPI-memory";
148			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
149			clock-names = "qspi_en", "qspi";
150			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
151			status = "disabled";
152		};
153
154		esdhc0: esdhc@1560000 {
155			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
156			reg = <0x0 0x1560000 0x0 0x10000>;
157			interrupts = <0 62 0x4>;
158			clocks = <&clockgen 4 0>;
159			voltage-ranges = <1800 1800 3300 3300>;
160			sdhci,auto-cmd12;
161			big-endian;
162			bus-width = <4>;
163			status = "disabled";
164		};
165
166		scfg: scfg@1570000 {
167			compatible = "fsl,ls1012a-scfg", "syscon";
168			reg = <0x0 0x1570000 0x0 0x10000>;
169			big-endian;
170		};
171
172		esdhc1: esdhc@1580000 {
173			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
174			reg = <0x0 0x1580000 0x0 0x10000>;
175			interrupts = <0 65 0x4>;
176			clocks = <&clockgen 4 0>;
177			voltage-ranges = <1800 1800 3300 3300>;
178			sdhci,auto-cmd12;
179			big-endian;
180			broken-cd;
181			bus-width = <4>;
182			status = "disabled";
183		};
184
185		crypto: crypto@1700000 {
186			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
187				     "fsl,sec-v4.0";
188			fsl,sec-era = <8>;
189			#address-cells = <1>;
190			#size-cells = <1>;
191			ranges = <0x0 0x00 0x1700000 0x100000>;
192			reg = <0x00 0x1700000 0x0 0x100000>;
193			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
194
195			sec_jr0: jr@10000 {
196				compatible = "fsl,sec-v5.4-job-ring",
197					     "fsl,sec-v5.0-job-ring",
198					     "fsl,sec-v4.0-job-ring";
199				reg	   = <0x10000 0x10000>;
200				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
201			};
202
203			sec_jr1: jr@20000 {
204				compatible = "fsl,sec-v5.4-job-ring",
205					     "fsl,sec-v5.0-job-ring",
206					     "fsl,sec-v4.0-job-ring";
207				reg	   = <0x20000 0x10000>;
208				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
209			};
210
211			sec_jr2: jr@30000 {
212				compatible = "fsl,sec-v5.4-job-ring",
213					     "fsl,sec-v5.0-job-ring",
214					     "fsl,sec-v4.0-job-ring";
215				reg	   = <0x30000 0x10000>;
216				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
217			};
218
219			sec_jr3: jr@40000 {
220				compatible = "fsl,sec-v5.4-job-ring",
221					     "fsl,sec-v5.0-job-ring",
222					     "fsl,sec-v4.0-job-ring";
223				reg	   = <0x40000 0x10000>;
224				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
225			};
226
227			rtic@60000 {
228				compatible = "fsl,sec-v5.4-rtic",
229					     "fsl,sec-v5.0-rtic",
230					     "fsl,sec-v4.0-rtic";
231				#address-cells = <1>;
232				#size-cells = <1>;
233				reg = <0x60000 0x100 0x60e00 0x18>;
234				ranges = <0x0 0x60100 0x500>;
235
236				rtic_a: rtic-a@0 {
237					compatible = "fsl,sec-v5.4-rtic-memory",
238						     "fsl,sec-v5.0-rtic-memory",
239						     "fsl,sec-v4.0-rtic-memory";
240					reg = <0x00 0x20 0x100 0x100>;
241				};
242
243				rtic_b: rtic-b@20 {
244					compatible = "fsl,sec-v5.4-rtic-memory",
245						     "fsl,sec-v5.0-rtic-memory",
246						     "fsl,sec-v4.0-rtic-memory";
247					reg = <0x20 0x20 0x200 0x100>;
248				};
249
250				rtic_c: rtic-c@40 {
251					compatible = "fsl,sec-v5.4-rtic-memory",
252						     "fsl,sec-v5.0-rtic-memory",
253						     "fsl,sec-v4.0-rtic-memory";
254					reg = <0x40 0x20 0x300 0x100>;
255				};
256
257				rtic_d: rtic-d@60 {
258					compatible = "fsl,sec-v5.4-rtic-memory",
259						     "fsl,sec-v5.0-rtic-memory",
260						     "fsl,sec-v4.0-rtic-memory";
261					reg = <0x60 0x20 0x400 0x100>;
262				};
263			};
264		};
265
266		sec_mon: sec_mon@1e90000 {
267			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
268				     "fsl,sec-v4.0-mon";
269			reg = <0x0 0x1e90000 0x0 0x10000>;
270			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
271				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
272		};
273
274		dcfg: dcfg@1ee0000 {
275			compatible = "fsl,ls1012a-dcfg",
276				     "syscon";
277			reg = <0x0 0x1ee0000 0x0 0x10000>;
278			big-endian;
279		};
280
281		clockgen: clocking@1ee1000 {
282			compatible = "fsl,ls1012a-clockgen";
283			reg = <0x0 0x1ee1000 0x0 0x1000>;
284			#clock-cells = <2>;
285			clocks = <&sysclk &coreclk>;
286			clock-names = "sysclk", "coreclk";
287		};
288
289		tmu: tmu@1f00000 {
290			compatible = "fsl,qoriq-tmu";
291			reg = <0x0 0x1f00000 0x0 0x10000>;
292			interrupts = <0 33 0x4>;
293			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
294			fsl,tmu-calibration = <0x00000000 0x00000026
295					       0x00000001 0x0000002d
296					       0x00000002 0x00000032
297					       0x00000003 0x00000039
298					       0x00000004 0x0000003f
299					       0x00000005 0x00000046
300					       0x00000006 0x0000004d
301					       0x00000007 0x00000054
302					       0x00000008 0x0000005a
303					       0x00000009 0x00000061
304					       0x0000000a 0x0000006a
305					       0x0000000b 0x00000071
306
307					       0x00010000 0x00000025
308					       0x00010001 0x0000002c
309					       0x00010002 0x00000035
310					       0x00010003 0x0000003d
311					       0x00010004 0x00000045
312					       0x00010005 0x0000004e
313					       0x00010006 0x00000057
314					       0x00010007 0x00000061
315					       0x00010008 0x0000006b
316					       0x00010009 0x00000076
317
318					       0x00020000 0x00000029
319					       0x00020001 0x00000033
320					       0x00020002 0x0000003d
321					       0x00020003 0x00000049
322					       0x00020004 0x00000056
323					       0x00020005 0x00000061
324					       0x00020006 0x0000006d
325
326					       0x00030000 0x00000021
327					       0x00030001 0x0000002a
328					       0x00030002 0x0000003c
329					       0x00030003 0x0000004e>;
330			big-endian;
331			#thermal-sensor-cells = <1>;
332		};
333
334		i2c0: i2c@2180000 {
335			compatible = "fsl,vf610-i2c";
336			#address-cells = <1>;
337			#size-cells = <0>;
338			reg = <0x0 0x2180000 0x0 0x10000>;
339			interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
340			clocks = <&clockgen 4 3>;
341			status = "disabled";
342		};
343
344		i2c1: i2c@2190000 {
345			compatible = "fsl,vf610-i2c";
346			#address-cells = <1>;
347			#size-cells = <0>;
348			reg = <0x0 0x2190000 0x0 0x10000>;
349			interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
350			clocks = <&clockgen 4 3>;
351			status = "disabled";
352		};
353
354		dspi: spi@2100000 {
355			compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
356			#address-cells = <1>;
357			#size-cells = <0>;
358			reg = <0x0 0x2100000 0x0 0x10000>;
359			interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
360			clock-names = "dspi";
361			clocks = <&clockgen 4 0>;
362			spi-num-chipselects = <5>;
363			big-endian;
364			status = "disabled";
365		};
366
367		duart0: serial@21c0500 {
368			compatible = "fsl,ns16550", "ns16550a";
369			reg = <0x00 0x21c0500 0x0 0x100>;
370			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
371			clocks = <&clockgen 4 0>;
372			status = "disabled";
373		};
374
375		duart1: serial@21c0600 {
376			compatible = "fsl,ns16550", "ns16550a";
377			reg = <0x00 0x21c0600 0x0 0x100>;
378			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
379			clocks = <&clockgen 4 0>;
380			status = "disabled";
381		};
382
383		gpio0: gpio@2300000 {
384			compatible = "fsl,qoriq-gpio";
385			reg = <0x0 0x2300000 0x0 0x10000>;
386			interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
387			gpio-controller;
388			#gpio-cells = <2>;
389			interrupt-controller;
390			#interrupt-cells = <2>;
391		};
392
393		gpio1: gpio@2310000 {
394			compatible = "fsl,qoriq-gpio";
395			reg = <0x0 0x2310000 0x0 0x10000>;
396			interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
397			gpio-controller;
398			#gpio-cells = <2>;
399			interrupt-controller;
400			#interrupt-cells = <2>;
401		};
402
403		wdog0: wdog@2ad0000 {
404			compatible = "fsl,ls1012a-wdt",
405				     "fsl,imx21-wdt";
406			reg = <0x0 0x2ad0000 0x0 0x10000>;
407			interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
408			clocks = <&clockgen 4 0>;
409			big-endian;
410		};
411
412		sai1: sai@2b50000 {
413			#sound-dai-cells = <0>;
414			compatible = "fsl,vf610-sai";
415			reg = <0x0 0x2b50000 0x0 0x10000>;
416			interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
417			clocks = <&clockgen 4 3>, <&clockgen 4 3>,
418				 <&clockgen 4 3>, <&clockgen 4 3>;
419			clock-names = "bus", "mclk1", "mclk2", "mclk3";
420			dma-names = "tx", "rx";
421			dmas = <&edma0 1 47>,
422			       <&edma0 1 46>;
423			status = "disabled";
424		};
425
426		sai2: sai@2b60000 {
427			#sound-dai-cells = <0>;
428			compatible = "fsl,vf610-sai";
429			reg = <0x0 0x2b60000 0x0 0x10000>;
430			interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
431			clocks = <&clockgen 4 3>, <&clockgen 4 3>,
432				 <&clockgen 4 3>, <&clockgen 4 3>;
433			clock-names = "bus", "mclk1", "mclk2", "mclk3";
434			dma-names = "tx", "rx";
435			dmas = <&edma0 1 45>,
436			       <&edma0 1 44>;
437			status = "disabled";
438		};
439
440		edma0: edma@2c00000 {
441			#dma-cells = <2>;
442			compatible = "fsl,vf610-edma";
443			reg = <0x0 0x2c00000 0x0 0x10000>,
444			      <0x0 0x2c10000 0x0 0x10000>,
445			      <0x0 0x2c20000 0x0 0x10000>;
446			interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
447				     <0 103 IRQ_TYPE_LEVEL_HIGH>;
448			interrupt-names = "edma-tx", "edma-err";
449			dma-channels = <32>;
450			big-endian;
451			clock-names = "dmamux0", "dmamux1";
452			clocks = <&clockgen 4 3>,
453				 <&clockgen 4 3>;
454		};
455
456		usb0: usb3@2f00000 {
457			compatible = "snps,dwc3";
458			reg = <0x0 0x2f00000 0x0 0x10000>;
459			interrupts = <0 60 0x4>;
460			dr_mode = "host";
461			snps,quirk-frame-length-adjustment = <0x20>;
462			snps,dis_rxdet_inp3_quirk;
463			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
464		};
465
466		sata: sata@3200000 {
467			compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
468			reg = <0x0 0x3200000 0x0 0x10000>,
469				<0x0 0x20140520 0x0 0x4>;
470			reg-names = "ahci", "sata-ecc";
471			interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
472			clocks = <&clockgen 4 0>;
473			dma-coherent;
474			status = "disabled";
475		};
476
477		usb1: usb2@8600000 {
478			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
479			reg = <0x0 0x8600000 0x0 0x1000>;
480			interrupts = <0 139 0x4>;
481			dr_mode = "host";
482			phy_type = "ulpi";
483		};
484
485		msi: msi-controller1@1572000 {
486			compatible = "fsl,ls1012a-msi";
487			reg = <0x0 0x1572000 0x0 0x8>;
488			msi-controller;
489			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
490		};
491
492		pcie: pcie@3400000 {
493			compatible = "fsl,ls1012a-pcie";
494			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
495			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
496			reg-names = "regs", "config";
497			interrupts = <0 118 0x4>, /* controller interrupt */
498				     <0 117 0x4>; /* PME interrupt */
499			interrupt-names = "aer", "pme";
500			#address-cells = <3>;
501			#size-cells = <2>;
502			device_type = "pci";
503			num-viewport = <2>;
504			bus-range = <0x0 0xff>;
505			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
506				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
507			msi-parent = <&msi>;
508			#interrupt-cells = <1>;
509			interrupt-map-mask = <0 0 0 7>;
510			interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
511					<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
512					<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
513					<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
514			status = "disabled";
515		};
516
517		rcpm: power-controller@1ee2140 {
518			compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
519			reg = <0x0 0x1ee2140 0x0 0x4>;
520			#fsl,rcpm-wakeup-cells = <1>;
521		};
522
523		ftm_alarm0: timer@29d0000 {
524			compatible = "fsl,ls1012a-ftm-alarm";
525			reg = <0x0 0x29d0000 0x0 0x10000>;
526			fsl,rcpm-wakeup = <&rcpm 0x20000>;
527			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
528			big-endian;
529		};
530	};
531
532	firmware {
533		optee {
534			compatible = "linaro,optee-tz";
535			method = "smc";
536		};
537	};
538};
539