1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2019-2020 NXP
7 *
8 */
9
10#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15	compatible = "fsl,ls1012a";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		crypto = &crypto;
22		rtc1 = &ftm_alarm0;
23		rtic-a = &rtic_a;
24		rtic-b = &rtic_b;
25		rtic-c = &rtic_c;
26		rtic-d = &rtic_d;
27		sec-mon = &sec_mon;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		cpu0: cpu@0 {
35			device_type = "cpu";
36			compatible = "arm,cortex-a53";
37			reg = <0x0>;
38			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
39			#cooling-cells = <2>;
40			cpu-idle-states = <&CPU_PH20>;
41		};
42	};
43
44	idle-states {
45		/*
46		 * PSCI node is not added default, U-boot will add missing
47		 * parts if it determines to use PSCI.
48		 */
49		entry-method = "psci";
50
51		CPU_PH20: cpu-ph20 {
52			compatible = "arm,idle-state";
53			idle-state-name = "PH20";
54			arm,psci-suspend-param = <0x0>;
55			entry-latency-us = <1000>;
56			exit-latency-us = <1000>;
57			min-residency-us = <3000>;
58		};
59	};
60
61	sysclk: sysclk {
62		compatible = "fixed-clock";
63		#clock-cells = <0>;
64		clock-frequency = <125000000>;
65		clock-output-names = "sysclk";
66	};
67
68	coreclk: coreclk {
69		compatible = "fixed-clock";
70		#clock-cells = <0>;
71		clock-frequency = <100000000>;
72		clock-output-names = "coreclk";
73	};
74
75	timer {
76		compatible = "arm,armv8-timer";
77		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
78			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
79			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
80			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
81	};
82
83	pmu {
84		compatible = "arm,armv8-pmuv3";
85		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
86	};
87
88	gic: interrupt-controller@1400000 {
89		compatible = "arm,gic-400";
90		#interrupt-cells = <3>;
91		interrupt-controller;
92		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93		      <0x0 0x1402000 0 0x2000>, /* GICC */
94		      <0x0 0x1404000 0 0x2000>, /* GICH */
95		      <0x0 0x1406000 0 0x2000>; /* GICV */
96		interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
97	};
98
99	reboot {
100		compatible = "syscon-reboot";
101		regmap = <&dcfg>;
102		offset = <0xb0>;
103		mask = <0x02>;
104	};
105
106	thermal-zones {
107		cpu_thermal: cpu-thermal {
108			polling-delay-passive = <1000>;
109			polling-delay = <5000>;
110			thermal-sensors = <&tmu 0>;
111
112			trips {
113				cpu_alert: cpu-alert {
114					temperature = <85000>;
115					hysteresis = <2000>;
116					type = "passive";
117				};
118
119				cpu_crit: cpu-crit {
120					temperature = <95000>;
121					hysteresis = <2000>;
122					type = "critical";
123				};
124			};
125
126			cooling-maps {
127				map0 {
128					trip = <&cpu_alert>;
129					cooling-device =
130						<&cpu0 THERMAL_NO_LIMIT
131						THERMAL_NO_LIMIT>;
132				};
133			};
134		};
135	};
136
137	soc {
138		compatible = "simple-bus";
139		#address-cells = <2>;
140		#size-cells = <2>;
141		ranges;
142
143		qspi: spi@1550000 {
144			compatible = "fsl,ls1021a-qspi";
145			#address-cells = <1>;
146			#size-cells = <0>;
147			reg = <0x0 0x1550000 0x0 0x10000>,
148				<0x0 0x40000000 0x0 0x10000000>;
149			reg-names = "QuadSPI", "QuadSPI-memory";
150			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
151			clock-names = "qspi_en", "qspi";
152			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
153					    QORIQ_CLK_PLL_DIV(1)>,
154				 <&clockgen QORIQ_CLK_PLATFORM_PLL
155					    QORIQ_CLK_PLL_DIV(1)>;
156			status = "disabled";
157		};
158
159		esdhc0: esdhc@1560000 {
160			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
161			reg = <0x0 0x1560000 0x0 0x10000>;
162			interrupts = <0 62 0x4>;
163			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
164					    QORIQ_CLK_PLL_DIV(1)>;
165			voltage-ranges = <1800 1800 3300 3300>;
166			sdhci,auto-cmd12;
167			big-endian;
168			bus-width = <4>;
169			status = "disabled";
170		};
171
172		scfg: scfg@1570000 {
173			compatible = "fsl,ls1012a-scfg", "syscon";
174			reg = <0x0 0x1570000 0x0 0x10000>;
175			big-endian;
176		};
177
178		esdhc1: esdhc@1580000 {
179			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
180			reg = <0x0 0x1580000 0x0 0x10000>;
181			interrupts = <0 65 0x4>;
182			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
183					    QORIQ_CLK_PLL_DIV(1)>;
184			voltage-ranges = <1800 1800 3300 3300>;
185			sdhci,auto-cmd12;
186			big-endian;
187			broken-cd;
188			bus-width = <4>;
189			status = "disabled";
190		};
191
192		crypto: crypto@1700000 {
193			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
194				     "fsl,sec-v4.0";
195			fsl,sec-era = <8>;
196			#address-cells = <1>;
197			#size-cells = <1>;
198			ranges = <0x0 0x00 0x1700000 0x100000>;
199			reg = <0x00 0x1700000 0x0 0x100000>;
200			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
201
202			sec_jr0: jr@10000 {
203				compatible = "fsl,sec-v5.4-job-ring",
204					     "fsl,sec-v5.0-job-ring",
205					     "fsl,sec-v4.0-job-ring";
206				reg	   = <0x10000 0x10000>;
207				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
208			};
209
210			sec_jr1: jr@20000 {
211				compatible = "fsl,sec-v5.4-job-ring",
212					     "fsl,sec-v5.0-job-ring",
213					     "fsl,sec-v4.0-job-ring";
214				reg	   = <0x20000 0x10000>;
215				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
216			};
217
218			sec_jr2: jr@30000 {
219				compatible = "fsl,sec-v5.4-job-ring",
220					     "fsl,sec-v5.0-job-ring",
221					     "fsl,sec-v4.0-job-ring";
222				reg	   = <0x30000 0x10000>;
223				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
224			};
225
226			sec_jr3: jr@40000 {
227				compatible = "fsl,sec-v5.4-job-ring",
228					     "fsl,sec-v5.0-job-ring",
229					     "fsl,sec-v4.0-job-ring";
230				reg	   = <0x40000 0x10000>;
231				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
232			};
233
234			rtic@60000 {
235				compatible = "fsl,sec-v5.4-rtic",
236					     "fsl,sec-v5.0-rtic",
237					     "fsl,sec-v4.0-rtic";
238				#address-cells = <1>;
239				#size-cells = <1>;
240				reg = <0x60000 0x100 0x60e00 0x18>;
241				ranges = <0x0 0x60100 0x500>;
242
243				rtic_a: rtic-a@0 {
244					compatible = "fsl,sec-v5.4-rtic-memory",
245						     "fsl,sec-v5.0-rtic-memory",
246						     "fsl,sec-v4.0-rtic-memory";
247					reg = <0x00 0x20 0x100 0x100>;
248				};
249
250				rtic_b: rtic-b@20 {
251					compatible = "fsl,sec-v5.4-rtic-memory",
252						     "fsl,sec-v5.0-rtic-memory",
253						     "fsl,sec-v4.0-rtic-memory";
254					reg = <0x20 0x20 0x200 0x100>;
255				};
256
257				rtic_c: rtic-c@40 {
258					compatible = "fsl,sec-v5.4-rtic-memory",
259						     "fsl,sec-v5.0-rtic-memory",
260						     "fsl,sec-v4.0-rtic-memory";
261					reg = <0x40 0x20 0x300 0x100>;
262				};
263
264				rtic_d: rtic-d@60 {
265					compatible = "fsl,sec-v5.4-rtic-memory",
266						     "fsl,sec-v5.0-rtic-memory",
267						     "fsl,sec-v4.0-rtic-memory";
268					reg = <0x60 0x20 0x400 0x100>;
269				};
270			};
271		};
272
273		sec_mon: sec_mon@1e90000 {
274			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
275				     "fsl,sec-v4.0-mon";
276			reg = <0x0 0x1e90000 0x0 0x10000>;
277			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
278				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
279		};
280
281		dcfg: dcfg@1ee0000 {
282			compatible = "fsl,ls1012a-dcfg",
283				     "syscon";
284			reg = <0x0 0x1ee0000 0x0 0x10000>;
285			big-endian;
286		};
287
288		clockgen: clocking@1ee1000 {
289			compatible = "fsl,ls1012a-clockgen";
290			reg = <0x0 0x1ee1000 0x0 0x1000>;
291			#clock-cells = <2>;
292			clocks = <&sysclk &coreclk>;
293			clock-names = "sysclk", "coreclk";
294		};
295
296		tmu: tmu@1f00000 {
297			compatible = "fsl,qoriq-tmu";
298			reg = <0x0 0x1f00000 0x0 0x10000>;
299			interrupts = <0 33 0x4>;
300			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
301			fsl,tmu-calibration = <0x00000000 0x00000025
302					       0x00000001 0x0000002c
303					       0x00000002 0x00000032
304					       0x00000003 0x00000039
305					       0x00000004 0x0000003f
306					       0x00000005 0x00000046
307					       0x00000006 0x0000004c
308					       0x00000007 0x00000053
309					       0x00000008 0x00000059
310					       0x00000009 0x0000005f
311					       0x0000000a 0x00000066
312					       0x0000000b 0x0000006c
313
314					       0x00010000 0x00000026
315					       0x00010001 0x0000002d
316					       0x00010002 0x00000035
317					       0x00010003 0x0000003d
318					       0x00010004 0x00000045
319					       0x00010005 0x0000004d
320					       0x00010006 0x00000055
321					       0x00010007 0x0000005d
322					       0x00010008 0x00000065
323					       0x00010009 0x0000006d
324
325					       0x00020000 0x00000026
326					       0x00020001 0x00000030
327					       0x00020002 0x0000003a
328					       0x00020003 0x00000044
329					       0x00020004 0x0000004e
330					       0x00020005 0x00000059
331					       0x00020006 0x00000063
332
333					       0x00030000 0x00000014
334					       0x00030001 0x00000021
335					       0x00030002 0x0000002e
336					       0x00030003 0x0000003a
337					       0x00030004 0x00000047
338					       0x00030005 0x00000053
339					       0x00030006 0x00000060>;
340			big-endian;
341			#thermal-sensor-cells = <1>;
342		};
343
344		i2c0: i2c@2180000 {
345			compatible = "fsl,vf610-i2c";
346			#address-cells = <1>;
347			#size-cells = <0>;
348			reg = <0x0 0x2180000 0x0 0x10000>;
349			interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
350			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
351					    QORIQ_CLK_PLL_DIV(4)>;
352			status = "disabled";
353		};
354
355		i2c1: i2c@2190000 {
356			compatible = "fsl,vf610-i2c";
357			#address-cells = <1>;
358			#size-cells = <0>;
359			reg = <0x0 0x2190000 0x0 0x10000>;
360			interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
361			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
362					    QORIQ_CLK_PLL_DIV(4)>;
363			status = "disabled";
364		};
365
366		dspi: spi@2100000 {
367			compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
368			#address-cells = <1>;
369			#size-cells = <0>;
370			reg = <0x0 0x2100000 0x0 0x10000>;
371			interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
372			clock-names = "dspi";
373			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
374					    QORIQ_CLK_PLL_DIV(1)>;
375			spi-num-chipselects = <5>;
376			big-endian;
377			status = "disabled";
378		};
379
380		duart0: serial@21c0500 {
381			compatible = "fsl,ns16550", "ns16550a";
382			reg = <0x00 0x21c0500 0x0 0x100>;
383			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
384			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
385					    QORIQ_CLK_PLL_DIV(1)>;
386			status = "disabled";
387		};
388
389		duart1: serial@21c0600 {
390			compatible = "fsl,ns16550", "ns16550a";
391			reg = <0x00 0x21c0600 0x0 0x100>;
392			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
393			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
394					    QORIQ_CLK_PLL_DIV(1)>;
395			status = "disabled";
396		};
397
398		gpio0: gpio@2300000 {
399			compatible = "fsl,qoriq-gpio";
400			reg = <0x0 0x2300000 0x0 0x10000>;
401			interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
402			gpio-controller;
403			#gpio-cells = <2>;
404			interrupt-controller;
405			#interrupt-cells = <2>;
406		};
407
408		gpio1: gpio@2310000 {
409			compatible = "fsl,qoriq-gpio";
410			reg = <0x0 0x2310000 0x0 0x10000>;
411			interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
412			gpio-controller;
413			#gpio-cells = <2>;
414			interrupt-controller;
415			#interrupt-cells = <2>;
416		};
417
418		wdog0: watchdog@2ad0000 {
419			compatible = "fsl,ls1012a-wdt",
420				     "fsl,imx21-wdt";
421			reg = <0x0 0x2ad0000 0x0 0x10000>;
422			interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
423			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>;
424			big-endian;
425		};
426
427		sai1: sai@2b50000 {
428			#sound-dai-cells = <0>;
429			compatible = "fsl,vf610-sai";
430			reg = <0x0 0x2b50000 0x0 0x10000>;
431			interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
432			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
433					    QORIQ_CLK_PLL_DIV(4)>,
434				 <&clockgen QORIQ_CLK_PLATFORM_PLL
435					    QORIQ_CLK_PLL_DIV(4)>,
436				 <&clockgen QORIQ_CLK_PLATFORM_PLL
437					    QORIQ_CLK_PLL_DIV(4)>,
438				 <&clockgen QORIQ_CLK_PLATFORM_PLL
439					    QORIQ_CLK_PLL_DIV(4)>;
440			clock-names = "bus", "mclk1", "mclk2", "mclk3";
441			dma-names = "tx", "rx";
442			dmas = <&edma0 1 47>,
443			       <&edma0 1 46>;
444			status = "disabled";
445		};
446
447		sai2: sai@2b60000 {
448			#sound-dai-cells = <0>;
449			compatible = "fsl,vf610-sai";
450			reg = <0x0 0x2b60000 0x0 0x10000>;
451			interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
452			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
453					    QORIQ_CLK_PLL_DIV(4)>,
454				 <&clockgen QORIQ_CLK_PLATFORM_PLL
455					    QORIQ_CLK_PLL_DIV(4)>,
456				 <&clockgen QORIQ_CLK_PLATFORM_PLL
457					    QORIQ_CLK_PLL_DIV(4)>,
458				 <&clockgen QORIQ_CLK_PLATFORM_PLL
459					    QORIQ_CLK_PLL_DIV(4)>;
460			clock-names = "bus", "mclk1", "mclk2", "mclk3";
461			dma-names = "tx", "rx";
462			dmas = <&edma0 1 45>,
463			       <&edma0 1 44>;
464			status = "disabled";
465		};
466
467		edma0: edma@2c00000 {
468			#dma-cells = <2>;
469			compatible = "fsl,vf610-edma";
470			reg = <0x0 0x2c00000 0x0 0x10000>,
471			      <0x0 0x2c10000 0x0 0x10000>,
472			      <0x0 0x2c20000 0x0 0x10000>;
473			interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
474				     <0 103 IRQ_TYPE_LEVEL_HIGH>;
475			interrupt-names = "edma-tx", "edma-err";
476			dma-channels = <32>;
477			big-endian;
478			clock-names = "dmamux0", "dmamux1";
479			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
480					    QORIQ_CLK_PLL_DIV(4)>,
481				 <&clockgen QORIQ_CLK_PLATFORM_PLL
482					    QORIQ_CLK_PLL_DIV(4)>;
483		};
484
485		usb0: usb@2f00000 {
486			compatible = "snps,dwc3";
487			reg = <0x0 0x2f00000 0x0 0x10000>;
488			interrupts = <0 60 0x4>;
489			dr_mode = "host";
490			snps,quirk-frame-length-adjustment = <0x20>;
491			snps,dis_rxdet_inp3_quirk;
492			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
493		};
494
495		sata: sata@3200000 {
496			compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
497			reg = <0x0 0x3200000 0x0 0x10000>,
498				<0x0 0x20140520 0x0 0x4>;
499			reg-names = "ahci", "sata-ecc";
500			interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
501			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
502					    QORIQ_CLK_PLL_DIV(1)>;
503			dma-coherent;
504			status = "disabled";
505		};
506
507		usb1: usb@8600000 {
508			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
509			reg = <0x0 0x8600000 0x0 0x1000>;
510			interrupts = <0 139 0x4>;
511			dr_mode = "host";
512			phy_type = "ulpi";
513		};
514
515		msi: msi-controller1@1572000 {
516			compatible = "fsl,ls1012a-msi";
517			reg = <0x0 0x1572000 0x0 0x8>;
518			msi-controller;
519			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
520		};
521
522		pcie1: pcie@3400000 {
523			compatible = "fsl,ls1012a-pcie";
524			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
525			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
526			reg-names = "regs", "config";
527			interrupts = <0 118 0x4>, /* controller interrupt */
528				     <0 117 0x4>; /* PME interrupt */
529			interrupt-names = "aer", "pme";
530			#address-cells = <3>;
531			#size-cells = <2>;
532			device_type = "pci";
533			num-viewport = <2>;
534			bus-range = <0x0 0xff>;
535			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
536				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
537			msi-parent = <&msi>;
538			#interrupt-cells = <1>;
539			interrupt-map-mask = <0 0 0 7>;
540			interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
541					<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
542					<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
543					<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
544			status = "disabled";
545		};
546
547		rcpm: power-controller@1ee2140 {
548			compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
549			reg = <0x0 0x1ee2140 0x0 0x4>;
550			#fsl,rcpm-wakeup-cells = <1>;
551		};
552
553		ftm_alarm0: timer@29d0000 {
554			compatible = "fsl,ls1012a-ftm-alarm";
555			reg = <0x0 0x29d0000 0x0 0x10000>;
556			fsl,rcpm-wakeup = <&rcpm 0x20000>;
557			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
558			big-endian;
559		};
560	};
561
562	firmware {
563		optee {
564			compatible = "linaro,optee-tz";
565			method = "smc";
566		};
567	};
568};
569