1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's ExynosAuto v9 SoC device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6 *
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/soc/samsung,exynos-usi.h>
11
12/ {
13	compatible = "samsung,exynosautov9";
14	#address-cells = <2>;
15	#size-cells = <1>;
16
17	interrupt-parent = <&gic>;
18
19	aliases {
20		pinctrl0 = &pinctrl_alive;
21		pinctrl1 = &pinctrl_aud;
22		pinctrl2 = &pinctrl_fsys0;
23		pinctrl3 = &pinctrl_fsys1;
24		pinctrl4 = &pinctrl_fsys2;
25		pinctrl5 = &pinctrl_peric0;
26		pinctrl6 = &pinctrl_peric1;
27	};
28
29	arm-pmu {
30		compatible = "arm,cortex-a76-pmu";
31		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
35			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
36			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
37			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
38			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
39		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
40				     <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
41	};
42
43	cpus {
44		#address-cells = <1>;
45		#size-cells = <0>;
46
47		cpu-map {
48			cluster0 {
49				core0 {
50					cpu = <&cpu0>;
51				};
52				core1 {
53					cpu = <&cpu1>;
54				};
55				core2 {
56					cpu = <&cpu2>;
57				};
58				core3 {
59					cpu = <&cpu3>;
60				};
61			};
62
63			cluster1 {
64				core0 {
65					cpu = <&cpu4>;
66				};
67				core1 {
68					cpu = <&cpu5>;
69				};
70				core2 {
71					cpu = <&cpu6>;
72				};
73				core3 {
74					cpu = <&cpu7>;
75				};
76			};
77		};
78
79		cpu0: cpu@0 {
80			device_type = "cpu";
81			compatible = "arm,cortex-a76";
82			reg = <0x0>;
83			enable-method = "psci";
84		};
85
86		cpu1: cpu@100 {
87			device_type = "cpu";
88			compatible = "arm,cortex-a76";
89			reg = <0x100>;
90			enable-method = "psci";
91		};
92
93		cpu2: cpu@200 {
94			device_type = "cpu";
95			compatible = "arm,cortex-a76";
96			reg = <0x200>;
97			enable-method = "psci";
98		};
99
100		cpu3: cpu@300 {
101			device_type = "cpu";
102			compatible = "arm,cortex-a76";
103			reg = <0x300>;
104			enable-method = "psci";
105		};
106
107		cpu4: cpu@10000 {
108			device_type = "cpu";
109			compatible = "arm,cortex-a76";
110			reg = <0x10000>;
111			enable-method = "psci";
112		};
113
114		cpu5: cpu@10100 {
115			device_type = "cpu";
116			compatible = "arm,cortex-a76";
117			reg = <0x10100>;
118			enable-method = "psci";
119		};
120
121		cpu6: cpu@10200 {
122			device_type = "cpu";
123			compatible = "arm,cortex-a76";
124			reg = <0x10200>;
125			enable-method = "psci";
126		};
127
128		cpu7: cpu@10300 {
129			device_type = "cpu";
130			compatible = "arm,cortex-a76";
131			reg = <0x10300>;
132			enable-method = "psci";
133		};
134	};
135
136	psci {
137		compatible = "arm,psci-1.0";
138		method = "smc";
139		cpu_suspend = <0xc4000001>;
140		cpu_off = <0x84000002>;
141		cpu_on = <0xc4000003>;
142	};
143
144	timer {
145		compatible = "arm,armv8-timer";
146		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
147			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
148			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
149			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
150	};
151
152	fixed-rate-clocks {
153		xtcxo: clock {
154			compatible = "fixed-clock";
155			#clock-cells = <0>;
156			clock-frequency = <26000000>;
157			clock-output-names = "oscclk";
158		};
159
160		/*
161		 * Keep the stub clock for serial driver, until proper clock
162		 * driver is implemented.
163		 */
164		uart_clock: uart-clock {
165			compatible = "fixed-clock";
166			#clock-cells = <0>;
167			clock-frequency = <133250000>;
168			clock-output-names = "uart";
169		};
170
171		/*
172		 * Keep the stub clock for ufs driver, until proper clock
173		 * driver is implemented.
174		 */
175		ufs_core_clock: ufs-core-clock {
176			compatible = "fixed-clock";
177			#clock-cells = <0>;
178			clock-frequency = <166562500>;
179		};
180	};
181
182	soc: soc@0 {
183		compatible = "simple-bus";
184		#address-cells = <1>;
185		#size-cells = <1>;
186		ranges = <0x0 0x0 0x0 0x20000000>;
187
188		chipid@10000000 {
189			compatible = "samsung,exynos850-chipid";
190			reg = <0x10000000 0x24>;
191		};
192
193		gic: interrupt-controller@10101000 {
194			compatible = "arm,gic-400";
195			#interrupt-cells = <3>;
196			#address-cells = <0>;
197			interrupt-controller;
198			reg = <0x10101000 0x1000>,
199			      <0x10102000 0x2000>,
200			      <0x10104000 0x2000>,
201			      <0x10106000 0x2000>;
202			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
203						 IRQ_TYPE_LEVEL_HIGH)>;
204		};
205
206		pinctrl_alive: pinctrl@10450000 {
207			compatible = "samsung,exynosautov9-pinctrl";
208			reg = <0x10450000 0x1000>;
209
210			wakeup-interrupt-controller {
211				compatible = "samsung,exynosautov9-wakeup-eint";
212			};
213		};
214
215		pinctrl_aud: pinctrl@19c60000{
216			compatible = "samsung,exynosautov9-pinctrl";
217			reg = <0x19c60000 0x1000>;
218		};
219
220		pinctrl_fsys0: pinctrl@17740000 {
221			compatible = "samsung,exynosautov9-pinctrl";
222			reg = <0x17740000 0x1000>;
223			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
224		};
225
226		pinctrl_fsys1: pinctrl@17060000 {
227			compatible = "samsung,exynosautov9-pinctrl";
228			reg = <0x17060000 0x1000>;
229			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
230		};
231
232		pinctrl_fsys2: pinctrl@17c30000 {
233			compatible = "samsung,exynosautov9-pinctrl";
234			reg = <0x17c30000 0x1000>;
235			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
236		};
237
238		pinctrl_peric0: pinctrl@10230000 {
239			compatible = "samsung,exynosautov9-pinctrl";
240			reg = <0x10230000 0x1000>;
241			interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
242		};
243
244		pinctrl_peric1: pinctrl@10830000 {
245			compatible = "samsung,exynosautov9-pinctrl";
246			reg = <0x10830000 0x1000>;
247			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
248		};
249
250		pmu_system_controller: system-controller@10460000 {
251			compatible = "samsung,exynos7-pmu", "syscon";
252			reg = <0x10460000 0x10000>;
253		};
254
255		syscon_fsys2: syscon@17c20000 {
256			compatible = "samsung,exynosautov9-sysreg", "syscon";
257			reg = <0x17c20000 0x1000>;
258		};
259
260		syscon_peric0: syscon@10220000 {
261			compatible = "samsung,exynosautov9-sysreg", "syscon";
262			reg = <0x10220000 0x2000>;
263		};
264
265		usi_0: usi@103000c0 {
266			compatible = "samsung,exynos850-usi";
267			reg = <0x103000c0 0x20>;
268			samsung,sysreg = <&syscon_peric0 0x1000>;
269			samsung,mode = <USI_V2_UART>;
270			samsung,clkreq-on; /* needed for UART mode */
271			#address-cells = <1>;
272			#size-cells = <1>;
273			ranges;
274			clocks = <&uart_clock>, <&uart_clock>;
275			clock-names = "pclk", "ipclk";
276			status = "disabled";
277
278			/* USI: UART */
279			serial_0: serial@10300000 {
280				compatible = "samsung,exynos850-uart";
281				reg = <0x10300000 0xc0>;
282				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
283				pinctrl-names = "default";
284				pinctrl-0 = <&uart0_bus_dual>;
285				clocks = <&uart_clock>, <&uart_clock>;
286				clock-names = "uart", "clk_uart_baud0";
287				status = "disabled";
288			};
289		};
290
291		ufs_0_phy: ufs0-phy@17e04000 {
292			compatible = "samsung,exynosautov9-ufs-phy";
293			reg = <0x17e04000 0xc00>;
294			reg-names = "phy-pma";
295			samsung,pmu-syscon = <&pmu_system_controller>;
296			#phy-cells = <0>;
297			clocks = <&xtcxo>;
298			clock-names = "ref_clk";
299			status = "disabled";
300		};
301
302		ufs_0: ufs0@17e00000 {
303			compatible ="samsung,exynosautov9-ufs";
304
305			reg = <0x17e00000 0x100>,  /* 0: HCI standard */
306				<0x17e01100 0x410>,  /* 1: Vendor-specific */
307				<0x17e80000 0x8000>,  /* 2: UNIPRO */
308				<0x17dc0000 0x2200>;  /* 3: UFS protector */
309			reg-names = "hci", "vs_hci", "unipro", "ufsp";
310			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
311			clocks = <&ufs_core_clock>,
312				<&ufs_core_clock>;
313			clock-names = "core_clk", "sclk_unipro_main";
314			freq-table-hz = <0 0>, <0 0>;
315			pinctrl-names = "default";
316			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
317			phys = <&ufs_0_phy>;
318			phy-names = "ufs-phy";
319			samsung,sysreg = <&syscon_fsys2 0x710>;
320			status = "disabled";
321		};
322	};
323};
324
325#include "exynosautov9-pinctrl.dtsi"
326