1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's ExynosAuto v9 SoC device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6 *
7 */
8
9#include <dt-bindings/clock/samsung,exynosautov9.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/soc/samsung,boot-mode.h>
12#include <dt-bindings/soc/samsung,exynos-usi.h>
13
14/ {
15	compatible = "samsung,exynosautov9";
16	#address-cells = <2>;
17	#size-cells = <1>;
18
19	interrupt-parent = <&gic>;
20
21	aliases {
22		pinctrl0 = &pinctrl_alive;
23		pinctrl1 = &pinctrl_aud;
24		pinctrl2 = &pinctrl_fsys0;
25		pinctrl3 = &pinctrl_fsys1;
26		pinctrl4 = &pinctrl_fsys2;
27		pinctrl5 = &pinctrl_peric0;
28		pinctrl6 = &pinctrl_peric1;
29	};
30
31	arm-pmu {
32		compatible = "arm,cortex-a76-pmu";
33		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
35			     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
36			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
37			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
38			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
39			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
40			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
41		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
42				     <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
43	};
44
45	cpus {
46		#address-cells = <1>;
47		#size-cells = <0>;
48
49		cpu-map {
50			cluster0 {
51				core0 {
52					cpu = <&cpu0>;
53				};
54				core1 {
55					cpu = <&cpu1>;
56				};
57				core2 {
58					cpu = <&cpu2>;
59				};
60				core3 {
61					cpu = <&cpu3>;
62				};
63			};
64
65			cluster1 {
66				core0 {
67					cpu = <&cpu4>;
68				};
69				core1 {
70					cpu = <&cpu5>;
71				};
72				core2 {
73					cpu = <&cpu6>;
74				};
75				core3 {
76					cpu = <&cpu7>;
77				};
78			};
79		};
80
81		cpu0: cpu@0 {
82			device_type = "cpu";
83			compatible = "arm,cortex-a76";
84			reg = <0x0>;
85			enable-method = "psci";
86		};
87
88		cpu1: cpu@100 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a76";
91			reg = <0x100>;
92			enable-method = "psci";
93		};
94
95		cpu2: cpu@200 {
96			device_type = "cpu";
97			compatible = "arm,cortex-a76";
98			reg = <0x200>;
99			enable-method = "psci";
100		};
101
102		cpu3: cpu@300 {
103			device_type = "cpu";
104			compatible = "arm,cortex-a76";
105			reg = <0x300>;
106			enable-method = "psci";
107		};
108
109		cpu4: cpu@10000 {
110			device_type = "cpu";
111			compatible = "arm,cortex-a76";
112			reg = <0x10000>;
113			enable-method = "psci";
114		};
115
116		cpu5: cpu@10100 {
117			device_type = "cpu";
118			compatible = "arm,cortex-a76";
119			reg = <0x10100>;
120			enable-method = "psci";
121		};
122
123		cpu6: cpu@10200 {
124			device_type = "cpu";
125			compatible = "arm,cortex-a76";
126			reg = <0x10200>;
127			enable-method = "psci";
128		};
129
130		cpu7: cpu@10300 {
131			device_type = "cpu";
132			compatible = "arm,cortex-a76";
133			reg = <0x10300>;
134			enable-method = "psci";
135		};
136	};
137
138	psci {
139		compatible = "arm,psci-1.0";
140		method = "smc";
141		cpu_suspend = <0xc4000001>;
142		cpu_off = <0x84000002>;
143		cpu_on = <0xc4000003>;
144	};
145
146	timer {
147		compatible = "arm,armv8-timer";
148		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
149			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
150			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
151			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
152	};
153
154	fixed-rate-clocks {
155		xtcxo: clock {
156			compatible = "fixed-clock";
157			#clock-cells = <0>;
158			clock-output-names = "oscclk";
159		};
160	};
161
162	soc: soc@0 {
163		compatible = "simple-bus";
164		#address-cells = <1>;
165		#size-cells = <1>;
166		ranges = <0x0 0x0 0x0 0x20000000>;
167
168		chipid@10000000 {
169			compatible = "samsung,exynos850-chipid";
170			reg = <0x10000000 0x24>;
171		};
172
173		cmu_peris: clock-controller@10020000 {
174			compatible = "samsung,exynosautov9-cmu-peris";
175			reg = <0x10020000 0x8000>;
176			#clock-cells = <1>;
177
178			clocks = <&xtcxo>,
179				 <&cmu_top DOUT_CLKCMU_PERIS_BUS>;
180			clock-names = "oscclk",
181				      "dout_clkcmu_peris_bus";
182		};
183
184		cmu_peric0: clock-controller@10200000 {
185			compatible = "samsung,exynosautov9-cmu-peric0";
186			reg = <0x10200000 0x8000>;
187			#clock-cells = <1>;
188
189			clocks = <&xtcxo>,
190				 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>,
191				 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
192			clock-names = "oscclk",
193				      "dout_clkcmu_peric0_bus",
194				      "dout_clkcmu_peric0_ip";
195		};
196
197		cmu_peric1: clock-controller@10800000 {
198			compatible = "samsung,exynosautov9-cmu-peric1";
199			reg = <0x10800000 0x8000>;
200			#clock-cells = <1>;
201
202			clocks = <&xtcxo>,
203				 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>,
204				 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
205			clock-names = "oscclk",
206				      "dout_clkcmu_peric1_bus",
207				      "dout_clkcmu_peric1_ip";
208		};
209
210		cmu_fsys1: clock-controller@17040000 {
211			compatible = "samsung,exynosautov9-cmu-fsys1";
212			reg = <0x17040000 0x8000>;
213			#clock-cells = <1>;
214
215			clocks = <&xtcxo>,
216				 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
217				 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
218				 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
219			clock-names = "oscclk",
220				      "dout_clkcmu_fsys1_bus",
221				      "gout_clkcmu_fsys1_mmc_card",
222				      "dout_clkcmu_fsys1_usbdrd";
223		};
224
225		cmu_fsys0: clock-controller@17700000 {
226			compatible = "samsung,exynosautov9-cmu-fsys0";
227			reg = <0x17700000 0x8000>;
228			#clock-cells = <1>;
229
230			clocks = <&xtcxo>,
231				 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
232				 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
233			clock-names = "oscclk",
234				      "dout_clkcmu_fsys0_bus",
235				      "dout_clkcmu_fsys0_pcie";
236		};
237
238		cmu_fsys2: clock-controller@17c00000 {
239			compatible = "samsung,exynosautov9-cmu-fsys2";
240			reg = <0x17c00000 0x8000>;
241			#clock-cells = <1>;
242
243			clocks = <&xtcxo>,
244				 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
245				 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
246				 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
247			clock-names = "oscclk",
248				      "dout_clkcmu_fsys2_bus",
249				      "dout_fsys2_clkcmu_ufs_embd",
250				      "dout_fsys2_clkcmu_ethernet";
251		};
252
253		cmu_core: clock-controller@1b030000 {
254			compatible = "samsung,exynosautov9-cmu-core";
255			reg = <0x1b030000 0x8000>;
256			#clock-cells = <1>;
257
258			clocks = <&xtcxo>,
259				 <&cmu_top DOUT_CLKCMU_CORE_BUS>;
260			clock-names = "oscclk",
261				      "dout_clkcmu_core_bus";
262		};
263
264		cmu_busmc: clock-controller@1b200000 {
265			compatible = "samsung,exynosautov9-cmu-busmc";
266			reg = <0x1b200000 0x8000>;
267			#clock-cells = <1>;
268
269			clocks = <&xtcxo>,
270				 <&cmu_top DOUT_CLKCMU_BUSMC_BUS>;
271			clock-names = "oscclk",
272				      "dout_clkcmu_busmc_bus";
273		};
274
275		cmu_top: clock-controller@1b240000 {
276			compatible = "samsung,exynosautov9-cmu-top";
277			reg = <0x1b240000 0x8000>;
278			#clock-cells = <1>;
279
280			clocks = <&xtcxo>;
281			clock-names = "oscclk";
282		};
283
284		gic: interrupt-controller@10101000 {
285			compatible = "arm,gic-400";
286			#interrupt-cells = <3>;
287			#address-cells = <0>;
288			interrupt-controller;
289			reg = <0x10101000 0x1000>,
290			      <0x10102000 0x2000>,
291			      <0x10104000 0x2000>,
292			      <0x10106000 0x2000>;
293			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
294						 IRQ_TYPE_LEVEL_HIGH)>;
295		};
296
297		pdma0: dma-controller@1b2e0000 {
298			compatible = "arm,pl330", "arm,primecell";
299			reg = <0x1b2e0000 0x1000>;
300			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
301			clocks = <&cmu_busmc CLK_GOUT_BUSMC_PDMA0_PCLK>;
302			clock-names = "apb_pclk";
303			arm,pl330-broken-no-flushp;
304			#dma-cells = <1>;
305		};
306
307		pinctrl_alive: pinctrl@10450000 {
308			compatible = "samsung,exynosautov9-pinctrl";
309			reg = <0x10450000 0x1000>;
310
311			wakeup-interrupt-controller {
312				compatible = "samsung,exynosautov9-wakeup-eint";
313			};
314		};
315
316		pinctrl_aud: pinctrl@19c60000 {
317			compatible = "samsung,exynosautov9-pinctrl";
318			reg = <0x19c60000 0x1000>;
319		};
320
321		pinctrl_fsys0: pinctrl@17740000 {
322			compatible = "samsung,exynosautov9-pinctrl";
323			reg = <0x17740000 0x1000>;
324			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
325		};
326
327		pinctrl_fsys1: pinctrl@17060000 {
328			compatible = "samsung,exynosautov9-pinctrl";
329			reg = <0x17060000 0x1000>;
330			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
331		};
332
333		pinctrl_fsys2: pinctrl@17c30000 {
334			compatible = "samsung,exynosautov9-pinctrl";
335			reg = <0x17c30000 0x1000>;
336			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
337		};
338
339		pinctrl_peric0: pinctrl@10230000 {
340			compatible = "samsung,exynosautov9-pinctrl";
341			reg = <0x10230000 0x1000>;
342			interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
343		};
344
345		pinctrl_peric1: pinctrl@10830000 {
346			compatible = "samsung,exynosautov9-pinctrl";
347			reg = <0x10830000 0x1000>;
348			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
349		};
350
351		pmu_system_controller: system-controller@10460000 {
352			compatible = "samsung,exynos7-pmu", "syscon";
353			reg = <0x10460000 0x10000>;
354
355			reboot: syscon-reboot {
356				compatible = "syscon-reboot";
357				regmap = <&pmu_system_controller>;
358				offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
359				value = <0x2>;
360				mask = <0x2>;
361			};
362
363			reboot-mode {
364				compatible = "syscon-reboot-mode";
365				offset = <0x810>; /* SYSIP_DAT0 */
366				mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>;
367				mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>;
368				mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>;
369			};
370		};
371
372		syscon_fsys2: syscon@17c20000 {
373			compatible = "samsung,exynosautov9-fsys2-sysreg",
374				     "samsung,exynosautov9-sysreg", "syscon";
375			reg = <0x17c20000 0x1000>;
376		};
377
378		syscon_peric0: syscon@10220000 {
379			compatible = "samsung,exynosautov9-peric0-sysreg",
380				     "samsung,exynosautov9-sysreg", "syscon";
381			reg = <0x10220000 0x2000>;
382		};
383
384		syscon_peric1: syscon@10820000 {
385			compatible = "samsung,exynosautov9-peric1-sysreg",
386				     "samsung,exynosautov9-sysreg", "syscon";
387			reg = <0x10820000 0x2000>;
388		};
389
390		usi_0: usi@103000c0 {
391			compatible = "samsung,exynosautov9-usi",
392				     "samsung,exynos850-usi";
393			reg = <0x103000c0 0x20>;
394			samsung,sysreg = <&syscon_peric0 0x1000>;
395			samsung,mode = <USI_V2_UART>;
396			#address-cells = <1>;
397			#size-cells = <1>;
398			ranges;
399			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
400				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
401			clock-names = "pclk", "ipclk";
402			status = "disabled";
403
404			serial_0: serial@10300000 {
405				compatible = "samsung,exynosautov9-uart",
406					     "samsung,exynos850-uart";
407				reg = <0x10300000 0xc0>;
408				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
409				pinctrl-names = "default";
410				pinctrl-0 = <&uart0_bus>;
411				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
412					 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
413				clock-names = "uart", "clk_uart_baud0";
414				samsung,uart-fifosize = <256>;
415				status = "disabled";
416			};
417
418			spi_0: spi@10300000 {
419				compatible = "samsung,exynosautov9-spi";
420				reg = <0x10300000 0x30>;
421				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
422				pinctrl-names = "default";
423				pinctrl-0 = <&spi0_bus &spi0_cs_func>;
424				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>,
425					 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>,
426					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>;
427				clock-names = "spi", "spi_busclk0", "spi_ioclk";
428				samsung,spi-src-clk = <0>;
429				dmas = <&pdma0 1>, <&pdma0 0>;
430				dma-names = "tx", "rx";
431				num-cs = <1>;
432				#address-cells = <1>;
433				#size-cells = <0>;
434				status = "disabled";
435			};
436
437			hsi2c_0: i2c@10300000 {
438				compatible = "samsung,exynosautov9-hsi2c";
439				reg = <0x10300000 0xc0>;
440				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
441				pinctrl-names = "default";
442				pinctrl-0 = <&hsi2c0_bus>;
443				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>,
444					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>;
445				clock-names = "hsi2c", "hsi2c_pclk";
446				#address-cells = <1>;
447				#size-cells = <0>;
448				status = "disabled";
449			};
450		};
451
452		usi_i2c_0: usi@103100c0 {
453			compatible = "samsung,exynosautov9-usi",
454				     "samsung,exynos850-usi";
455			reg = <0x103100c0 0x20>;
456			samsung,sysreg = <&syscon_peric0 0x1004>;
457			samsung,mode = <USI_V2_I2C>;
458			#address-cells = <1>;
459			#size-cells = <1>;
460			ranges;
461			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>,
462				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>;
463			clock-names = "pclk", "ipclk";
464			status = "disabled";
465
466			hsi2c_1: i2c@10310000 {
467				compatible = "samsung,exynosautov9-hsi2c";
468				reg = <0x10310000 0xc0>;
469				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
470				pinctrl-names = "default";
471				pinctrl-0 = <&hsi2c1_bus>;
472				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>,
473					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>;
474				clock-names = "hsi2c", "hsi2c_pclk";
475				#address-cells = <1>;
476				#size-cells = <0>;
477				status = "disabled";
478			};
479		};
480
481		usi_1: usi@103200c0 {
482			compatible = "samsung,exynosautov9-usi",
483				     "samsung,exynos850-usi";
484			reg = <0x103200c0 0x20>;
485			samsung,sysreg = <&syscon_peric0 0x1008>;
486			samsung,mode = <USI_V2_UART>;
487			#address-cells = <1>;
488			#size-cells = <1>;
489			ranges;
490			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>,
491				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>;
492			clock-names = "pclk", "ipclk";
493			status = "disabled";
494
495			serial_1: serial@10320000 {
496				compatible = "samsung,exynosautov9-uart",
497					     "samsung,exynos850-uart";
498				reg = <0x10320000 0xc0>;
499				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
500				pinctrl-names = "default";
501				pinctrl-0 = <&uart1_bus>;
502				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>,
503					 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>;
504				clock-names = "uart", "clk_uart_baud0";
505				samsung,uart-fifosize = <256>;
506				status = "disabled";
507			};
508
509			spi_1: spi@10320000 {
510				compatible = "samsung,exynosautov9-spi";
511				reg = <0x10320000 0x30>;
512				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
513				pinctrl-names = "default";
514				pinctrl-0 = <&spi1_bus &spi1_cs_func>;
515				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>,
516					 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>,
517					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>;
518				clock-names = "spi", "spi_busclk0", "spi_ioclk";
519				samsung,spi-src-clk = <0>;
520				dmas = <&pdma0 3>, <&pdma0 2>;
521				dma-names = "tx", "rx";
522				num-cs = <1>;
523				#address-cells = <1>;
524				#size-cells = <0>;
525				status = "disabled";
526			};
527
528			hsi2c_2: i2c@10320000 {
529				compatible = "samsung,exynosautov9-hsi2c";
530				reg = <0x10320000 0xc0>;
531				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
532				pinctrl-names = "default";
533				pinctrl-0 = <&hsi2c2_bus>;
534				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>,
535					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>;
536				clock-names = "hsi2c", "hsi2c_pclk";
537				#address-cells = <1>;
538				#size-cells = <0>;
539				status = "disabled";
540			};
541		};
542
543		usi_i2c_1: usi@103300c0 {
544			compatible = "samsung,exynosautov9-usi",
545				     "samsung,exynos850-usi";
546			reg = <0x103300c0 0x20>;
547			samsung,sysreg = <&syscon_peric0 0x100c>;
548			samsung,mode = <USI_V2_I2C>;
549			#address-cells = <1>;
550			#size-cells = <1>;
551			ranges;
552			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>,
553				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>;
554			clock-names = "pclk", "ipclk";
555			status = "disabled";
556
557			hsi2c_3: i2c@10330000 {
558				compatible = "samsung,exynosautov9-hsi2c";
559				reg = <0x10330000 0xc0>;
560				interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
561				pinctrl-names = "default";
562				pinctrl-0 = <&hsi2c3_bus>;
563				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>,
564					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>;
565				clock-names = "hsi2c", "hsi2c_pclk";
566				#address-cells = <1>;
567				#size-cells = <0>;
568				status = "disabled";
569			};
570		};
571
572		usi_2: usi@103400c0 {
573			compatible = "samsung,exynosautov9-usi",
574				     "samsung,exynos850-usi";
575			reg = <0x103400c0 0x20>;
576			samsung,sysreg = <&syscon_peric0 0x1010>;
577			samsung,mode = <USI_V2_UART>;
578			#address-cells = <1>;
579			#size-cells = <1>;
580			ranges;
581			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>,
582				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>;
583			clock-names = "pclk", "ipclk";
584			status = "disabled";
585
586			serial_2: serial@10340000 {
587				compatible = "samsung,exynosautov9-uart",
588					     "samsung,exynos850-uart";
589				reg = <0x10340000 0xc0>;
590				interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
591				pinctrl-names = "default";
592				pinctrl-0 = <&uart2_bus>;
593				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>,
594					 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>;
595				clock-names = "uart", "clk_uart_baud0";
596				samsung,uart-fifosize = <64>;
597				status = "disabled";
598			};
599
600			spi_2: spi@10340000 {
601				compatible = "samsung,exynosautov9-spi";
602				reg = <0x10340000 0x30>;
603				interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
604				pinctrl-names = "default";
605				pinctrl-0 = <&spi2_bus &spi2_cs_func>;
606				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>,
607					 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>,
608					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>;
609				clock-names = "spi", "spi_busclk0", "spi_ioclk";
610				samsung,spi-src-clk = <0>;
611				dmas = <&pdma0 5>, <&pdma0 4>;
612				dma-names = "tx", "rx";
613				num-cs = <1>;
614				#address-cells = <1>;
615				#size-cells = <0>;
616				status = "disabled";
617			};
618
619			hsi2c_4: i2c@10340000 {
620				compatible = "samsung,exynosautov9-hsi2c";
621				reg = <0x10340000 0xc0>;
622				interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
623				pinctrl-names = "default";
624				pinctrl-0 = <&hsi2c4_bus>;
625				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>,
626					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>;
627				clock-names = "hsi2c", "hsi2c_pclk";
628				#address-cells = <1>;
629				#size-cells = <0>;
630				status = "disabled";
631			};
632		};
633
634		usi_i2c_2: usi@103500c0 {
635			compatible = "samsung,exynosautov9-usi",
636				     "samsung,exynos850-usi";
637			reg = <0x103500c0 0x20>;
638			samsung,sysreg = <&syscon_peric0 0x1014>;
639			samsung,mode = <USI_V2_I2C>;
640			#address-cells = <1>;
641			#size-cells = <1>;
642			ranges;
643			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>,
644				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>;
645			clock-names = "pclk", "ipclk";
646			status = "disabled";
647
648			hsi2c_5: i2c@10350000 {
649				compatible = "samsung,exynosautov9-hsi2c";
650				reg = <0x10350000 0xc0>;
651				interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
652				pinctrl-names = "default";
653				pinctrl-0 = <&hsi2c5_bus>;
654				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>,
655					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>;
656				clock-names = "hsi2c", "hsi2c_pclk";
657				#address-cells = <1>;
658				#size-cells = <0>;
659				status = "disabled";
660			};
661		};
662
663		usi_3: usi@103600c0 {
664			compatible = "samsung,exynosautov9-usi",
665				     "samsung,exynos850-usi";
666			reg = <0x103600c0 0x20>;
667			samsung,sysreg = <&syscon_peric0 0x1018>;
668			samsung,mode = <USI_V2_UART>;
669			#address-cells = <1>;
670			#size-cells = <1>;
671			ranges;
672			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>,
673				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>;
674			clock-names = "pclk", "ipclk";
675			status = "disabled";
676
677			serial_3: serial@10360000 {
678				compatible = "samsung,exynosautov9-uart",
679					     "samsung,exynos850-uart";
680				reg = <0x10360000 0xc0>;
681				interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
682				pinctrl-names = "default";
683				pinctrl-0 = <&uart3_bus>;
684				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>,
685					 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>;
686				clock-names = "uart", "clk_uart_baud0";
687				samsung,uart-fifosize = <64>;
688				status = "disabled";
689			};
690
691			spi_3: spi@10360000 {
692				compatible = "samsung,exynosautov9-spi";
693				reg = <0x10360000 0x30>;
694				interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
695				pinctrl-names = "default";
696				pinctrl-0 = <&spi3_bus &spi3_cs_func>;
697				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>,
698					 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>,
699					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>;
700				clock-names = "spi", "spi_busclk0", "spi_ioclk";
701				samsung,spi-src-clk = <0>;
702				dmas = <&pdma0 7>, <&pdma0 6>;
703				dma-names = "tx", "rx";
704				num-cs = <1>;
705				#address-cells = <1>;
706				#size-cells = <0>;
707				status = "disabled";
708			};
709
710			hsi2c_6: i2c@10360000 {
711				compatible = "samsung,exynosautov9-hsi2c";
712				reg = <0x10360000 0xc0>;
713				interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
714				pinctrl-names = "default";
715				pinctrl-0 = <&hsi2c6_bus>;
716				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>,
717					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>;
718				clock-names = "hsi2c", "hsi2c_pclk";
719				#address-cells = <1>;
720				#size-cells = <0>;
721				status = "disabled";
722			};
723		};
724
725		usi_i2c_3: usi@103700c0 {
726			compatible = "samsung,exynosautov9-usi",
727				     "samsung,exynos850-usi";
728			reg = <0x103700c0 0x20>;
729			samsung,sysreg = <&syscon_peric0 0x101c>;
730			samsung,mode = <USI_V2_I2C>;
731			#address-cells = <1>;
732			#size-cells = <1>;
733			ranges;
734			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>,
735				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>;
736			clock-names = "pclk", "ipclk";
737			status = "disabled";
738
739			hsi2c_7: i2c@10370000 {
740				compatible = "samsung,exynosautov9-hsi2c";
741				reg = <0x10370000 0xc0>;
742				interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
743				pinctrl-names = "default";
744				pinctrl-0 = <&hsi2c7_bus>;
745				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>,
746					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>;
747				clock-names = "hsi2c", "hsi2c_pclk";
748				#address-cells = <1>;
749				#size-cells = <0>;
750				status = "disabled";
751			};
752		};
753
754		usi_4: usi@103800c0 {
755			compatible = "samsung,exynosautov9-usi",
756				     "samsung,exynos850-usi";
757			reg = <0x103800c0 0x20>;
758			samsung,sysreg = <&syscon_peric0 0x1020>;
759			samsung,mode = <USI_V2_UART>;
760			#address-cells = <1>;
761			#size-cells = <1>;
762			ranges;
763			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>,
764				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>;
765			clock-names = "pclk", "ipclk";
766			status = "disabled";
767
768			serial_4: serial@10380000 {
769				compatible = "samsung,exynosautov9-uart",
770					     "samsung,exynos850-uart";
771				reg = <0x10380000 0xc0>;
772				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
773				pinctrl-names = "default";
774				pinctrl-0 = <&uart4_bus>;
775				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>,
776					 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>;
777				clock-names = "uart", "clk_uart_baud0";
778				samsung,uart-fifosize = <64>;
779				status = "disabled";
780			};
781
782			spi_4: spi@10380000 {
783				compatible = "samsung,exynosautov9-spi";
784				reg = <0x10380000 0x30>;
785				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
786				pinctrl-names = "default";
787				pinctrl-0 = <&spi4_bus &spi4_cs_func>;
788				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>,
789					 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>,
790					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>;
791				clock-names = "spi", "spi_busclk0", "spi_ioclk";
792				samsung,spi-src-clk = <0>;
793				dmas = <&pdma0 9>, <&pdma0 8>;
794				dma-names = "tx", "rx";
795				num-cs = <1>;
796				#address-cells = <1>;
797				#size-cells = <0>;
798				status = "disabled";
799			};
800
801			hsi2c_8: i2c@10380000 {
802				compatible = "samsung,exynosautov9-hsi2c";
803				reg = <0x10380000 0xc0>;
804				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
805				pinctrl-names = "default";
806				pinctrl-0 = <&hsi2c8_bus>;
807				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>,
808					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>;
809				clock-names = "hsi2c", "hsi2c_pclk";
810				#address-cells = <1>;
811				#size-cells = <0>;
812				status = "disabled";
813			};
814		};
815
816		usi_i2c_4: usi@103900c0 {
817			compatible = "samsung,exynosautov9-usi",
818				     "samsung,exynos850-usi";
819			reg = <0x103900c0 0x20>;
820			samsung,sysreg = <&syscon_peric0 0x1024>;
821			samsung,mode = <USI_V2_I2C>;
822			#address-cells = <1>;
823			#size-cells = <1>;
824			ranges;
825			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>,
826				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>;
827			clock-names = "pclk", "ipclk";
828			status = "disabled";
829
830			hsi2c_9: i2c@10390000 {
831				compatible = "samsung,exynosautov9-hsi2c";
832				reg = <0x10390000 0xc0>;
833				interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
834				pinctrl-names = "default";
835				pinctrl-0 = <&hsi2c9_bus>;
836				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>,
837					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>;
838				clock-names = "hsi2c", "hsi2c_pclk";
839				#address-cells = <1>;
840				#size-cells = <0>;
841				status = "disabled";
842			};
843		};
844
845		usi_5: usi@103a00c0 {
846			compatible = "samsung,exynosautov9-usi",
847				     "samsung,exynos850-usi";
848			reg = <0x103a00c0 0x20>;
849			samsung,sysreg = <&syscon_peric0 0x1028>;
850			samsung,mode = <USI_V2_UART>;
851			#address-cells = <1>;
852			#size-cells = <1>;
853			ranges;
854			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>,
855				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>;
856			clock-names = "pclk", "ipclk";
857			status = "disabled";
858
859			serial_5: serial@103a0000 {
860				compatible = "samsung,exynosautov9-uart",
861					     "samsung,exynos850-uart";
862				reg = <0x103a0000 0xc0>;
863				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
864				pinctrl-names = "default";
865				pinctrl-0 = <&uart5_bus>;
866				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>,
867					 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>;
868				clock-names = "uart", "clk_uart_baud0";
869				samsung,uart-fifosize = <64>;
870				status = "disabled";
871			};
872
873			spi_5: spi@103a0000 {
874				compatible = "samsung,exynosautov9-spi";
875				reg = <0x103a0000 0x30>;
876				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
877				pinctrl-names = "default";
878				pinctrl-0 = <&spi5_bus &spi5_cs_func>;
879				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>,
880					 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>,
881					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>;
882				clock-names = "spi", "spi_busclk0", "spi_ioclk";
883				samsung,spi-src-clk = <0>;
884				dmas = <&pdma0 11>, <&pdma0 10>;
885				dma-names = "tx", "rx";
886				num-cs = <1>;
887				#address-cells = <1>;
888				#size-cells = <0>;
889				status = "disabled";
890			};
891
892			hsi2c_10: i2c@103a0000 {
893				compatible = "samsung,exynosautov9-hsi2c";
894				reg = <0x103a0000 0xc0>;
895				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
896				pinctrl-names = "default";
897				pinctrl-0 = <&hsi2c10_bus>;
898				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>,
899					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>;
900				clock-names = "hsi2c", "hsi2c_pclk";
901				#address-cells = <1>;
902				#size-cells = <0>;
903				status = "disabled";
904			};
905		};
906
907		usi_i2c_5: usi@103b00c0 {
908			compatible = "samsung,exynosautov9-usi",
909				     "samsung,exynos850-usi";
910			reg = <0x103b00c0 0x20>;
911			samsung,sysreg = <&syscon_peric0 0x102c>;
912			samsung,mode = <USI_V2_I2C>;
913			#address-cells = <1>;
914			#size-cells = <1>;
915			ranges;
916			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>,
917				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>;
918			clock-names = "pclk", "ipclk";
919			status = "disabled";
920
921			hsi2c_11: i2c@103b0000 {
922				compatible = "samsung,exynosautov9-hsi2c";
923				reg = <0x103b0000 0xc0>;
924				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
925				pinctrl-names = "default";
926				pinctrl-0 = <&hsi2c11_bus>;
927				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>,
928					 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>;
929				clock-names = "hsi2c", "hsi2c_pclk";
930				#address-cells = <1>;
931				#size-cells = <0>;
932				status = "disabled";
933			};
934		};
935
936		usi_6: usi@109000c0 {
937			compatible = "samsung,exynosautov9-usi",
938				     "samsung,exynos850-usi";
939			reg = <0x109000c0 0x20>;
940			samsung,sysreg = <&syscon_peric1 0x1000>;
941			samsung,mode = <USI_V2_UART>;
942			#address-cells = <1>;
943			#size-cells = <1>;
944			ranges;
945			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>,
946				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>;
947			clock-names = "pclk", "ipclk";
948			status = "disabled";
949
950			serial_6: serial@10900000 {
951				compatible = "samsung,exynosautov9-uart",
952					     "samsung,exynos850-uart";
953				reg = <0x10900000 0xc0>;
954				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
955				pinctrl-names = "default";
956				pinctrl-0 = <&uart6_bus>;
957				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>,
958					 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>;
959				clock-names = "uart", "clk_uart_baud0";
960				samsung,uart-fifosize = <256>;
961				status = "disabled";
962			};
963
964			spi_6: spi@10900000 {
965				compatible = "samsung,exynosautov9-spi";
966				reg = <0x10900000 0x30>;
967				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
968				pinctrl-names = "default";
969				pinctrl-0 = <&spi6_bus &spi6_cs_func>;
970				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>,
971					 <&cmu_peric1 CLK_DOUT_PERIC1_USI06_USI>,
972					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>;
973				clock-names = "spi", "spi_busclk0", "spi_ioclk";
974				samsung,spi-src-clk = <0>;
975				dmas = <&pdma0 13>, <&pdma0 12>;
976				dma-names = "tx", "rx";
977				num-cs = <1>;
978				#address-cells = <1>;
979				#size-cells = <0>;
980				status = "disabled";
981			};
982
983			hsi2c_12: i2c@10900000 {
984				compatible = "samsung,exynosautov9-hsi2c";
985				reg = <0x10900000 0xc0>;
986				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
987				pinctrl-names = "default";
988				pinctrl-0 = <&hsi2c12_bus>;
989				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>,
990					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>;
991				clock-names = "hsi2c", "hsi2c_pclk";
992				#address-cells = <1>;
993				#size-cells = <0>;
994				status = "disabled";
995			};
996		};
997
998		usi_i2c_6: usi@109100c0 {
999			compatible = "samsung,exynosautov9-usi",
1000				     "samsung,exynos850-usi";
1001			reg = <0x109100c0 0x20>;
1002			samsung,sysreg = <&syscon_peric1 0x1004>;
1003			samsung,mode = <USI_V2_I2C>;
1004			#address-cells = <1>;
1005			#size-cells = <1>;
1006			ranges;
1007			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>,
1008				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>;
1009			clock-names = "pclk", "ipclk";
1010			status = "disabled";
1011
1012			hsi2c_13: i2c@10910000 {
1013				compatible = "samsung,exynosautov9-hsi2c";
1014				reg = <0x10910000 0xc0>;
1015				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1016				pinctrl-names = "default";
1017				pinctrl-0 = <&hsi2c13_bus>;
1018				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>,
1019					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>;
1020				clock-names = "hsi2c", "hsi2c_pclk";
1021				#address-cells = <1>;
1022				#size-cells = <0>;
1023				status = "disabled";
1024			};
1025		};
1026
1027		usi_7: usi@109200c0 {
1028			compatible = "samsung,exynosautov9-usi",
1029				     "samsung,exynos850-usi";
1030			reg = <0x109200c0 0x20>;
1031			samsung,sysreg = <&syscon_peric1 0x1008>;
1032			samsung,mode = <USI_V2_UART>;
1033			#address-cells = <1>;
1034			#size-cells = <1>;
1035			ranges;
1036			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>,
1037				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>;
1038			clock-names = "pclk", "ipclk";
1039			status = "disabled";
1040
1041			serial_7: serial@10920000 {
1042				compatible = "samsung,exynosautov9-uart",
1043					     "samsung,exynos850-uart";
1044				reg = <0x10920000 0xc0>;
1045				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1046				pinctrl-names = "default";
1047				pinctrl-0 = <&uart7_bus>;
1048				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>,
1049					 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>;
1050				clock-names = "uart", "clk_uart_baud0";
1051				samsung,uart-fifosize = <64>;
1052				status = "disabled";
1053			};
1054
1055			spi_7: spi@10920000 {
1056				compatible = "samsung,exynosautov9-spi";
1057				reg = <0x10920000 0x30>;
1058				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1059				pinctrl-names = "default";
1060				pinctrl-0 = <&spi7_bus &spi7_cs_func>;
1061				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>,
1062					 <&cmu_peric1 CLK_DOUT_PERIC1_USI07_USI>,
1063					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>;
1064				clock-names = "spi", "spi_busclk0", "spi_ioclk";
1065				samsung,spi-src-clk = <0>;
1066				dmas = <&pdma0 15>, <&pdma0 14>;
1067				dma-names = "tx", "rx";
1068				num-cs = <1>;
1069				#address-cells = <1>;
1070				#size-cells = <0>;
1071				status = "disabled";
1072			};
1073
1074			hsi2c_14: i2c@10920000 {
1075				compatible = "samsung,exynosautov9-hsi2c";
1076				reg = <0x10920000 0xc0>;
1077				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1078				pinctrl-names = "default";
1079				pinctrl-0 = <&hsi2c14_bus>;
1080				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>,
1081					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>;
1082				clock-names = "hsi2c", "hsi2c_pclk";
1083				#address-cells = <1>;
1084				#size-cells = <0>;
1085				status = "disabled";
1086			};
1087		};
1088
1089		usi_i2c_7: usi@109300c0 {
1090			compatible = "samsung,exynosautov9-usi",
1091				     "samsung,exynos850-usi";
1092			reg = <0x109300c0 0x20>;
1093			samsung,sysreg = <&syscon_peric1 0x100c>;
1094			samsung,mode = <USI_V2_I2C>;
1095			#address-cells = <1>;
1096			#size-cells = <1>;
1097			ranges;
1098			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>,
1099				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>;
1100			clock-names = "pclk", "ipclk";
1101			status = "disabled";
1102
1103			hsi2c_15: i2c@10930000 {
1104				compatible = "samsung,exynosautov9-hsi2c";
1105				reg = <0x10930000 0xc0>;
1106				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1107				pinctrl-names = "default";
1108				pinctrl-0 = <&hsi2c15_bus>;
1109				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>,
1110					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>;
1111				clock-names = "hsi2c", "hsi2c_pclk";
1112				#address-cells = <1>;
1113				#size-cells = <0>;
1114				status = "disabled";
1115			};
1116		};
1117
1118		usi_8: usi@109400c0 {
1119			compatible = "samsung,exynosautov9-usi",
1120				     "samsung,exynos850-usi";
1121			reg = <0x109400c0 0x20>;
1122			samsung,sysreg = <&syscon_peric1 0x1010>;
1123			samsung,mode = <USI_V2_UART>;
1124			#address-cells = <1>;
1125			#size-cells = <1>;
1126			ranges;
1127			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>,
1128				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>;
1129			clock-names = "pclk", "ipclk";
1130			status = "disabled";
1131
1132			serial_8: serial@10940000 {
1133				compatible = "samsung,exynosautov9-uart",
1134					     "samsung,exynos850-uart";
1135				reg = <0x10940000 0xc0>;
1136				interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>;
1137				pinctrl-names = "default";
1138				pinctrl-0 = <&uart8_bus>;
1139				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>,
1140					 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>;
1141				clock-names = "uart", "clk_uart_baud0";
1142				samsung,uart-fifosize = <64>;
1143				status = "disabled";
1144			};
1145
1146			spi_8: spi@10940000 {
1147				compatible = "samsung,exynosautov9-spi";
1148				reg = <0x10940000 0x30>;
1149				interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>;
1150				pinctrl-names = "default";
1151				pinctrl-0 = <&spi8_bus &spi8_cs_func>;
1152				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>,
1153					 <&cmu_peric1 CLK_DOUT_PERIC1_USI08_USI>,
1154					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>;
1155				clock-names = "spi", "spi_busclk0", "spi_ioclk";
1156				samsung,spi-src-clk = <0>;
1157				dmas = <&pdma0 17>, <&pdma0 16>;
1158				dma-names = "tx", "rx";
1159				num-cs = <1>;
1160				#address-cells = <1>;
1161				#size-cells = <0>;
1162				status = "disabled";
1163			};
1164
1165			hsi2c_16: i2c@10940000 {
1166				compatible = "samsung,exynosautov9-hsi2c";
1167				reg = <0x10940000 0xc0>;
1168				interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>;
1169				pinctrl-names = "default";
1170				pinctrl-0 = <&hsi2c16_bus>;
1171				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>,
1172					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>;
1173				clock-names = "hsi2c", "hsi2c_pclk";
1174				#address-cells = <1>;
1175				#size-cells = <0>;
1176				status = "disabled";
1177			};
1178		};
1179
1180		usi_i2c_8: usi@109500c0 {
1181			compatible = "samsung,exynosautov9-usi",
1182				     "samsung,exynos850-usi";
1183			reg = <0x109500c0 0x20>;
1184			samsung,sysreg = <&syscon_peric1 0x1014>;
1185			samsung,mode = <USI_V2_I2C>;
1186			#address-cells = <1>;
1187			#size-cells = <1>;
1188			ranges;
1189			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>,
1190				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>;
1191			clock-names = "pclk", "ipclk";
1192			status = "disabled";
1193
1194			hsi2c_17: i2c@10950000 {
1195				compatible = "samsung,exynosautov9-hsi2c";
1196				reg = <0x10950000 0xc0>;
1197				interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1198				pinctrl-names = "default";
1199				pinctrl-0 = <&hsi2c17_bus>;
1200				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>,
1201					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>;
1202				clock-names = "hsi2c", "hsi2c_pclk";
1203				#address-cells = <1>;
1204				#size-cells = <0>;
1205				status = "disabled";
1206			};
1207		};
1208
1209		usi_9: usi@109600c0 {
1210			compatible = "samsung,exynosautov9-usi",
1211				     "samsung,exynos850-usi";
1212			reg = <0x109600c0 0x20>;
1213			samsung,sysreg = <&syscon_peric1 0x1018>;
1214			samsung,mode = <USI_V2_UART>;
1215			#address-cells = <1>;
1216			#size-cells = <1>;
1217			ranges;
1218			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>,
1219				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>;
1220			clock-names = "pclk", "ipclk";
1221			status = "disabled";
1222
1223			serial_9: serial@10960000 {
1224				compatible = "samsung,exynosautov9-uart",
1225					     "samsung,exynos850-uart";
1226				reg = <0x10960000 0xc0>;
1227				interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>;
1228				pinctrl-names = "default";
1229				pinctrl-0 = <&uart9_bus>;
1230				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>,
1231					 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>;
1232				clock-names = "uart", "clk_uart_baud0";
1233				samsung,uart-fifosize = <64>;
1234				status = "disabled";
1235			};
1236
1237			spi_9: spi@10960000 {
1238				compatible = "samsung,exynosautov9-spi";
1239				reg = <0x10960000 0x30>;
1240				interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>;
1241				pinctrl-names = "default";
1242				pinctrl-0 = <&spi9_bus &spi9_cs_func>;
1243				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>,
1244					 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>,
1245					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>;
1246				clock-names = "spi", "spi_busclk0", "spi_ioclk";
1247				samsung,spi-src-clk = <0>;
1248				dmas = <&pdma0 19>, <&pdma0 18>;
1249				dma-names = "tx", "rx";
1250				num-cs = <1>;
1251				#address-cells = <1>;
1252				#size-cells = <0>;
1253				status = "disabled";
1254			};
1255
1256			hsi2c_18: i2c@10960000 {
1257				compatible = "samsung,exynosautov9-hsi2c";
1258				reg = <0x10960000 0xc0>;
1259				interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>;
1260				pinctrl-names = "default";
1261				pinctrl-0 = <&hsi2c18_bus>;
1262				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>,
1263					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>;
1264				clock-names = "hsi2c", "hsi2c_pclk";
1265				#address-cells = <1>;
1266				#size-cells = <0>;
1267				status = "disabled";
1268			};
1269		};
1270
1271		usi_i2c_9: usi@109700c0 {
1272			compatible = "samsung,exynosautov9-usi",
1273				     "samsung,exynos850-usi";
1274			reg = <0x109700c0 0x20>;
1275			samsung,sysreg = <&syscon_peric1 0x101c>;
1276			samsung,mode = <USI_V2_I2C>;
1277			#address-cells = <1>;
1278			#size-cells = <1>;
1279			ranges;
1280			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>,
1281				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>;
1282			clock-names = "pclk", "ipclk";
1283			status = "disabled";
1284
1285			hsi2c_19: i2c@10970000 {
1286				compatible = "samsung,exynosautov9-hsi2c";
1287				reg = <0x10970000 0xc0>;
1288				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1289				pinctrl-names = "default";
1290				pinctrl-0 = <&hsi2c19_bus>;
1291				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>,
1292					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>;
1293				clock-names = "hsi2c", "hsi2c_pclk";
1294				#address-cells = <1>;
1295				#size-cells = <0>;
1296				status = "disabled";
1297			};
1298		};
1299
1300		usi_10: usi@109800c0 {
1301			compatible = "samsung,exynosautov9-usi",
1302				     "samsung,exynos850-usi";
1303			reg = <0x109800c0 0x20>;
1304			samsung,sysreg = <&syscon_peric1 0x1020>;
1305			samsung,mode = <USI_V2_UART>;
1306			#address-cells = <1>;
1307			#size-cells = <1>;
1308			ranges;
1309			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>,
1310				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>;
1311			clock-names = "pclk", "ipclk";
1312			status = "disabled";
1313
1314			serial_10: serial@10980000 {
1315				compatible = "samsung,exynosautov9-uart",
1316					     "samsung,exynos850-uart";
1317				reg = <0x10980000 0xc0>;
1318				interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
1319				pinctrl-names = "default";
1320				pinctrl-0 = <&uart10_bus>;
1321				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>,
1322					 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>;
1323				clock-names = "uart", "clk_uart_baud0";
1324				samsung,uart-fifosize = <64>;
1325				status = "disabled";
1326			};
1327
1328			spi_10: spi@10980000 {
1329				compatible = "samsung,exynosautov9-spi";
1330				reg = <0x10980000 0x30>;
1331				interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
1332				pinctrl-names = "default";
1333				pinctrl-0 = <&spi10_bus &spi10_cs_func>;
1334				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>,
1335					 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>,
1336					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>;
1337				clock-names = "spi", "spi_busclk0", "spi_ioclk";
1338				samsung,spi-src-clk = <0>;
1339				dmas = <&pdma0 21>, <&pdma0 20>;
1340				dma-names = "tx", "rx";
1341				num-cs = <1>;
1342				#address-cells = <1>;
1343				#size-cells = <0>;
1344				status = "disabled";
1345			};
1346
1347			hsi2c_20: i2c@10980000 {
1348				compatible = "samsung,exynosautov9-hsi2c";
1349				reg = <0x10980000 0xc0>;
1350				interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
1351				pinctrl-names = "default";
1352				pinctrl-0 = <&hsi2c20_bus>;
1353				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>,
1354					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>;
1355				clock-names = "hsi2c", "hsi2c_pclk";
1356				#address-cells = <1>;
1357				#size-cells = <0>;
1358				status = "disabled";
1359			};
1360		};
1361
1362		usi_i2c_10: usi@109900c0 {
1363			compatible = "samsung,exynosautov9-usi",
1364				     "samsung,exynos850-usi";
1365			reg = <0x109900c0 0x20>;
1366			samsung,sysreg = <&syscon_peric1 0x1024>;
1367			samsung,mode = <USI_V2_I2C>;
1368			#address-cells = <1>;
1369			#size-cells = <1>;
1370			ranges;
1371			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>,
1372				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>;
1373			clock-names = "pclk", "ipclk";
1374			status = "disabled";
1375
1376			hsi2c_21: i2c@10990000 {
1377				compatible = "samsung,exynosautov9-hsi2c";
1378				reg = <0x10990000 0xc0>;
1379				interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
1380				pinctrl-names = "default";
1381				pinctrl-0 = <&hsi2c21_bus>;
1382				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>,
1383					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>;
1384				clock-names = "hsi2c", "hsi2c_pclk";
1385				#address-cells = <1>;
1386				#size-cells = <0>;
1387				status = "disabled";
1388			};
1389		};
1390
1391		usi_11: usi@109a00c0 {
1392			compatible = "samsung,exynosautov9-usi",
1393				     "samsung,exynos850-usi";
1394			reg = <0x109a00c0 0x20>;
1395			samsung,sysreg = <&syscon_peric1 0x1028>;
1396			samsung,mode = <USI_V2_UART>;
1397			#address-cells = <1>;
1398			#size-cells = <1>;
1399			ranges;
1400			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>,
1401				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>;
1402			clock-names = "pclk", "ipclk";
1403			status = "disabled";
1404
1405			serial_11: serial@109a0000 {
1406				compatible = "samsung,exynosautov9-uart",
1407					     "samsung,exynos850-uart";
1408				reg = <0x109a0000 0xc0>;
1409				interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1410				pinctrl-names = "default";
1411				pinctrl-0 = <&uart11_bus>;
1412				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>,
1413					 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>;
1414				clock-names = "uart", "clk_uart_baud0";
1415				samsung,uart-fifosize = <64>;
1416				status = "disabled";
1417			};
1418
1419			spi_11: spi@109a0000 {
1420				compatible = "samsung,exynosautov9-spi";
1421				reg = <0x109a0000 0x30>;
1422				interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1423				pinctrl-names = "default";
1424				pinctrl-0 = <&spi11_bus &spi11_cs_func>;
1425				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>,
1426					 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>,
1427					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>;
1428				clock-names = "spi", "spi_busclk0", "spi_ioclk";
1429				samsung,spi-src-clk = <0>;
1430				num-cs = <1>;
1431				#address-cells = <1>;
1432				#size-cells = <0>;
1433				status = "disabled";
1434			};
1435
1436			hsi2c_22: i2c@109a0000 {
1437				compatible = "samsung,exynosautov9-hsi2c";
1438				reg = <0x109a0000 0xc0>;
1439				pinctrl-names = "default";
1440				pinctrl-0 = <&hsi2c22_bus>;
1441				interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1442				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>,
1443					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>;
1444				clock-names = "hsi2c", "hsi2c_pclk";
1445				#address-cells = <1>;
1446				#size-cells = <0>;
1447				status = "disabled";
1448			};
1449		};
1450
1451		usi_i2c_11: usi@109b00c0 {
1452			compatible = "samsung,exynosautov9-usi",
1453				     "samsung,exynos850-usi";
1454			reg = <0x109b00c0 0x20>;
1455			samsung,sysreg = <&syscon_peric1 0x102c>;
1456			samsung,mode = <USI_V2_I2C>;
1457			#address-cells = <1>;
1458			#size-cells = <1>;
1459			ranges;
1460			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>,
1461				 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>;
1462			clock-names = "pclk", "ipclk";
1463			status = "disabled";
1464
1465			hsi2c_23: i2c@109b0000 {
1466				compatible = "samsung,exynosautov9-hsi2c";
1467				reg = <0x109b0000 0xc0>;
1468				interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
1469				pinctrl-names = "default";
1470				pinctrl-0 = <&hsi2c23_bus>;
1471				clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>,
1472					 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>;
1473				clock-names = "hsi2c", "hsi2c_pclk";
1474				#address-cells = <1>;
1475				#size-cells = <0>;
1476				status = "disabled";
1477			};
1478		};
1479
1480		ufs_0_phy: phy@17e04000 {
1481			compatible = "samsung,exynosautov9-ufs-phy";
1482			reg = <0x17e04000 0xc00>;
1483			reg-names = "phy-pma";
1484			samsung,pmu-syscon = <&pmu_system_controller>;
1485			#phy-cells = <0>;
1486			clocks = <&xtcxo>;
1487			clock-names = "ref_clk";
1488			status = "disabled";
1489		};
1490
1491		ufs_0: ufs@17e00000 {
1492			compatible = "samsung,exynosautov9-ufs";
1493
1494			reg = <0x17e00000 0x100>,
1495			      <0x17e01100 0x410>,
1496			      <0x17e80000 0x8000>,
1497			      <0x17dc0000 0x2200>;
1498			reg-names = "hci", "vs_hci", "unipro", "ufsp";
1499			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1500			clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>,
1501				 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>;
1502			clock-names = "core_clk", "sclk_unipro_main";
1503			freq-table-hz = <0 0>, <0 0>;
1504			pinctrl-names = "default";
1505			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
1506			phys = <&ufs_0_phy>;
1507			phy-names = "ufs-phy";
1508			samsung,sysreg = <&syscon_fsys2 0x710>;
1509			status = "disabled";
1510		};
1511
1512		ufs_1_phy: phy@17f04000 {
1513			compatible = "samsung,exynosautov9-ufs-phy";
1514			reg = <0x17f04000 0xc00>;
1515			reg-names = "phy-pma";
1516			samsung,pmu-syscon = <&pmu_system_controller 0x72c>;
1517			#phy-cells = <0>;
1518			clocks = <&xtcxo>;
1519			clock-names = "ref_clk";
1520			status = "disabled";
1521		};
1522
1523		ufs_1: ufs@17f00000 {
1524			compatible = "samsung,exynosautov9-ufs";
1525
1526			reg = <0x17f00000 0x100>,
1527			      <0x17f01100 0x410>,
1528			      <0x17f80000 0x8000>,
1529			      <0x17de0000 0x2200>;
1530			reg-names = "hci", "vs_hci", "unipro", "ufsp";
1531			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1532			clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>,
1533				 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>;
1534			clock-names = "core_clk", "sclk_unipro_main";
1535			freq-table-hz = <0 0>, <0 0>;
1536			pinctrl-names = "default";
1537			pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>;
1538			phys = <&ufs_1_phy>;
1539			phy-names = "ufs-phy";
1540			samsung,sysreg = <&syscon_fsys2 0x714>;
1541			status = "disabled";
1542		};
1543
1544		watchdog_cl0: watchdog@10050000 {
1545			compatible = "samsung,exynosautov9-wdt";
1546			reg = <0x10050000 0x100>;
1547			interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
1548			clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>;
1549			clock-names = "watchdog", "watchdog_src";
1550			samsung,syscon-phandle = <&pmu_system_controller>;
1551			samsung,cluster-index = <0>;
1552		};
1553
1554		watchdog_cl1: watchdog@10060000 {
1555			compatible = "samsung,exynosautov9-wdt";
1556			reg = <0x10060000 0x100>;
1557			interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
1558			clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>;
1559			clock-names = "watchdog", "watchdog_src";
1560			samsung,syscon-phandle = <&pmu_system_controller>;
1561			samsung,cluster-index = <1>;
1562		};
1563
1564		pwm: pwm@103f0000 {
1565			compatible = "samsung,exynosautov9-pwm",
1566				     "samsung,exynos4210-pwm";
1567			reg = <0x103f0000 0x100>;
1568			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1569			#pwm-cells = <3>;
1570			clocks = <&xtcxo>;
1571			clock-names = "timers";
1572			status = "disabled";
1573		};
1574	};
1575};
1576
1577#include "exynosautov9-pinctrl.dtsi"
1578