1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung ExynosAutov9 SADK board device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6 *
7 */
8
9/dts-v1/;
10#include "exynosautov9.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	model = "Samsung ExynosAuto v9 SADK board";
15	compatible = "samsung,exynosautov9-sadk", "samsung,exynosautov9";
16
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		serial0 = &serial_0;
22	};
23
24	chosen {
25		stdout-path = &serial_0;
26	};
27
28	memory@80000000 {
29		device_type = "memory";
30		reg = <0x0 0x80000000 0x0 0x77000000>,
31		      <0x8 0x80000000 0x1 0x7ba00000>,
32		      <0xa 0x00000000 0x2 0x00000000>;
33	};
34
35	ufs_0_fixed_vcc_reg: regulator-0 {
36		compatible = "regulator-fixed";
37		regulator-name = "ufs-vcc";
38		gpio = <&gpq0 1 GPIO_ACTIVE_HIGH>;
39		regulator-boot-on;
40		enable-active-high;
41	};
42
43	ufs_1_fixed_vcc_reg: regulator-1 {
44		compatible = "regulator-fixed";
45		regulator-name = "ufs-vcc";
46		gpio = <&gpg2 2 GPIO_ACTIVE_HIGH>;
47		regulator-boot-on;
48		enable-active-high;
49	};
50};
51
52&pwm {
53	pinctrl-names = "default";
54	pinctrl-0 = <&pwm_tout3>;
55	status = "okay";
56};
57
58&serial_0 {
59	pinctrl-0 = <&uart0_bus_dual>;
60	status = "okay";
61};
62
63&ufs_0_phy {
64	status = "okay";
65};
66
67&ufs_1_phy {
68	status = "okay";
69};
70
71&ufs_0 {
72	status = "okay";
73	vcc-supply = <&ufs_0_fixed_vcc_reg>;
74};
75
76&ufs_1 {
77	status = "okay";
78	vcc-supply = <&ufs_1_fixed_vcc_reg>;
79};
80
81&usi_0 {
82	samsung,clkreq-on; /* needed for UART mode */
83	status = "okay";
84};
85
86&xtcxo {
87	clock-frequency = <26000000>;
88};
89