1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos7 SoC device tree source 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 */ 8 9#include <dt-bindings/clock/exynos7-clk.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "samsung,exynos7"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 pinctrl0 = &pinctrl_alive; 20 pinctrl1 = &pinctrl_bus0; 21 pinctrl2 = &pinctrl_nfc; 22 pinctrl3 = &pinctrl_touch; 23 pinctrl4 = &pinctrl_ff; 24 pinctrl5 = &pinctrl_ese; 25 pinctrl6 = &pinctrl_fsys0; 26 pinctrl7 = &pinctrl_fsys1; 27 pinctrl8 = &pinctrl_bus1; 28 tmuctrl0 = &tmuctrl_0; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a57-pmu"; 33 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, 38 <&cpu_atlas2>, <&cpu_atlas3>; 39 }; 40 41 fin_pll: clock { 42 /* XXTI */ 43 compatible = "fixed-clock"; 44 clock-output-names = "fin_pll"; 45 #clock-cells = <0>; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu_atlas0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a57"; 55 reg = <0x0>; 56 enable-method = "psci"; 57 i-cache-size = <0xc000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <256>; 63 next-level-cache = <&atlas_l2>; 64 }; 65 66 cpu_atlas1: cpu@1 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a57"; 69 reg = <0x1>; 70 enable-method = "psci"; 71 i-cache-size = <0xc000>; 72 i-cache-line-size = <64>; 73 i-cache-sets = <256>; 74 d-cache-size = <0x8000>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <256>; 77 next-level-cache = <&atlas_l2>; 78 }; 79 80 cpu_atlas2: cpu@2 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a57"; 83 reg = <0x2>; 84 enable-method = "psci"; 85 i-cache-size = <0xc000>; 86 i-cache-line-size = <64>; 87 i-cache-sets = <256>; 88 d-cache-size = <0x8000>; 89 d-cache-line-size = <64>; 90 d-cache-sets = <256>; 91 next-level-cache = <&atlas_l2>; 92 }; 93 94 cpu_atlas3: cpu@3 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57"; 97 reg = <0x3>; 98 enable-method = "psci"; 99 i-cache-size = <0xc000>; 100 i-cache-line-size = <64>; 101 i-cache-sets = <256>; 102 d-cache-size = <0x8000>; 103 d-cache-line-size = <64>; 104 d-cache-sets = <256>; 105 next-level-cache = <&atlas_l2>; 106 }; 107 108 atlas_l2: l2-cache0 { 109 compatible = "cache"; 110 cache-size = <0x200000>; 111 cache-line-size = <64>; 112 cache-sets = <2048>; 113 }; 114 }; 115 116 psci { 117 compatible = "arm,psci"; 118 method = "smc"; 119 cpu_off = <0x84000002>; 120 cpu_on = <0xC4000003>; 121 }; 122 123 soc: soc@0 { 124 compatible = "simple-bus"; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0 0 0 0x18000000>; 128 129 chipid@10000000 { 130 compatible = "samsung,exynos4210-chipid"; 131 reg = <0x10000000 0x100>; 132 }; 133 134 gic: interrupt-controller@11001000 { 135 compatible = "arm,gic-400"; 136 #interrupt-cells = <3>; 137 #address-cells = <0>; 138 interrupt-controller; 139 reg = <0x11001000 0x1000>, 140 <0x11002000 0x2000>, 141 <0x11004000 0x2000>, 142 <0x11006000 0x2000>; 143 }; 144 145 pdma0: dma-controller@10e10000 { 146 compatible = "arm,pl330", "arm,primecell"; 147 reg = <0x10E10000 0x1000>; 148 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 149 clocks = <&clock_fsys0 ACLK_PDMA0>; 150 clock-names = "apb_pclk"; 151 #dma-cells = <1>; 152 #dma-channels = <8>; 153 #dma-requests = <32>; 154 }; 155 156 pdma1: dma-controller@10eb0000 { 157 compatible = "arm,pl330", "arm,primecell"; 158 reg = <0x10EB0000 0x1000>; 159 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&clock_fsys0 ACLK_PDMA1>; 161 clock-names = "apb_pclk"; 162 #dma-cells = <1>; 163 #dma-channels = <8>; 164 #dma-requests = <32>; 165 }; 166 167 clock_topc: clock-controller@10570000 { 168 compatible = "samsung,exynos7-clock-topc"; 169 reg = <0x10570000 0x10000>; 170 #clock-cells = <1>; 171 }; 172 173 clock_top0: clock-controller@105d0000 { 174 compatible = "samsung,exynos7-clock-top0"; 175 reg = <0x105d0000 0xb000>; 176 #clock-cells = <1>; 177 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 178 <&clock_topc DOUT_SCLK_BUS1_PLL>, 179 <&clock_topc DOUT_SCLK_CC_PLL>, 180 <&clock_topc DOUT_SCLK_MFC_PLL>, 181 <&clock_topc DOUT_SCLK_AUD_PLL>; 182 clock-names = "fin_pll", "dout_sclk_bus0_pll", 183 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 184 "dout_sclk_mfc_pll", "dout_sclk_aud_pll"; 185 }; 186 187 clock_top1: clock-controller@105e0000 { 188 compatible = "samsung,exynos7-clock-top1"; 189 reg = <0x105e0000 0xb000>; 190 #clock-cells = <1>; 191 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 192 <&clock_topc DOUT_SCLK_BUS1_PLL>, 193 <&clock_topc DOUT_SCLK_CC_PLL>, 194 <&clock_topc DOUT_SCLK_MFC_PLL>; 195 clock-names = "fin_pll", "dout_sclk_bus0_pll", 196 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 197 "dout_sclk_mfc_pll"; 198 }; 199 200 clock_ccore: clock-controller@105b0000 { 201 compatible = "samsung,exynos7-clock-ccore"; 202 reg = <0x105b0000 0xd00>; 203 #clock-cells = <1>; 204 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; 205 clock-names = "fin_pll", "dout_aclk_ccore_133"; 206 }; 207 208 clock_peric0: clock-controller@13610000 { 209 compatible = "samsung,exynos7-clock-peric0"; 210 reg = <0x13610000 0xd00>; 211 #clock-cells = <1>; 212 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, 213 <&clock_top0 CLK_SCLK_UART0>; 214 clock-names = "fin_pll", "dout_aclk_peric0_66", 215 "sclk_uart0"; 216 }; 217 218 clock_peric1: clock-controller@14c80000 { 219 compatible = "samsung,exynos7-clock-peric1"; 220 reg = <0x14c80000 0xd00>; 221 #clock-cells = <1>; 222 clocks = <&fin_pll>, 223 <&clock_top0 DOUT_ACLK_PERIC1>, 224 <&clock_top0 CLK_SCLK_UART1>, 225 <&clock_top0 CLK_SCLK_UART2>, 226 <&clock_top0 CLK_SCLK_UART3>, 227 <&clock_top0 CLK_SCLK_SPI0>, 228 <&clock_top0 CLK_SCLK_SPI1>, 229 <&clock_top0 CLK_SCLK_SPI2>, 230 <&clock_top0 CLK_SCLK_SPI3>, 231 <&clock_top0 CLK_SCLK_SPI4>, 232 <&clock_top0 CLK_SCLK_I2S1>, 233 <&clock_top0 CLK_SCLK_PCM1>, 234 <&clock_top0 CLK_SCLK_SPDIF>; 235 clock-names = "fin_pll", 236 "dout_aclk_peric1_66", 237 "sclk_uart1", 238 "sclk_uart2", 239 "sclk_uart3", 240 "sclk_spi0", 241 "sclk_spi1", 242 "sclk_spi2", 243 "sclk_spi3", 244 "sclk_spi4", 245 "sclk_i2s1", 246 "sclk_pcm1", 247 "sclk_spdif"; 248 }; 249 250 clock_peris: clock-controller@10040000 { 251 compatible = "samsung,exynos7-clock-peris"; 252 reg = <0x10040000 0xd00>; 253 #clock-cells = <1>; 254 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; 255 clock-names = "fin_pll", "dout_aclk_peris_66"; 256 }; 257 258 clock_fsys0: clock-controller@10e90000 { 259 compatible = "samsung,exynos7-clock-fsys0"; 260 reg = <0x10e90000 0xd00>; 261 #clock-cells = <1>; 262 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, 263 <&clock_top1 DOUT_SCLK_MMC2>; 264 clock-names = "fin_pll", "dout_aclk_fsys0_200", 265 "dout_sclk_mmc2"; 266 }; 267 268 clock_fsys1: clock-controller@156e0000 { 269 compatible = "samsung,exynos7-clock-fsys1"; 270 reg = <0x156e0000 0xd00>; 271 #clock-cells = <1>; 272 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, 273 <&clock_top1 DOUT_SCLK_MMC0>, 274 <&clock_top1 DOUT_SCLK_MMC1>, 275 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>, 276 <&clock_top1 DOUT_SCLK_PHY_FSYS1>, 277 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>; 278 clock-names = "fin_pll", "dout_aclk_fsys1_200", 279 "dout_sclk_mmc0", "dout_sclk_mmc1", 280 "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1", 281 "dout_sclk_phy_fsys1_26m"; 282 }; 283 284 serial_0: serial@13630000 { 285 compatible = "samsung,exynos4210-uart"; 286 reg = <0x13630000 0x100>; 287 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clock_peric0 PCLK_UART0>, 289 <&clock_peric0 SCLK_UART0>; 290 clock-names = "uart", "clk_uart_baud0"; 291 status = "disabled"; 292 }; 293 294 serial_1: serial@14c20000 { 295 compatible = "samsung,exynos4210-uart"; 296 reg = <0x14c20000 0x100>; 297 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&clock_peric1 PCLK_UART1>, 299 <&clock_peric1 SCLK_UART1>; 300 clock-names = "uart", "clk_uart_baud0"; 301 status = "disabled"; 302 }; 303 304 serial_2: serial@14c30000 { 305 compatible = "samsung,exynos4210-uart"; 306 reg = <0x14c30000 0x100>; 307 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&clock_peric1 PCLK_UART2>, 309 <&clock_peric1 SCLK_UART2>; 310 clock-names = "uart", "clk_uart_baud0"; 311 status = "disabled"; 312 }; 313 314 serial_3: serial@14c40000 { 315 compatible = "samsung,exynos4210-uart"; 316 reg = <0x14c40000 0x100>; 317 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&clock_peric1 PCLK_UART3>, 319 <&clock_peric1 SCLK_UART3>; 320 clock-names = "uart", "clk_uart_baud0"; 321 status = "disabled"; 322 }; 323 324 pinctrl_alive: pinctrl@10580000 { 325 compatible = "samsung,exynos7-pinctrl"; 326 reg = <0x10580000 0x1000>; 327 328 wakeup-interrupt-controller { 329 compatible = "samsung,exynos7-wakeup-eint"; 330 interrupt-parent = <&gic>; 331 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 332 }; 333 }; 334 335 pinctrl_bus0: pinctrl@13470000 { 336 compatible = "samsung,exynos7-pinctrl"; 337 reg = <0x13470000 0x1000>; 338 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 339 }; 340 341 pinctrl_nfc: pinctrl@14cd0000 { 342 compatible = "samsung,exynos7-pinctrl"; 343 reg = <0x14cd0000 0x1000>; 344 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 345 }; 346 347 pinctrl_touch: pinctrl@14ce0000 { 348 compatible = "samsung,exynos7-pinctrl"; 349 reg = <0x14ce0000 0x1000>; 350 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 351 }; 352 353 pinctrl_ff: pinctrl@14c90000 { 354 compatible = "samsung,exynos7-pinctrl"; 355 reg = <0x14c90000 0x1000>; 356 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 357 }; 358 359 pinctrl_ese: pinctrl@14ca0000 { 360 compatible = "samsung,exynos7-pinctrl"; 361 reg = <0x14ca0000 0x1000>; 362 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 363 }; 364 365 pinctrl_fsys0: pinctrl@10e60000 { 366 compatible = "samsung,exynos7-pinctrl"; 367 reg = <0x10e60000 0x1000>; 368 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 369 }; 370 371 pinctrl_fsys1: pinctrl@15690000 { 372 compatible = "samsung,exynos7-pinctrl"; 373 reg = <0x15690000 0x1000>; 374 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 375 }; 376 377 pinctrl_bus1: pinctrl@14870000 { 378 compatible = "samsung,exynos7-pinctrl"; 379 reg = <0x14870000 0x1000>; 380 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 381 }; 382 383 hsi2c_0: i2c@13640000 { 384 compatible = "samsung,exynos7-hsi2c"; 385 reg = <0x13640000 0x1000>; 386 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&hs_i2c0_bus>; 391 clocks = <&clock_peric0 PCLK_HSI2C0>; 392 clock-names = "hsi2c"; 393 status = "disabled"; 394 }; 395 396 hsi2c_1: i2c@13650000 { 397 compatible = "samsung,exynos7-hsi2c"; 398 reg = <0x13650000 0x1000>; 399 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&hs_i2c1_bus>; 404 clocks = <&clock_peric0 PCLK_HSI2C1>; 405 clock-names = "hsi2c"; 406 status = "disabled"; 407 }; 408 409 hsi2c_2: i2c@14e60000 { 410 compatible = "samsung,exynos7-hsi2c"; 411 reg = <0x14e60000 0x1000>; 412 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&hs_i2c2_bus>; 417 clocks = <&clock_peric1 PCLK_HSI2C2>; 418 clock-names = "hsi2c"; 419 status = "disabled"; 420 }; 421 422 hsi2c_3: i2c@14e70000 { 423 compatible = "samsung,exynos7-hsi2c"; 424 reg = <0x14e70000 0x1000>; 425 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&hs_i2c3_bus>; 430 clocks = <&clock_peric1 PCLK_HSI2C3>; 431 clock-names = "hsi2c"; 432 status = "disabled"; 433 }; 434 435 hsi2c_4: i2c@13660000 { 436 compatible = "samsung,exynos7-hsi2c"; 437 reg = <0x13660000 0x1000>; 438 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&hs_i2c4_bus>; 443 clocks = <&clock_peric0 PCLK_HSI2C4>; 444 clock-names = "hsi2c"; 445 status = "disabled"; 446 }; 447 448 hsi2c_5: i2c@13670000 { 449 compatible = "samsung,exynos7-hsi2c"; 450 reg = <0x13670000 0x1000>; 451 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&hs_i2c5_bus>; 456 clocks = <&clock_peric0 PCLK_HSI2C5>; 457 clock-names = "hsi2c"; 458 status = "disabled"; 459 }; 460 461 hsi2c_6: i2c@14e00000 { 462 compatible = "samsung,exynos7-hsi2c"; 463 reg = <0x14e00000 0x1000>; 464 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&hs_i2c6_bus>; 469 clocks = <&clock_peric1 PCLK_HSI2C6>; 470 clock-names = "hsi2c"; 471 status = "disabled"; 472 }; 473 474 hsi2c_7: i2c@13e10000 { 475 compatible = "samsung,exynos7-hsi2c"; 476 reg = <0x13e10000 0x1000>; 477 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&hs_i2c7_bus>; 482 clocks = <&clock_peric1 PCLK_HSI2C7>; 483 clock-names = "hsi2c"; 484 status = "disabled"; 485 }; 486 487 hsi2c_8: i2c@14e20000 { 488 compatible = "samsung,exynos7-hsi2c"; 489 reg = <0x14e20000 0x1000>; 490 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&hs_i2c8_bus>; 495 clocks = <&clock_peric1 PCLK_HSI2C8>; 496 clock-names = "hsi2c"; 497 status = "disabled"; 498 }; 499 500 hsi2c_9: i2c@13680000 { 501 compatible = "samsung,exynos7-hsi2c"; 502 reg = <0x13680000 0x1000>; 503 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&hs_i2c9_bus>; 508 clocks = <&clock_peric0 PCLK_HSI2C9>; 509 clock-names = "hsi2c"; 510 status = "disabled"; 511 }; 512 513 hsi2c_10: i2c@13690000 { 514 compatible = "samsung,exynos7-hsi2c"; 515 reg = <0x13690000 0x1000>; 516 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 pinctrl-names = "default"; 520 pinctrl-0 = <&hs_i2c10_bus>; 521 clocks = <&clock_peric0 PCLK_HSI2C10>; 522 clock-names = "hsi2c"; 523 status = "disabled"; 524 }; 525 526 hsi2c_11: i2c@136a0000 { 527 compatible = "samsung,exynos7-hsi2c"; 528 reg = <0x136a0000 0x1000>; 529 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&hs_i2c11_bus>; 534 clocks = <&clock_peric0 PCLK_HSI2C11>; 535 clock-names = "hsi2c"; 536 status = "disabled"; 537 }; 538 539 pmu_system_controller: system-controller@105c0000 { 540 compatible = "samsung,exynos7-pmu", "syscon"; 541 reg = <0x105c0000 0x5000>; 542 }; 543 544 rtc: rtc@10590000 { 545 compatible = "samsung,s3c6410-rtc"; 546 reg = <0x10590000 0x100>; 547 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clock_ccore PCLK_RTC>; 550 clock-names = "rtc"; 551 status = "disabled"; 552 }; 553 554 watchdog: watchdog@101d0000 { 555 compatible = "samsung,exynos7-wdt"; 556 reg = <0x101d0000 0x100>; 557 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&clock_peris PCLK_WDT>; 559 clock-names = "watchdog"; 560 samsung,syscon-phandle = <&pmu_system_controller>; 561 status = "disabled"; 562 }; 563 564 gpu: gpu@14ac0000 { 565 compatible = "samsung,exynos5433-mali", "arm,mali-t760"; 566 reg = <0x14ac0000 0x5000>; 567 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 570 interrupt-names = "job", "mmu", "gpu"; 571 status = "disabled"; 572 /* TODO: operating points for DVFS, cooling device */ 573 }; 574 575 mmc_0: mmc@15740000 { 576 compatible = "samsung,exynos7-dw-mshc-smu"; 577 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 reg = <0x15740000 0x2000>; 581 clocks = <&clock_fsys1 ACLK_MMC0>, 582 <&clock_top1 CLK_SCLK_MMC0>; 583 clock-names = "biu", "ciu"; 584 fifo-depth = <0x40>; 585 status = "disabled"; 586 }; 587 588 mmc_1: mmc@15750000 { 589 compatible = "samsung,exynos7-dw-mshc"; 590 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 reg = <0x15750000 0x2000>; 594 clocks = <&clock_fsys1 ACLK_MMC1>, 595 <&clock_top1 CLK_SCLK_MMC1>; 596 clock-names = "biu", "ciu"; 597 fifo-depth = <0x40>; 598 status = "disabled"; 599 }; 600 601 mmc_2: mmc@15560000 { 602 compatible = "samsung,exynos7-dw-mshc-smu"; 603 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 reg = <0x15560000 0x2000>; 607 clocks = <&clock_fsys0 ACLK_MMC2>, 608 <&clock_top1 CLK_SCLK_MMC2>; 609 clock-names = "biu", "ciu"; 610 fifo-depth = <0x40>; 611 status = "disabled"; 612 }; 613 614 adc: adc@13620000 { 615 compatible = "samsung,exynos7-adc"; 616 reg = <0x13620000 0x100>; 617 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&clock_peric0 PCLK_ADCIF>; 619 clock-names = "adc"; 620 #io-channel-cells = <1>; 621 status = "disabled"; 622 }; 623 624 pwm: pwm@136c0000 { 625 compatible = "samsung,exynos4210-pwm"; 626 reg = <0x136c0000 0x100>; 627 interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; 632 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 633 #pwm-cells = <3>; 634 clocks = <&clock_peric0 PCLK_PWM>; 635 clock-names = "timers"; 636 }; 637 638 tmuctrl_0: tmu@10060000 { 639 compatible = "samsung,exynos7-tmu"; 640 reg = <0x10060000 0x200>; 641 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&clock_peris PCLK_TMU>, 643 <&clock_peris SCLK_TMU>; 644 clock-names = "tmu_apbif", "tmu_sclk"; 645 #thermal-sensor-cells = <0>; 646 }; 647 648 ufs: ufs@15570000 { 649 compatible = "samsung,exynos7-ufs"; 650 reg = <0x15570000 0x100>, /* 0: HCI standard */ 651 <0x15570100 0x100>, /* 1: Vendor specificed */ 652 <0x15571000 0x200>, /* 2: UNIPRO */ 653 <0x15572000 0x300>; /* 3: UFS protector */ 654 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 655 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clock_fsys1 ACLK_UFS20_LINK>, 657 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; 658 clock-names = "core_clk", "sclk_unipro_main"; 659 freq-table-hz = <0 0>, <0 0>; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 662 phys = <&ufs_phy>; 663 phy-names = "ufs-phy"; 664 status = "disabled"; 665 }; 666 667 ufs_phy: ufs-phy@15571800 { 668 compatible = "samsung,exynos7-ufs-phy"; 669 reg = <0x15571800 0x240>; 670 reg-names = "phy-pma"; 671 samsung,pmu-syscon = <&pmu_system_controller>; 672 #phy-cells = <0>; 673 clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, 674 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, 675 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, 676 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; 677 clock-names = "ref_clk", "rx1_symbol_clk", 678 "rx0_symbol_clk", 679 "tx0_symbol_clk"; 680 }; 681 682 usbdrd_phy: phy@15500000 { 683 compatible = "samsung,exynos7-usbdrd-phy"; 684 reg = <0x15500000 0x100>; 685 clocks = <&clock_fsys0 ACLK_USBDRD300>, 686 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, 687 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, 688 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, 689 <&clock_fsys0 SCLK_USBDRD300_REFCLK>; 690 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; 691 samsung,pmu-syscon = <&pmu_system_controller>; 692 #phy-cells = <1>; 693 }; 694 695 usbdrd: usb { 696 compatible = "samsung,exynos7-dwusb3"; 697 clocks = <&clock_fsys0 ACLK_USBDRD300>, 698 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, 699 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; 700 clock-names = "usbdrd30", "usbdrd30_susp_clk", 701 "usbdrd30_axius_clk"; 702 #address-cells = <1>; 703 #size-cells = <1>; 704 ranges; 705 706 usb@15400000 { 707 compatible = "snps,dwc3"; 708 reg = <0x15400000 0x10000>; 709 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 710 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 711 phy-names = "usb2-phy", "usb3-phy"; 712 }; 713 }; 714 }; 715 716 thermal-zones { 717 atlas_thermal: cluster0-thermal { 718 polling-delay-passive = <0>; /* milliseconds */ 719 polling-delay = <0>; /* milliseconds */ 720 thermal-sensors = <&tmuctrl_0>; 721 #include "exynos7-trip-points.dtsi" 722 }; 723 }; 724 725 timer { 726 compatible = "arm,armv8-timer"; 727 interrupts = <GIC_PPI 13 728 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 729 <GIC_PPI 14 730 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 731 <GIC_PPI 11 732 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 733 <GIC_PPI 10 734 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 735 }; 736}; 737 738#include "exynos7-pinctrl.dtsi" 739#include "arm/exynos-syscon-restart.dtsi" 740