1/* 2 * SAMSUNG EXYNOS7 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include <dt-bindings/clock/exynos7-clk.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14 15/ { 16 compatible = "samsung,exynos7"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 pinctrl0 = &pinctrl_alive; 23 pinctrl1 = &pinctrl_bus0; 24 pinctrl2 = &pinctrl_nfc; 25 pinctrl3 = &pinctrl_touch; 26 pinctrl4 = &pinctrl_ff; 27 pinctrl5 = &pinctrl_ese; 28 pinctrl6 = &pinctrl_fsys0; 29 pinctrl7 = &pinctrl_fsys1; 30 pinctrl8 = &pinctrl_bus1; 31 tmuctrl0 = &tmuctrl_0; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu_atlas0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a57", "arm,armv8"; 41 reg = <0x0>; 42 enable-method = "psci"; 43 }; 44 45 cpu_atlas1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a57", "arm,armv8"; 48 reg = <0x1>; 49 enable-method = "psci"; 50 }; 51 52 cpu_atlas2: cpu@2 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a57", "arm,armv8"; 55 reg = <0x2>; 56 enable-method = "psci"; 57 }; 58 59 cpu_atlas3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a57", "arm,armv8"; 62 reg = <0x3>; 63 enable-method = "psci"; 64 }; 65 }; 66 67 psci { 68 compatible = "arm,psci-0.2"; 69 method = "smc"; 70 }; 71 72 soc: soc { 73 compatible = "simple-bus"; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges = <0 0 0 0x18000000>; 77 78 chipid@10000000 { 79 compatible = "samsung,exynos4210-chipid"; 80 reg = <0x10000000 0x100>; 81 }; 82 83 fin_pll: xxti { 84 compatible = "fixed-clock"; 85 clock-output-names = "fin_pll"; 86 #clock-cells = <0>; 87 }; 88 89 gic: interrupt-controller@11001000 { 90 compatible = "arm,gic-400"; 91 #interrupt-cells = <3>; 92 #address-cells = <0>; 93 interrupt-controller; 94 reg = <0x11001000 0x1000>, 95 <0x11002000 0x1000>, 96 <0x11004000 0x2000>, 97 <0x11006000 0x2000>; 98 }; 99 100 amba { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges; 105 106 pdma0: pdma@10E10000 { 107 compatible = "arm,pl330", "arm,primecell"; 108 reg = <0x10E10000 0x1000>; 109 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&clock_fsys0 ACLK_PDMA0>; 111 clock-names = "apb_pclk"; 112 #dma-cells = <1>; 113 #dma-channels = <8>; 114 #dma-requests = <32>; 115 }; 116 117 pdma1: pdma@10EB0000 { 118 compatible = "arm,pl330", "arm,primecell"; 119 reg = <0x10EB0000 0x1000>; 120 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&clock_fsys0 ACLK_PDMA1>; 122 clock-names = "apb_pclk"; 123 #dma-cells = <1>; 124 #dma-channels = <8>; 125 #dma-requests = <32>; 126 }; 127 }; 128 129 clock_topc: clock-controller@10570000 { 130 compatible = "samsung,exynos7-clock-topc"; 131 reg = <0x10570000 0x10000>; 132 #clock-cells = <1>; 133 }; 134 135 clock_top0: clock-controller@105d0000 { 136 compatible = "samsung,exynos7-clock-top0"; 137 reg = <0x105d0000 0xb000>; 138 #clock-cells = <1>; 139 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 140 <&clock_topc DOUT_SCLK_BUS1_PLL>, 141 <&clock_topc DOUT_SCLK_CC_PLL>, 142 <&clock_topc DOUT_SCLK_MFC_PLL>; 143 clock-names = "fin_pll", "dout_sclk_bus0_pll", 144 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 145 "dout_sclk_mfc_pll"; 146 }; 147 148 clock_top1: clock-controller@105e0000 { 149 compatible = "samsung,exynos7-clock-top1"; 150 reg = <0x105e0000 0xb000>; 151 #clock-cells = <1>; 152 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 153 <&clock_topc DOUT_SCLK_BUS1_PLL>, 154 <&clock_topc DOUT_SCLK_CC_PLL>, 155 <&clock_topc DOUT_SCLK_MFC_PLL>; 156 clock-names = "fin_pll", "dout_sclk_bus0_pll", 157 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 158 "dout_sclk_mfc_pll"; 159 }; 160 161 clock_ccore: clock-controller@105b0000 { 162 compatible = "samsung,exynos7-clock-ccore"; 163 reg = <0x105b0000 0xd00>; 164 #clock-cells = <1>; 165 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; 166 clock-names = "fin_pll", "dout_aclk_ccore_133"; 167 }; 168 169 clock_peric0: clock-controller@13610000 { 170 compatible = "samsung,exynos7-clock-peric0"; 171 reg = <0x13610000 0xd00>; 172 #clock-cells = <1>; 173 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, 174 <&clock_top0 CLK_SCLK_UART0>; 175 clock-names = "fin_pll", "dout_aclk_peric0_66", 176 "sclk_uart0"; 177 }; 178 179 clock_peric1: clock-controller@14c80000 { 180 compatible = "samsung,exynos7-clock-peric1"; 181 reg = <0x14c80000 0xd00>; 182 #clock-cells = <1>; 183 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, 184 <&clock_top0 CLK_SCLK_UART1>, 185 <&clock_top0 CLK_SCLK_UART2>, 186 <&clock_top0 CLK_SCLK_UART3>; 187 clock-names = "fin_pll", "dout_aclk_peric1_66", 188 "sclk_uart1", "sclk_uart2", "sclk_uart3"; 189 }; 190 191 clock_peris: clock-controller@10040000 { 192 compatible = "samsung,exynos7-clock-peris"; 193 reg = <0x10040000 0xd00>; 194 #clock-cells = <1>; 195 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; 196 clock-names = "fin_pll", "dout_aclk_peris_66"; 197 }; 198 199 clock_fsys0: clock-controller@10e90000 { 200 compatible = "samsung,exynos7-clock-fsys0"; 201 reg = <0x10e90000 0xd00>; 202 #clock-cells = <1>; 203 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, 204 <&clock_top1 DOUT_SCLK_MMC2>; 205 clock-names = "fin_pll", "dout_aclk_fsys0_200", 206 "dout_sclk_mmc2"; 207 }; 208 209 clock_fsys1: clock-controller@156e0000 { 210 compatible = "samsung,exynos7-clock-fsys1"; 211 reg = <0x156e0000 0xd00>; 212 #clock-cells = <1>; 213 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, 214 <&clock_top1 DOUT_SCLK_MMC0>, 215 <&clock_top1 DOUT_SCLK_MMC1>; 216 clock-names = "fin_pll", "dout_aclk_fsys1_200", 217 "dout_sclk_mmc0", "dout_sclk_mmc1"; 218 }; 219 220 serial_0: serial@13630000 { 221 compatible = "samsung,exynos4210-uart"; 222 reg = <0x13630000 0x100>; 223 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&clock_peric0 PCLK_UART0>, 225 <&clock_peric0 SCLK_UART0>; 226 clock-names = "uart", "clk_uart_baud0"; 227 status = "disabled"; 228 }; 229 230 serial_1: serial@14c20000 { 231 compatible = "samsung,exynos4210-uart"; 232 reg = <0x14c20000 0x100>; 233 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&clock_peric1 PCLK_UART1>, 235 <&clock_peric1 SCLK_UART1>; 236 clock-names = "uart", "clk_uart_baud0"; 237 status = "disabled"; 238 }; 239 240 serial_2: serial@14c30000 { 241 compatible = "samsung,exynos4210-uart"; 242 reg = <0x14c30000 0x100>; 243 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&clock_peric1 PCLK_UART2>, 245 <&clock_peric1 SCLK_UART2>; 246 clock-names = "uart", "clk_uart_baud0"; 247 status = "disabled"; 248 }; 249 250 serial_3: serial@14c40000 { 251 compatible = "samsung,exynos4210-uart"; 252 reg = <0x14c40000 0x100>; 253 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&clock_peric1 PCLK_UART3>, 255 <&clock_peric1 SCLK_UART3>; 256 clock-names = "uart", "clk_uart_baud0"; 257 status = "disabled"; 258 }; 259 260 pinctrl_alive: pinctrl@10580000 { 261 compatible = "samsung,exynos7-pinctrl"; 262 reg = <0x10580000 0x1000>; 263 264 wakeup-interrupt-controller { 265 compatible = "samsung,exynos7-wakeup-eint"; 266 interrupt-parent = <&gic>; 267 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 268 }; 269 }; 270 271 pinctrl_bus0: pinctrl@13470000 { 272 compatible = "samsung,exynos7-pinctrl"; 273 reg = <0x13470000 0x1000>; 274 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 275 }; 276 277 pinctrl_nfc: pinctrl@14cd0000 { 278 compatible = "samsung,exynos7-pinctrl"; 279 reg = <0x14cd0000 0x1000>; 280 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 281 }; 282 283 pinctrl_touch: pinctrl@14ce0000 { 284 compatible = "samsung,exynos7-pinctrl"; 285 reg = <0x14ce0000 0x1000>; 286 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 287 }; 288 289 pinctrl_ff: pinctrl@14c90000 { 290 compatible = "samsung,exynos7-pinctrl"; 291 reg = <0x14c90000 0x1000>; 292 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 293 }; 294 295 pinctrl_ese: pinctrl@14ca0000 { 296 compatible = "samsung,exynos7-pinctrl"; 297 reg = <0x14ca0000 0x1000>; 298 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 299 }; 300 301 pinctrl_fsys0: pinctrl@10e60000 { 302 compatible = "samsung,exynos7-pinctrl"; 303 reg = <0x10e60000 0x1000>; 304 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 305 }; 306 307 pinctrl_fsys1: pinctrl@15690000 { 308 compatible = "samsung,exynos7-pinctrl"; 309 reg = <0x15690000 0x1000>; 310 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 311 }; 312 313 pinctrl_bus1: pinctrl@14870000 { 314 compatible = "samsung,exynos7-pinctrl"; 315 reg = <0x14870000 0x1000>; 316 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 317 }; 318 319 hsi2c_0: hsi2c@13640000 { 320 compatible = "samsung,exynos7-hsi2c"; 321 reg = <0x13640000 0x1000>; 322 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&hs_i2c0_bus>; 327 clocks = <&clock_peric0 PCLK_HSI2C0>; 328 clock-names = "hsi2c"; 329 status = "disabled"; 330 }; 331 332 hsi2c_1: hsi2c@13650000 { 333 compatible = "samsung,exynos7-hsi2c"; 334 reg = <0x13650000 0x1000>; 335 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&hs_i2c1_bus>; 340 clocks = <&clock_peric0 PCLK_HSI2C1>; 341 clock-names = "hsi2c"; 342 status = "disabled"; 343 }; 344 345 hsi2c_2: hsi2c@14e60000 { 346 compatible = "samsung,exynos7-hsi2c"; 347 reg = <0x14e60000 0x1000>; 348 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&hs_i2c2_bus>; 353 clocks = <&clock_peric1 PCLK_HSI2C2>; 354 clock-names = "hsi2c"; 355 status = "disabled"; 356 }; 357 358 hsi2c_3: hsi2c@14e70000 { 359 compatible = "samsung,exynos7-hsi2c"; 360 reg = <0x14e70000 0x1000>; 361 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&hs_i2c3_bus>; 366 clocks = <&clock_peric1 PCLK_HSI2C3>; 367 clock-names = "hsi2c"; 368 status = "disabled"; 369 }; 370 371 hsi2c_4: hsi2c@13660000 { 372 compatible = "samsung,exynos7-hsi2c"; 373 reg = <0x13660000 0x1000>; 374 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&hs_i2c4_bus>; 379 clocks = <&clock_peric0 PCLK_HSI2C4>; 380 clock-names = "hsi2c"; 381 status = "disabled"; 382 }; 383 384 hsi2c_5: hsi2c@13670000 { 385 compatible = "samsung,exynos7-hsi2c"; 386 reg = <0x13670000 0x1000>; 387 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&hs_i2c5_bus>; 392 clocks = <&clock_peric0 PCLK_HSI2C5>; 393 clock-names = "hsi2c"; 394 status = "disabled"; 395 }; 396 397 hsi2c_6: hsi2c@14e00000 { 398 compatible = "samsung,exynos7-hsi2c"; 399 reg = <0x14e00000 0x1000>; 400 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&hs_i2c6_bus>; 405 clocks = <&clock_peric1 PCLK_HSI2C6>; 406 clock-names = "hsi2c"; 407 status = "disabled"; 408 }; 409 410 hsi2c_7: hsi2c@13e10000 { 411 compatible = "samsung,exynos7-hsi2c"; 412 reg = <0x13e10000 0x1000>; 413 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&hs_i2c7_bus>; 418 clocks = <&clock_peric1 PCLK_HSI2C7>; 419 clock-names = "hsi2c"; 420 status = "disabled"; 421 }; 422 423 hsi2c_8: hsi2c@14e20000 { 424 compatible = "samsung,exynos7-hsi2c"; 425 reg = <0x14e20000 0x1000>; 426 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&hs_i2c8_bus>; 431 clocks = <&clock_peric1 PCLK_HSI2C8>; 432 clock-names = "hsi2c"; 433 status = "disabled"; 434 }; 435 436 hsi2c_9: hsi2c@13680000 { 437 compatible = "samsung,exynos7-hsi2c"; 438 reg = <0x13680000 0x1000>; 439 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&hs_i2c9_bus>; 444 clocks = <&clock_peric0 PCLK_HSI2C9>; 445 clock-names = "hsi2c"; 446 status = "disabled"; 447 }; 448 449 hsi2c_10: hsi2c@13690000 { 450 compatible = "samsung,exynos7-hsi2c"; 451 reg = <0x13690000 0x1000>; 452 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&hs_i2c10_bus>; 457 clocks = <&clock_peric0 PCLK_HSI2C10>; 458 clock-names = "hsi2c"; 459 status = "disabled"; 460 }; 461 462 hsi2c_11: hsi2c@136a0000 { 463 compatible = "samsung,exynos7-hsi2c"; 464 reg = <0x136a0000 0x1000>; 465 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&hs_i2c11_bus>; 470 clocks = <&clock_peric0 PCLK_HSI2C11>; 471 clock-names = "hsi2c"; 472 status = "disabled"; 473 }; 474 475 arm-pmu { 476 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; 477 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, 482 <&cpu_atlas2>, <&cpu_atlas3>; 483 }; 484 485 timer { 486 compatible = "arm,armv8-timer"; 487 interrupts = <GIC_PPI 13 488 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 489 <GIC_PPI 14 490 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 491 <GIC_PPI 11 492 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 493 <GIC_PPI 10 494 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 495 }; 496 497 pmu_system_controller: system-controller@105c0000 { 498 compatible = "samsung,exynos7-pmu", "syscon"; 499 reg = <0x105c0000 0x5000>; 500 }; 501 502 reboot: syscon-reboot { 503 compatible = "syscon-reboot"; 504 regmap = <&pmu_system_controller>; 505 offset = <0x0400>; 506 mask = <0x1>; 507 }; 508 509 rtc: rtc@10590000 { 510 compatible = "samsung,s3c6410-rtc"; 511 reg = <0x10590000 0x100>; 512 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&clock_ccore PCLK_RTC>; 515 clock-names = "rtc"; 516 status = "disabled"; 517 }; 518 519 watchdog: watchdog@101d0000 { 520 compatible = "samsung,exynos7-wdt"; 521 reg = <0x101d0000 0x100>; 522 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&clock_peris PCLK_WDT>; 524 clock-names = "watchdog"; 525 samsung,syscon-phandle = <&pmu_system_controller>; 526 status = "disabled"; 527 }; 528 529 mmc_0: mmc@15740000 { 530 compatible = "samsung,exynos7-dw-mshc-smu"; 531 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 reg = <0x15740000 0x2000>; 535 clocks = <&clock_fsys1 ACLK_MMC0>, 536 <&clock_top1 CLK_SCLK_MMC0>; 537 clock-names = "biu", "ciu"; 538 fifo-depth = <0x40>; 539 status = "disabled"; 540 }; 541 542 mmc_1: mmc@15750000 { 543 compatible = "samsung,exynos7-dw-mshc"; 544 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 reg = <0x15750000 0x2000>; 548 clocks = <&clock_fsys1 ACLK_MMC1>, 549 <&clock_top1 CLK_SCLK_MMC1>; 550 clock-names = "biu", "ciu"; 551 fifo-depth = <0x40>; 552 status = "disabled"; 553 }; 554 555 mmc_2: mmc@15560000 { 556 compatible = "samsung,exynos7-dw-mshc-smu"; 557 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 reg = <0x15560000 0x2000>; 561 clocks = <&clock_fsys0 ACLK_MMC2>, 562 <&clock_top1 CLK_SCLK_MMC2>; 563 clock-names = "biu", "ciu"; 564 fifo-depth = <0x40>; 565 status = "disabled"; 566 }; 567 568 adc: adc@13620000 { 569 compatible = "samsung,exynos7-adc"; 570 reg = <0x13620000 0x100>; 571 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&clock_peric0 PCLK_ADCIF>; 573 clock-names = "adc"; 574 #io-channel-cells = <1>; 575 io-channel-ranges; 576 status = "disabled"; 577 }; 578 579 pwm: pwm@136c0000 { 580 compatible = "samsung,exynos4210-pwm"; 581 reg = <0x136c0000 0x100>; 582 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 583 #pwm-cells = <3>; 584 clocks = <&clock_peric0 PCLK_PWM>; 585 clock-names = "timers"; 586 }; 587 588 tmuctrl_0: tmu@10060000 { 589 compatible = "samsung,exynos7-tmu"; 590 reg = <0x10060000 0x200>; 591 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&clock_peris PCLK_TMU>, 593 <&clock_peris SCLK_TMU>; 594 clock-names = "tmu_apbif", "tmu_sclk"; 595 #include "exynos7-tmu-sensor-conf.dtsi" 596 }; 597 598 thermal-zones { 599 atlas_thermal: cluster0-thermal { 600 polling-delay-passive = <0>; /* milliseconds */ 601 polling-delay = <0>; /* milliseconds */ 602 thermal-sensors = <&tmuctrl_0>; 603 #include "exynos7-trip-points.dtsi" 604 }; 605 }; 606 607 usbdrd_phy: phy@15500000 { 608 compatible = "samsung,exynos7-usbdrd-phy"; 609 reg = <0x15500000 0x100>; 610 clocks = <&clock_fsys0 ACLK_USBDRD300>, 611 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, 612 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, 613 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, 614 <&clock_fsys0 SCLK_USBDRD300_REFCLK>; 615 clock-names = "phy", "ref", "phy_pipe", 616 "phy_utmi", "itp"; 617 samsung,pmu-syscon = <&pmu_system_controller>; 618 #phy-cells = <1>; 619 }; 620 621 usbdrd3 { 622 compatible = "samsung,exynos7-dwusb3"; 623 clocks = <&clock_fsys0 ACLK_USBDRD300>, 624 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, 625 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; 626 clock-names = "usbdrd30", "usbdrd30_susp_clk", 627 "usbdrd30_axius_clk"; 628 #address-cells = <1>; 629 #size-cells = <1>; 630 ranges; 631 632 dwc3@15400000 { 633 compatible = "snps,dwc3"; 634 reg = <0x15400000 0x10000>; 635 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 636 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 637 phy-names = "usb2-phy", "usb3-phy"; 638 }; 639 }; 640 }; 641}; 642 643#include "exynos7-pinctrl.dtsi" 644