1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos7 SoC device tree source 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 */ 8 9#include <dt-bindings/clock/exynos7-clk.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "samsung,exynos7"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 pinctrl0 = &pinctrl_alive; 20 pinctrl1 = &pinctrl_bus0; 21 pinctrl2 = &pinctrl_nfc; 22 pinctrl3 = &pinctrl_touch; 23 pinctrl4 = &pinctrl_ff; 24 pinctrl5 = &pinctrl_ese; 25 pinctrl6 = &pinctrl_fsys0; 26 pinctrl7 = &pinctrl_fsys1; 27 pinctrl8 = &pinctrl_bus1; 28 tmuctrl0 = &tmuctrl_0; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a57-pmu"; 33 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, 38 <&cpu_atlas2>, <&cpu_atlas3>; 39 }; 40 41 fin_pll: clock { 42 /* XXTI */ 43 compatible = "fixed-clock"; 44 clock-output-names = "fin_pll"; 45 #clock-cells = <0>; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu_atlas0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a57"; 55 reg = <0x0>; 56 enable-method = "psci"; 57 }; 58 59 cpu_atlas1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a57"; 62 reg = <0x1>; 63 enable-method = "psci"; 64 }; 65 66 cpu_atlas2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a57"; 69 reg = <0x2>; 70 enable-method = "psci"; 71 }; 72 73 cpu_atlas3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a57"; 76 reg = <0x3>; 77 enable-method = "psci"; 78 }; 79 }; 80 81 psci { 82 compatible = "arm,psci-0.2"; 83 method = "smc"; 84 }; 85 86 soc: soc { 87 compatible = "simple-bus"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges = <0 0 0 0x18000000>; 91 92 chipid@10000000 { 93 compatible = "samsung,exynos4210-chipid"; 94 reg = <0x10000000 0x100>; 95 }; 96 97 gic: interrupt-controller@11001000 { 98 compatible = "arm,gic-400"; 99 #interrupt-cells = <3>; 100 #address-cells = <0>; 101 interrupt-controller; 102 reg = <0x11001000 0x1000>, 103 <0x11002000 0x1000>, 104 <0x11004000 0x2000>, 105 <0x11006000 0x2000>; 106 }; 107 108 amba { 109 compatible = "simple-bus"; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges; 113 114 pdma0: pdma@10e10000 { 115 compatible = "arm,pl330", "arm,primecell"; 116 reg = <0x10E10000 0x1000>; 117 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&clock_fsys0 ACLK_PDMA0>; 119 clock-names = "apb_pclk"; 120 #dma-cells = <1>; 121 #dma-channels = <8>; 122 #dma-requests = <32>; 123 }; 124 125 pdma1: pdma@10eb0000 { 126 compatible = "arm,pl330", "arm,primecell"; 127 reg = <0x10EB0000 0x1000>; 128 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&clock_fsys0 ACLK_PDMA1>; 130 clock-names = "apb_pclk"; 131 #dma-cells = <1>; 132 #dma-channels = <8>; 133 #dma-requests = <32>; 134 }; 135 }; 136 137 clock_topc: clock-controller@10570000 { 138 compatible = "samsung,exynos7-clock-topc"; 139 reg = <0x10570000 0x10000>; 140 #clock-cells = <1>; 141 }; 142 143 clock_top0: clock-controller@105d0000 { 144 compatible = "samsung,exynos7-clock-top0"; 145 reg = <0x105d0000 0xb000>; 146 #clock-cells = <1>; 147 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 148 <&clock_topc DOUT_SCLK_BUS1_PLL>, 149 <&clock_topc DOUT_SCLK_CC_PLL>, 150 <&clock_topc DOUT_SCLK_MFC_PLL>; 151 clock-names = "fin_pll", "dout_sclk_bus0_pll", 152 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 153 "dout_sclk_mfc_pll"; 154 }; 155 156 clock_top1: clock-controller@105e0000 { 157 compatible = "samsung,exynos7-clock-top1"; 158 reg = <0x105e0000 0xb000>; 159 #clock-cells = <1>; 160 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 161 <&clock_topc DOUT_SCLK_BUS1_PLL>, 162 <&clock_topc DOUT_SCLK_CC_PLL>, 163 <&clock_topc DOUT_SCLK_MFC_PLL>; 164 clock-names = "fin_pll", "dout_sclk_bus0_pll", 165 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 166 "dout_sclk_mfc_pll"; 167 }; 168 169 clock_ccore: clock-controller@105b0000 { 170 compatible = "samsung,exynos7-clock-ccore"; 171 reg = <0x105b0000 0xd00>; 172 #clock-cells = <1>; 173 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; 174 clock-names = "fin_pll", "dout_aclk_ccore_133"; 175 }; 176 177 clock_peric0: clock-controller@13610000 { 178 compatible = "samsung,exynos7-clock-peric0"; 179 reg = <0x13610000 0xd00>; 180 #clock-cells = <1>; 181 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, 182 <&clock_top0 CLK_SCLK_UART0>; 183 clock-names = "fin_pll", "dout_aclk_peric0_66", 184 "sclk_uart0"; 185 }; 186 187 clock_peric1: clock-controller@14c80000 { 188 compatible = "samsung,exynos7-clock-peric1"; 189 reg = <0x14c80000 0xd00>; 190 #clock-cells = <1>; 191 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, 192 <&clock_top0 CLK_SCLK_UART1>, 193 <&clock_top0 CLK_SCLK_UART2>, 194 <&clock_top0 CLK_SCLK_UART3>; 195 clock-names = "fin_pll", "dout_aclk_peric1_66", 196 "sclk_uart1", "sclk_uart2", "sclk_uart3"; 197 }; 198 199 clock_peris: clock-controller@10040000 { 200 compatible = "samsung,exynos7-clock-peris"; 201 reg = <0x10040000 0xd00>; 202 #clock-cells = <1>; 203 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; 204 clock-names = "fin_pll", "dout_aclk_peris_66"; 205 }; 206 207 clock_fsys0: clock-controller@10e90000 { 208 compatible = "samsung,exynos7-clock-fsys0"; 209 reg = <0x10e90000 0xd00>; 210 #clock-cells = <1>; 211 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, 212 <&clock_top1 DOUT_SCLK_MMC2>; 213 clock-names = "fin_pll", "dout_aclk_fsys0_200", 214 "dout_sclk_mmc2"; 215 }; 216 217 clock_fsys1: clock-controller@156e0000 { 218 compatible = "samsung,exynos7-clock-fsys1"; 219 reg = <0x156e0000 0xd00>; 220 #clock-cells = <1>; 221 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, 222 <&clock_top1 DOUT_SCLK_MMC0>, 223 <&clock_top1 DOUT_SCLK_MMC1>, 224 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>, 225 <&clock_top1 DOUT_SCLK_PHY_FSYS1>, 226 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>; 227 clock-names = "fin_pll", "dout_aclk_fsys1_200", 228 "dout_sclk_mmc0", "dout_sclk_mmc1", 229 "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1", 230 "dout_sclk_phy_fsys1_26m"; 231 }; 232 233 serial_0: serial@13630000 { 234 compatible = "samsung,exynos4210-uart"; 235 reg = <0x13630000 0x100>; 236 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&clock_peric0 PCLK_UART0>, 238 <&clock_peric0 SCLK_UART0>; 239 clock-names = "uart", "clk_uart_baud0"; 240 status = "disabled"; 241 }; 242 243 serial_1: serial@14c20000 { 244 compatible = "samsung,exynos4210-uart"; 245 reg = <0x14c20000 0x100>; 246 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clock_peric1 PCLK_UART1>, 248 <&clock_peric1 SCLK_UART1>; 249 clock-names = "uart", "clk_uart_baud0"; 250 status = "disabled"; 251 }; 252 253 serial_2: serial@14c30000 { 254 compatible = "samsung,exynos4210-uart"; 255 reg = <0x14c30000 0x100>; 256 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&clock_peric1 PCLK_UART2>, 258 <&clock_peric1 SCLK_UART2>; 259 clock-names = "uart", "clk_uart_baud0"; 260 status = "disabled"; 261 }; 262 263 serial_3: serial@14c40000 { 264 compatible = "samsung,exynos4210-uart"; 265 reg = <0x14c40000 0x100>; 266 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&clock_peric1 PCLK_UART3>, 268 <&clock_peric1 SCLK_UART3>; 269 clock-names = "uart", "clk_uart_baud0"; 270 status = "disabled"; 271 }; 272 273 pinctrl_alive: pinctrl@10580000 { 274 compatible = "samsung,exynos7-pinctrl"; 275 reg = <0x10580000 0x1000>; 276 277 wakeup-interrupt-controller { 278 compatible = "samsung,exynos7-wakeup-eint"; 279 interrupt-parent = <&gic>; 280 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 281 }; 282 }; 283 284 pinctrl_bus0: pinctrl@13470000 { 285 compatible = "samsung,exynos7-pinctrl"; 286 reg = <0x13470000 0x1000>; 287 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 288 }; 289 290 pinctrl_nfc: pinctrl@14cd0000 { 291 compatible = "samsung,exynos7-pinctrl"; 292 reg = <0x14cd0000 0x1000>; 293 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 294 }; 295 296 pinctrl_touch: pinctrl@14ce0000 { 297 compatible = "samsung,exynos7-pinctrl"; 298 reg = <0x14ce0000 0x1000>; 299 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 300 }; 301 302 pinctrl_ff: pinctrl@14c90000 { 303 compatible = "samsung,exynos7-pinctrl"; 304 reg = <0x14c90000 0x1000>; 305 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 306 }; 307 308 pinctrl_ese: pinctrl@14ca0000 { 309 compatible = "samsung,exynos7-pinctrl"; 310 reg = <0x14ca0000 0x1000>; 311 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 312 }; 313 314 pinctrl_fsys0: pinctrl@10e60000 { 315 compatible = "samsung,exynos7-pinctrl"; 316 reg = <0x10e60000 0x1000>; 317 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 318 }; 319 320 pinctrl_fsys1: pinctrl@15690000 { 321 compatible = "samsung,exynos7-pinctrl"; 322 reg = <0x15690000 0x1000>; 323 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 324 }; 325 326 pinctrl_bus1: pinctrl@14870000 { 327 compatible = "samsung,exynos7-pinctrl"; 328 reg = <0x14870000 0x1000>; 329 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 330 }; 331 332 hsi2c_0: hsi2c@13640000 { 333 compatible = "samsung,exynos7-hsi2c"; 334 reg = <0x13640000 0x1000>; 335 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&hs_i2c0_bus>; 340 clocks = <&clock_peric0 PCLK_HSI2C0>; 341 clock-names = "hsi2c"; 342 status = "disabled"; 343 }; 344 345 hsi2c_1: hsi2c@13650000 { 346 compatible = "samsung,exynos7-hsi2c"; 347 reg = <0x13650000 0x1000>; 348 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&hs_i2c1_bus>; 353 clocks = <&clock_peric0 PCLK_HSI2C1>; 354 clock-names = "hsi2c"; 355 status = "disabled"; 356 }; 357 358 hsi2c_2: hsi2c@14e60000 { 359 compatible = "samsung,exynos7-hsi2c"; 360 reg = <0x14e60000 0x1000>; 361 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&hs_i2c2_bus>; 366 clocks = <&clock_peric1 PCLK_HSI2C2>; 367 clock-names = "hsi2c"; 368 status = "disabled"; 369 }; 370 371 hsi2c_3: hsi2c@14e70000 { 372 compatible = "samsung,exynos7-hsi2c"; 373 reg = <0x14e70000 0x1000>; 374 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&hs_i2c3_bus>; 379 clocks = <&clock_peric1 PCLK_HSI2C3>; 380 clock-names = "hsi2c"; 381 status = "disabled"; 382 }; 383 384 hsi2c_4: hsi2c@13660000 { 385 compatible = "samsung,exynos7-hsi2c"; 386 reg = <0x13660000 0x1000>; 387 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&hs_i2c4_bus>; 392 clocks = <&clock_peric0 PCLK_HSI2C4>; 393 clock-names = "hsi2c"; 394 status = "disabled"; 395 }; 396 397 hsi2c_5: hsi2c@13670000 { 398 compatible = "samsung,exynos7-hsi2c"; 399 reg = <0x13670000 0x1000>; 400 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&hs_i2c5_bus>; 405 clocks = <&clock_peric0 PCLK_HSI2C5>; 406 clock-names = "hsi2c"; 407 status = "disabled"; 408 }; 409 410 hsi2c_6: hsi2c@14e00000 { 411 compatible = "samsung,exynos7-hsi2c"; 412 reg = <0x14e00000 0x1000>; 413 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&hs_i2c6_bus>; 418 clocks = <&clock_peric1 PCLK_HSI2C6>; 419 clock-names = "hsi2c"; 420 status = "disabled"; 421 }; 422 423 hsi2c_7: hsi2c@13e10000 { 424 compatible = "samsung,exynos7-hsi2c"; 425 reg = <0x13e10000 0x1000>; 426 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&hs_i2c7_bus>; 431 clocks = <&clock_peric1 PCLK_HSI2C7>; 432 clock-names = "hsi2c"; 433 status = "disabled"; 434 }; 435 436 hsi2c_8: hsi2c@14e20000 { 437 compatible = "samsung,exynos7-hsi2c"; 438 reg = <0x14e20000 0x1000>; 439 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&hs_i2c8_bus>; 444 clocks = <&clock_peric1 PCLK_HSI2C8>; 445 clock-names = "hsi2c"; 446 status = "disabled"; 447 }; 448 449 hsi2c_9: hsi2c@13680000 { 450 compatible = "samsung,exynos7-hsi2c"; 451 reg = <0x13680000 0x1000>; 452 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&hs_i2c9_bus>; 457 clocks = <&clock_peric0 PCLK_HSI2C9>; 458 clock-names = "hsi2c"; 459 status = "disabled"; 460 }; 461 462 hsi2c_10: hsi2c@13690000 { 463 compatible = "samsung,exynos7-hsi2c"; 464 reg = <0x13690000 0x1000>; 465 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&hs_i2c10_bus>; 470 clocks = <&clock_peric0 PCLK_HSI2C10>; 471 clock-names = "hsi2c"; 472 status = "disabled"; 473 }; 474 475 hsi2c_11: hsi2c@136a0000 { 476 compatible = "samsung,exynos7-hsi2c"; 477 reg = <0x136a0000 0x1000>; 478 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&hs_i2c11_bus>; 483 clocks = <&clock_peric0 PCLK_HSI2C11>; 484 clock-names = "hsi2c"; 485 status = "disabled"; 486 }; 487 488 pmu_system_controller: system-controller@105c0000 { 489 compatible = "samsung,exynos7-pmu", "syscon"; 490 reg = <0x105c0000 0x5000>; 491 492 reboot: syscon-reboot { 493 compatible = "syscon-reboot"; 494 regmap = <&pmu_system_controller>; 495 offset = <0x0400>; 496 mask = <0x1>; 497 }; 498 }; 499 500 rtc: rtc@10590000 { 501 compatible = "samsung,s3c6410-rtc"; 502 reg = <0x10590000 0x100>; 503 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clock_ccore PCLK_RTC>; 506 clock-names = "rtc"; 507 status = "disabled"; 508 }; 509 510 watchdog: watchdog@101d0000 { 511 compatible = "samsung,exynos7-wdt"; 512 reg = <0x101d0000 0x100>; 513 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&clock_peris PCLK_WDT>; 515 clock-names = "watchdog"; 516 samsung,syscon-phandle = <&pmu_system_controller>; 517 status = "disabled"; 518 }; 519 520 gpu: gpu@14ac0000 { 521 compatible = "samsung,exynos5433-mali", "arm,mali-t760"; 522 reg = <0x14ac0000 0x5000>; 523 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 526 interrupt-names = "job", "mmu", "gpu"; 527 status = "disabled"; 528 /* TODO: operating points for DVFS, cooling device */ 529 }; 530 531 mmc_0: mmc@15740000 { 532 compatible = "samsung,exynos7-dw-mshc-smu"; 533 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 reg = <0x15740000 0x2000>; 537 clocks = <&clock_fsys1 ACLK_MMC0>, 538 <&clock_top1 CLK_SCLK_MMC0>; 539 clock-names = "biu", "ciu"; 540 fifo-depth = <0x40>; 541 status = "disabled"; 542 }; 543 544 mmc_1: mmc@15750000 { 545 compatible = "samsung,exynos7-dw-mshc"; 546 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 reg = <0x15750000 0x2000>; 550 clocks = <&clock_fsys1 ACLK_MMC1>, 551 <&clock_top1 CLK_SCLK_MMC1>; 552 clock-names = "biu", "ciu"; 553 fifo-depth = <0x40>; 554 status = "disabled"; 555 }; 556 557 mmc_2: mmc@15560000 { 558 compatible = "samsung,exynos7-dw-mshc-smu"; 559 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 reg = <0x15560000 0x2000>; 563 clocks = <&clock_fsys0 ACLK_MMC2>, 564 <&clock_top1 CLK_SCLK_MMC2>; 565 clock-names = "biu", "ciu"; 566 fifo-depth = <0x40>; 567 status = "disabled"; 568 }; 569 570 adc: adc@13620000 { 571 compatible = "samsung,exynos7-adc"; 572 reg = <0x13620000 0x100>; 573 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&clock_peric0 PCLK_ADCIF>; 575 clock-names = "adc"; 576 #io-channel-cells = <1>; 577 io-channel-ranges; 578 status = "disabled"; 579 }; 580 581 pwm: pwm@136c0000 { 582 compatible = "samsung,exynos4210-pwm"; 583 reg = <0x136c0000 0x100>; 584 interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; 589 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 590 #pwm-cells = <3>; 591 clocks = <&clock_peric0 PCLK_PWM>; 592 clock-names = "timers"; 593 }; 594 595 tmuctrl_0: tmu@10060000 { 596 compatible = "samsung,exynos7-tmu"; 597 reg = <0x10060000 0x200>; 598 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&clock_peris PCLK_TMU>, 600 <&clock_peris SCLK_TMU>; 601 clock-names = "tmu_apbif", "tmu_sclk"; 602 #thermal-sensor-cells = <0>; 603 }; 604 605 thermal-zones { 606 atlas_thermal: cluster0-thermal { 607 polling-delay-passive = <0>; /* milliseconds */ 608 polling-delay = <0>; /* milliseconds */ 609 thermal-sensors = <&tmuctrl_0>; 610 #include "exynos7-trip-points.dtsi" 611 }; 612 }; 613 614 ufs: ufs@15570000 { 615 compatible = "samsung,exynos7-ufs"; 616 reg = <0x15570000 0x100>, /* 0: HCI standard */ 617 <0x15570100 0x100>, /* 1: Vendor specificed */ 618 <0x15571000 0x200>, /* 2: UNIPRO */ 619 <0x15572000 0x300>; /* 3: UFS protector */ 620 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 621 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&clock_fsys1 ACLK_UFS20_LINK>, 623 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; 624 clock-names = "core_clk", "sclk_unipro_main"; 625 freq-table-hz = <0 0>, <0 0>; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 628 phys = <&ufs_phy>; 629 phy-names = "ufs-phy"; 630 status = "disabled"; 631 }; 632 633 ufs_phy: ufs-phy@15571800 { 634 compatible = "samsung,exynos7-ufs-phy"; 635 reg = <0x15571800 0x240>; 636 reg-names = "phy-pma"; 637 samsung,pmu-syscon = <&pmu_system_controller>; 638 #phy-cells = <0>; 639 clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, 640 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, 641 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, 642 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; 643 clock-names = "ref_clk", "rx1_symbol_clk", 644 "rx0_symbol_clk", 645 "tx0_symbol_clk"; 646 }; 647 648 usbdrd_phy: phy@15500000 { 649 compatible = "samsung,exynos7-usbdrd-phy"; 650 reg = <0x15500000 0x100>; 651 clocks = <&clock_fsys0 ACLK_USBDRD300>, 652 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, 653 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, 654 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, 655 <&clock_fsys0 SCLK_USBDRD300_REFCLK>; 656 clock-names = "phy", "ref", "phy_pipe", 657 "phy_utmi", "itp"; 658 samsung,pmu-syscon = <&pmu_system_controller>; 659 #phy-cells = <1>; 660 }; 661 662 usbdrd3 { 663 compatible = "samsung,exynos7-dwusb3"; 664 clocks = <&clock_fsys0 ACLK_USBDRD300>, 665 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, 666 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; 667 clock-names = "usbdrd30", "usbdrd30_susp_clk", 668 "usbdrd30_axius_clk"; 669 #address-cells = <1>; 670 #size-cells = <1>; 671 ranges; 672 673 dwc3@15400000 { 674 compatible = "snps,dwc3"; 675 reg = <0x15400000 0x10000>; 676 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 677 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 678 phy-names = "usb2-phy", "usb3-phy"; 679 }; 680 }; 681 }; 682 683 timer { 684 compatible = "arm,armv8-timer"; 685 interrupts = <GIC_PPI 13 686 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 687 <GIC_PPI 14 688 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 689 <GIC_PPI 11 690 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 691 <GIC_PPI 10 692 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 693 }; 694}; 695 696#include "exynos7-pinctrl.dtsi" 697