1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's Exynos5433 SoC device tree source 4 * 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6 * 7 * Samsung's Exynos5433 SoC device nodes are listed in this file. 8 * Exynos5433 based board files can include this file and provide 9 * values for board specific bindings. 10 * 11 * Note: This file does not include device nodes for all the controllers in 12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, 13 * additional nodes can be added to this file. 14 */ 15 16#include <dt-bindings/clock/exynos5433.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18 19/ { 20 compatible = "samsung,exynos5433"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 interrupt-parent = <&gic>; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@100 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a53", "arm,armv8"; 33 enable-method = "psci"; 34 reg = <0x100>; 35 clock-frequency = <1300000000>; 36 clocks = <&cmu_apollo CLK_SCLK_APOLLO>; 37 clock-names = "apolloclk"; 38 operating-points-v2 = <&cluster_a53_opp_table>; 39 #cooling-cells = <2>; 40 }; 41 42 cpu1: cpu@101 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 enable-method = "psci"; 46 reg = <0x101>; 47 clock-frequency = <1300000000>; 48 operating-points-v2 = <&cluster_a53_opp_table>; 49 #cooling-cells = <2>; 50 }; 51 52 cpu2: cpu@102 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53", "arm,armv8"; 55 enable-method = "psci"; 56 reg = <0x102>; 57 clock-frequency = <1300000000>; 58 operating-points-v2 = <&cluster_a53_opp_table>; 59 #cooling-cells = <2>; 60 }; 61 62 cpu3: cpu@103 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53", "arm,armv8"; 65 enable-method = "psci"; 66 reg = <0x103>; 67 clock-frequency = <1300000000>; 68 operating-points-v2 = <&cluster_a53_opp_table>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu4: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a57", "arm,armv8"; 75 enable-method = "psci"; 76 reg = <0x0>; 77 clock-frequency = <1900000000>; 78 clocks = <&cmu_atlas CLK_SCLK_ATLAS>; 79 clock-names = "atlasclk"; 80 operating-points-v2 = <&cluster_a57_opp_table>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu5: cpu@1 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a57", "arm,armv8"; 87 enable-method = "psci"; 88 reg = <0x1>; 89 clock-frequency = <1900000000>; 90 operating-points-v2 = <&cluster_a57_opp_table>; 91 #cooling-cells = <2>; 92 }; 93 94 cpu6: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57", "arm,armv8"; 97 enable-method = "psci"; 98 reg = <0x2>; 99 clock-frequency = <1900000000>; 100 operating-points-v2 = <&cluster_a57_opp_table>; 101 #cooling-cells = <2>; 102 }; 103 104 cpu7: cpu@3 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a57", "arm,armv8"; 107 enable-method = "psci"; 108 reg = <0x3>; 109 clock-frequency = <1900000000>; 110 operating-points-v2 = <&cluster_a57_opp_table>; 111 #cooling-cells = <2>; 112 }; 113 }; 114 115 cluster_a53_opp_table: opp_table0 { 116 compatible = "operating-points-v2"; 117 opp-shared; 118 119 opp-400000000 { 120 opp-hz = /bits/ 64 <400000000>; 121 opp-microvolt = <900000>; 122 }; 123 opp-500000000 { 124 opp-hz = /bits/ 64 <500000000>; 125 opp-microvolt = <925000>; 126 }; 127 opp-600000000 { 128 opp-hz = /bits/ 64 <600000000>; 129 opp-microvolt = <950000>; 130 }; 131 opp-700000000 { 132 opp-hz = /bits/ 64 <700000000>; 133 opp-microvolt = <975000>; 134 }; 135 opp-800000000 { 136 opp-hz = /bits/ 64 <800000000>; 137 opp-microvolt = <1000000>; 138 }; 139 opp-900000000 { 140 opp-hz = /bits/ 64 <900000000>; 141 opp-microvolt = <1050000>; 142 }; 143 opp-1000000000 { 144 opp-hz = /bits/ 64 <1000000000>; 145 opp-microvolt = <1075000>; 146 }; 147 opp-1100000000 { 148 opp-hz = /bits/ 64 <1100000000>; 149 opp-microvolt = <1112500>; 150 }; 151 opp-1200000000 { 152 opp-hz = /bits/ 64 <1200000000>; 153 opp-microvolt = <1112500>; 154 }; 155 opp-1300000000 { 156 opp-hz = /bits/ 64 <1300000000>; 157 opp-microvolt = <1150000>; 158 }; 159 }; 160 161 cluster_a57_opp_table: opp_table1 { 162 compatible = "operating-points-v2"; 163 opp-shared; 164 165 opp-500000000 { 166 opp-hz = /bits/ 64 <500000000>; 167 opp-microvolt = <900000>; 168 }; 169 opp-600000000 { 170 opp-hz = /bits/ 64 <600000000>; 171 opp-microvolt = <900000>; 172 }; 173 opp-700000000 { 174 opp-hz = /bits/ 64 <700000000>; 175 opp-microvolt = <912500>; 176 }; 177 opp-800000000 { 178 opp-hz = /bits/ 64 <800000000>; 179 opp-microvolt = <912500>; 180 }; 181 opp-900000000 { 182 opp-hz = /bits/ 64 <900000000>; 183 opp-microvolt = <937500>; 184 }; 185 opp-1000000000 { 186 opp-hz = /bits/ 64 <1000000000>; 187 opp-microvolt = <975000>; 188 }; 189 opp-1100000000 { 190 opp-hz = /bits/ 64 <1100000000>; 191 opp-microvolt = <1012500>; 192 }; 193 opp-1200000000 { 194 opp-hz = /bits/ 64 <1200000000>; 195 opp-microvolt = <1037500>; 196 }; 197 opp-1300000000 { 198 opp-hz = /bits/ 64 <1300000000>; 199 opp-microvolt = <1062500>; 200 }; 201 opp-1400000000 { 202 opp-hz = /bits/ 64 <1400000000>; 203 opp-microvolt = <1087500>; 204 }; 205 opp-1500000000 { 206 opp-hz = /bits/ 64 <1500000000>; 207 opp-microvolt = <1125000>; 208 }; 209 opp-1600000000 { 210 opp-hz = /bits/ 64 <1600000000>; 211 opp-microvolt = <1137500>; 212 }; 213 opp-1700000000 { 214 opp-hz = /bits/ 64 <1700000000>; 215 opp-microvolt = <1175000>; 216 }; 217 opp-1800000000 { 218 opp-hz = /bits/ 64 <1800000000>; 219 opp-microvolt = <1212500>; 220 }; 221 opp-1900000000 { 222 opp-hz = /bits/ 64 <1900000000>; 223 opp-microvolt = <1262500>; 224 }; 225 }; 226 227 psci { 228 compatible = "arm,psci"; 229 method = "smc"; 230 cpu_off = <0x84000002>; 231 cpu_on = <0xC4000003>; 232 }; 233 234 soc: soc { 235 compatible = "simple-bus"; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 ranges; 239 240 arm_a53_pmu { 241 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 242 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 246 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 247 }; 248 249 arm_a57_pmu { 250 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; 251 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 255 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 256 }; 257 258 chipid@10000000 { 259 compatible = "samsung,exynos4210-chipid"; 260 reg = <0x10000000 0x100>; 261 }; 262 263 xxti: xxti { 264 compatible = "fixed-clock"; 265 clock-output-names = "oscclk"; 266 #clock-cells = <0>; 267 }; 268 269 cmu_top: clock-controller@10030000 { 270 compatible = "samsung,exynos5433-cmu-top"; 271 reg = <0x10030000 0x1000>; 272 #clock-cells = <1>; 273 274 clock-names = "oscclk", 275 "sclk_mphy_pll", 276 "sclk_mfc_pll", 277 "sclk_bus_pll"; 278 clocks = <&xxti>, 279 <&cmu_cpif CLK_SCLK_MPHY_PLL>, 280 <&cmu_mif CLK_SCLK_MFC_PLL>, 281 <&cmu_mif CLK_SCLK_BUS_PLL>; 282 }; 283 284 cmu_cpif: clock-controller@10fc0000 { 285 compatible = "samsung,exynos5433-cmu-cpif"; 286 reg = <0x10fc0000 0x1000>; 287 #clock-cells = <1>; 288 289 clock-names = "oscclk"; 290 clocks = <&xxti>; 291 }; 292 293 cmu_mif: clock-controller@105b0000 { 294 compatible = "samsung,exynos5433-cmu-mif"; 295 reg = <0x105b0000 0x2000>; 296 #clock-cells = <1>; 297 298 clock-names = "oscclk", 299 "sclk_mphy_pll"; 300 clocks = <&xxti>, 301 <&cmu_cpif CLK_SCLK_MPHY_PLL>; 302 }; 303 304 cmu_peric: clock-controller@14c80000 { 305 compatible = "samsung,exynos5433-cmu-peric"; 306 reg = <0x14c80000 0x1000>; 307 #clock-cells = <1>; 308 }; 309 310 cmu_peris: clock-controller@10040000 { 311 compatible = "samsung,exynos5433-cmu-peris"; 312 reg = <0x10040000 0x1000>; 313 #clock-cells = <1>; 314 }; 315 316 cmu_fsys: clock-controller@156e0000 { 317 compatible = "samsung,exynos5433-cmu-fsys"; 318 reg = <0x156e0000 0x1000>; 319 #clock-cells = <1>; 320 321 clock-names = "oscclk", 322 "sclk_ufs_mphy", 323 "aclk_fsys_200", 324 "sclk_pcie_100_fsys", 325 "sclk_ufsunipro_fsys", 326 "sclk_mmc2_fsys", 327 "sclk_mmc1_fsys", 328 "sclk_mmc0_fsys", 329 "sclk_usbhost30_fsys", 330 "sclk_usbdrd30_fsys"; 331 clocks = <&xxti>, 332 <&cmu_cpif CLK_SCLK_UFS_MPHY>, 333 <&cmu_top CLK_ACLK_FSYS_200>, 334 <&cmu_top CLK_SCLK_PCIE_100_FSYS>, 335 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, 336 <&cmu_top CLK_SCLK_MMC2_FSYS>, 337 <&cmu_top CLK_SCLK_MMC1_FSYS>, 338 <&cmu_top CLK_SCLK_MMC0_FSYS>, 339 <&cmu_top CLK_SCLK_USBHOST30_FSYS>, 340 <&cmu_top CLK_SCLK_USBDRD30_FSYS>; 341 }; 342 343 cmu_g2d: clock-controller@12460000 { 344 compatible = "samsung,exynos5433-cmu-g2d"; 345 reg = <0x12460000 0x1000>; 346 #clock-cells = <1>; 347 348 clock-names = "oscclk", 349 "aclk_g2d_266", 350 "aclk_g2d_400"; 351 clocks = <&xxti>, 352 <&cmu_top CLK_ACLK_G2D_266>, 353 <&cmu_top CLK_ACLK_G2D_400>; 354 power-domains = <&pd_g2d>; 355 }; 356 357 cmu_disp: clock-controller@13b90000 { 358 compatible = "samsung,exynos5433-cmu-disp"; 359 reg = <0x13b90000 0x1000>; 360 #clock-cells = <1>; 361 362 clock-names = "oscclk", 363 "sclk_dsim1_disp", 364 "sclk_dsim0_disp", 365 "sclk_dsd_disp", 366 "sclk_decon_tv_eclk_disp", 367 "sclk_decon_vclk_disp", 368 "sclk_decon_eclk_disp", 369 "sclk_decon_tv_vclk_disp", 370 "aclk_disp_333"; 371 clocks = <&xxti>, 372 <&cmu_mif CLK_SCLK_DSIM1_DISP>, 373 <&cmu_mif CLK_SCLK_DSIM0_DISP>, 374 <&cmu_mif CLK_SCLK_DSD_DISP>, 375 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 376 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, 377 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 378 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, 379 <&cmu_mif CLK_ACLK_DISP_333>; 380 power-domains = <&pd_disp>; 381 }; 382 383 cmu_aud: clock-controller@114c0000 { 384 compatible = "samsung,exynos5433-cmu-aud"; 385 reg = <0x114c0000 0x1000>; 386 #clock-cells = <1>; 387 clock-names = "oscclk", "fout_aud_pll"; 388 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; 389 power-domains = <&pd_aud>; 390 }; 391 392 cmu_bus0: clock-controller@13600000 { 393 compatible = "samsung,exynos5433-cmu-bus0"; 394 reg = <0x13600000 0x1000>; 395 #clock-cells = <1>; 396 397 clock-names = "aclk_bus0_400"; 398 clocks = <&cmu_top CLK_ACLK_BUS0_400>; 399 }; 400 401 cmu_bus1: clock-controller@14800000 { 402 compatible = "samsung,exynos5433-cmu-bus1"; 403 reg = <0x14800000 0x1000>; 404 #clock-cells = <1>; 405 406 clock-names = "aclk_bus1_400"; 407 clocks = <&cmu_top CLK_ACLK_BUS1_400>; 408 }; 409 410 cmu_bus2: clock-controller@13400000 { 411 compatible = "samsung,exynos5433-cmu-bus2"; 412 reg = <0x13400000 0x1000>; 413 #clock-cells = <1>; 414 415 clock-names = "oscclk", "aclk_bus2_400"; 416 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; 417 }; 418 419 cmu_g3d: clock-controller@14aa0000 { 420 compatible = "samsung,exynos5433-cmu-g3d"; 421 reg = <0x14aa0000 0x2000>; 422 #clock-cells = <1>; 423 424 clock-names = "oscclk", "aclk_g3d_400"; 425 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; 426 power-domains = <&pd_g3d>; 427 }; 428 429 cmu_gscl: clock-controller@13cf0000 { 430 compatible = "samsung,exynos5433-cmu-gscl"; 431 reg = <0x13cf0000 0x1000>; 432 #clock-cells = <1>; 433 434 clock-names = "oscclk", 435 "aclk_gscl_111", 436 "aclk_gscl_333"; 437 clocks = <&xxti>, 438 <&cmu_top CLK_ACLK_GSCL_111>, 439 <&cmu_top CLK_ACLK_GSCL_333>; 440 power-domains = <&pd_gscl>; 441 }; 442 443 cmu_apollo: clock-controller@11900000 { 444 compatible = "samsung,exynos5433-cmu-apollo"; 445 reg = <0x11900000 0x2000>; 446 #clock-cells = <1>; 447 448 clock-names = "oscclk", "sclk_bus_pll_apollo"; 449 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; 450 }; 451 452 cmu_atlas: clock-controller@11800000 { 453 compatible = "samsung,exynos5433-cmu-atlas"; 454 reg = <0x11800000 0x2000>; 455 #clock-cells = <1>; 456 457 clock-names = "oscclk", "sclk_bus_pll_atlas"; 458 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; 459 }; 460 461 cmu_mscl: clock-controller@150d0000 { 462 compatible = "samsung,exynos5433-cmu-mscl"; 463 reg = <0x150d0000 0x1000>; 464 #clock-cells = <1>; 465 466 clock-names = "oscclk", 467 "sclk_jpeg_mscl", 468 "aclk_mscl_400"; 469 clocks = <&xxti>, 470 <&cmu_top CLK_SCLK_JPEG_MSCL>, 471 <&cmu_top CLK_ACLK_MSCL_400>; 472 power-domains = <&pd_mscl>; 473 }; 474 475 cmu_mfc: clock-controller@15280000 { 476 compatible = "samsung,exynos5433-cmu-mfc"; 477 reg = <0x15280000 0x1000>; 478 #clock-cells = <1>; 479 480 clock-names = "oscclk", "aclk_mfc_400"; 481 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; 482 power-domains = <&pd_mfc>; 483 }; 484 485 cmu_hevc: clock-controller@14f80000 { 486 compatible = "samsung,exynos5433-cmu-hevc"; 487 reg = <0x14f80000 0x1000>; 488 #clock-cells = <1>; 489 490 clock-names = "oscclk", "aclk_hevc_400"; 491 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; 492 power-domains = <&pd_hevc>; 493 }; 494 495 cmu_isp: clock-controller@146d0000 { 496 compatible = "samsung,exynos5433-cmu-isp"; 497 reg = <0x146d0000 0x1000>; 498 #clock-cells = <1>; 499 500 clock-names = "oscclk", 501 "aclk_isp_dis_400", 502 "aclk_isp_400"; 503 clocks = <&xxti>, 504 <&cmu_top CLK_ACLK_ISP_DIS_400>, 505 <&cmu_top CLK_ACLK_ISP_400>; 506 power-domains = <&pd_isp>; 507 }; 508 509 cmu_cam0: clock-controller@120d0000 { 510 compatible = "samsung,exynos5433-cmu-cam0"; 511 reg = <0x120d0000 0x1000>; 512 #clock-cells = <1>; 513 514 clock-names = "oscclk", 515 "aclk_cam0_333", 516 "aclk_cam0_400", 517 "aclk_cam0_552"; 518 clocks = <&xxti>, 519 <&cmu_top CLK_ACLK_CAM0_333>, 520 <&cmu_top CLK_ACLK_CAM0_400>, 521 <&cmu_top CLK_ACLK_CAM0_552>; 522 power-domains = <&pd_cam0>; 523 }; 524 525 cmu_cam1: clock-controller@145d0000 { 526 compatible = "samsung,exynos5433-cmu-cam1"; 527 reg = <0x145d0000 0x1000>; 528 #clock-cells = <1>; 529 530 clock-names = "oscclk", 531 "sclk_isp_uart_cam1", 532 "sclk_isp_spi1_cam1", 533 "sclk_isp_spi0_cam1", 534 "aclk_cam1_333", 535 "aclk_cam1_400", 536 "aclk_cam1_552"; 537 clocks = <&xxti>, 538 <&cmu_top CLK_SCLK_ISP_UART_CAM1>, 539 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, 540 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, 541 <&cmu_top CLK_ACLK_CAM1_333>, 542 <&cmu_top CLK_ACLK_CAM1_400>, 543 <&cmu_top CLK_ACLK_CAM1_552>; 544 power-domains = <&pd_cam1>; 545 }; 546 547 pd_gscl: power-domain@105c4000 { 548 compatible = "samsung,exynos5433-pd"; 549 reg = <0x105c4000 0x20>; 550 #power-domain-cells = <0>; 551 label = "GSCL"; 552 }; 553 554 pd_cam0: power-domain@105c4020 { 555 compatible = "samsung,exynos5433-pd"; 556 reg = <0x105c4020 0x20>; 557 #power-domain-cells = <0>; 558 power-domains = <&pd_cam1>; 559 label = "CAM0"; 560 }; 561 562 pd_mscl: power-domain@105c4040 { 563 compatible = "samsung,exynos5433-pd"; 564 reg = <0x105c4040 0x20>; 565 #power-domain-cells = <0>; 566 label = "MSCL"; 567 }; 568 569 pd_g3d: power-domain@105c4060 { 570 compatible = "samsung,exynos5433-pd"; 571 reg = <0x105c4060 0x20>; 572 #power-domain-cells = <0>; 573 label = "G3D"; 574 }; 575 576 pd_disp: power-domain@105c4080 { 577 compatible = "samsung,exynos5433-pd"; 578 reg = <0x105c4080 0x20>; 579 #power-domain-cells = <0>; 580 label = "DISP"; 581 }; 582 583 pd_cam1: power-domain@105c40a0 { 584 compatible = "samsung,exynos5433-pd"; 585 reg = <0x105c40a0 0x20>; 586 #power-domain-cells = <0>; 587 label = "CAM1"; 588 }; 589 590 pd_aud: power-domain@105c40c0 { 591 compatible = "samsung,exynos5433-pd"; 592 reg = <0x105c40c0 0x20>; 593 #power-domain-cells = <0>; 594 label = "AUD"; 595 }; 596 597 pd_g2d: power-domain@105c4120 { 598 compatible = "samsung,exynos5433-pd"; 599 reg = <0x105c4120 0x20>; 600 #power-domain-cells = <0>; 601 label = "G2D"; 602 }; 603 604 pd_isp: power-domain@105c4140 { 605 compatible = "samsung,exynos5433-pd"; 606 reg = <0x105c4140 0x20>; 607 #power-domain-cells = <0>; 608 power-domains = <&pd_cam0>; 609 label = "ISP"; 610 }; 611 612 pd_mfc: power-domain@105c4180 { 613 compatible = "samsung,exynos5433-pd"; 614 reg = <0x105c4180 0x20>; 615 #power-domain-cells = <0>; 616 label = "MFC"; 617 }; 618 619 pd_hevc: power-domain@105c41c0 { 620 compatible = "samsung,exynos5433-pd"; 621 reg = <0x105c41c0 0x20>; 622 #power-domain-cells = <0>; 623 label = "HEVC"; 624 }; 625 626 tmu_atlas0: tmu@10060000 { 627 compatible = "samsung,exynos5433-tmu"; 628 reg = <0x10060000 0x200>; 629 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, 631 <&cmu_peris CLK_SCLK_TMU0>; 632 clock-names = "tmu_apbif", "tmu_sclk"; 633 #thermal-sensor-cells = <0>; 634 status = "disabled"; 635 }; 636 637 tmu_atlas1: tmu@10068000 { 638 compatible = "samsung,exynos5433-tmu"; 639 reg = <0x10068000 0x200>; 640 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, 642 <&cmu_peris CLK_SCLK_TMU0>; 643 clock-names = "tmu_apbif", "tmu_sclk"; 644 #thermal-sensor-cells = <0>; 645 status = "disabled"; 646 }; 647 648 tmu_g3d: tmu@10070000 { 649 compatible = "samsung,exynos5433-tmu"; 650 reg = <0x10070000 0x200>; 651 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, 653 <&cmu_peris CLK_SCLK_TMU1>; 654 clock-names = "tmu_apbif", "tmu_sclk"; 655 #thermal-sensor-cells = <0>; 656 status = "disabled"; 657 }; 658 659 tmu_apollo: tmu@10078000 { 660 compatible = "samsung,exynos5433-tmu"; 661 reg = <0x10078000 0x200>; 662 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, 664 <&cmu_peris CLK_SCLK_TMU1>; 665 clock-names = "tmu_apbif", "tmu_sclk"; 666 #thermal-sensor-cells = <0>; 667 status = "disabled"; 668 }; 669 670 tmu_isp: tmu@1007c000 { 671 compatible = "samsung,exynos5433-tmu"; 672 reg = <0x1007c000 0x200>; 673 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, 675 <&cmu_peris CLK_SCLK_TMU1>; 676 clock-names = "tmu_apbif", "tmu_sclk"; 677 #thermal-sensor-cells = <0>; 678 status = "disabled"; 679 }; 680 681 mct@101c0000 { 682 compatible = "samsung,exynos4210-mct"; 683 reg = <0x101c0000 0x800>; 684 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; 697 clock-names = "fin_pll", "mct"; 698 }; 699 700 ppmu_d0_cpu: ppmu@10480000 { 701 compatible = "samsung,exynos-ppmu-v2"; 702 reg = <0x10480000 0x2000>; 703 status = "disabled"; 704 }; 705 706 ppmu_d0_general: ppmu@10490000 { 707 compatible = "samsung,exynos-ppmu-v2"; 708 reg = <0x10490000 0x2000>; 709 status = "disabled"; 710 }; 711 712 ppmu_d1_cpu: ppmu@104b0000 { 713 compatible = "samsung,exynos-ppmu-v2"; 714 reg = <0x104b0000 0x2000>; 715 status = "disabled"; 716 }; 717 718 ppmu_d1_general: ppmu@104c0000 { 719 compatible = "samsung,exynos-ppmu-v2"; 720 reg = <0x104c0000 0x2000>; 721 status = "disabled"; 722 }; 723 724 pinctrl_alive: pinctrl@10580000 { 725 compatible = "samsung,exynos5433-pinctrl"; 726 reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 727 728 wakeup-interrupt-controller { 729 compatible = "samsung,exynos7-wakeup-eint"; 730 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 731 }; 732 }; 733 734 pinctrl_aud: pinctrl@114b0000 { 735 compatible = "samsung,exynos5433-pinctrl"; 736 reg = <0x114b0000 0x1000>; 737 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 738 power-domains = <&pd_aud>; 739 }; 740 741 pinctrl_cpif: pinctrl@10fe0000 { 742 compatible = "samsung,exynos5433-pinctrl"; 743 reg = <0x10fe0000 0x1000>; 744 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 745 }; 746 747 pinctrl_ese: pinctrl@14ca0000 { 748 compatible = "samsung,exynos5433-pinctrl"; 749 reg = <0x14ca0000 0x1000>; 750 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 751 }; 752 753 pinctrl_finger: pinctrl@14cb0000 { 754 compatible = "samsung,exynos5433-pinctrl"; 755 reg = <0x14cb0000 0x1000>; 756 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 757 }; 758 759 pinctrl_fsys: pinctrl@15690000 { 760 compatible = "samsung,exynos5433-pinctrl"; 761 reg = <0x15690000 0x1000>; 762 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 763 }; 764 765 pinctrl_imem: pinctrl@11090000 { 766 compatible = "samsung,exynos5433-pinctrl"; 767 reg = <0x11090000 0x1000>; 768 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 769 }; 770 771 pinctrl_nfc: pinctrl@14cd0000 { 772 compatible = "samsung,exynos5433-pinctrl"; 773 reg = <0x14cd0000 0x1000>; 774 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 775 }; 776 777 pinctrl_peric: pinctrl@14cc0000 { 778 compatible = "samsung,exynos5433-pinctrl"; 779 reg = <0x14cc0000 0x1100>; 780 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 781 }; 782 783 pinctrl_touch: pinctrl@14ce0000 { 784 compatible = "samsung,exynos5433-pinctrl"; 785 reg = <0x14ce0000 0x1100>; 786 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 787 }; 788 789 pmu_system_controller: system-controller@105c0000 { 790 compatible = "samsung,exynos5433-pmu", "syscon"; 791 reg = <0x105c0000 0x5008>; 792 #clock-cells = <1>; 793 clock-names = "clkout16"; 794 clocks = <&xxti>; 795 796 reboot: syscon-reboot { 797 compatible = "syscon-reboot"; 798 regmap = <&pmu_system_controller>; 799 offset = <0x400>; /* SWRESET */ 800 mask = <0x1>; 801 }; 802 }; 803 804 gic: interrupt-controller@11001000 { 805 compatible = "arm,gic-400"; 806 #interrupt-cells = <3>; 807 interrupt-controller; 808 reg = <0x11001000 0x1000>, 809 <0x11002000 0x2000>, 810 <0x11004000 0x2000>, 811 <0x11006000 0x2000>; 812 interrupts = <GIC_PPI 9 0xf04>; 813 }; 814 815 mipi_phy: video-phy { 816 compatible = "samsung,exynos5433-mipi-video-phy"; 817 #phy-cells = <1>; 818 samsung,pmu-syscon = <&pmu_system_controller>; 819 samsung,cam0-sysreg = <&syscon_cam0>; 820 samsung,cam1-sysreg = <&syscon_cam1>; 821 samsung,disp-sysreg = <&syscon_disp>; 822 }; 823 824 decon: decon@13800000 { 825 compatible = "samsung,exynos5433-decon"; 826 reg = <0x13800000 0x2104>; 827 clocks = <&cmu_disp CLK_PCLK_DECON>, 828 <&cmu_disp CLK_ACLK_DECON>, 829 <&cmu_disp CLK_ACLK_SMMU_DECON0X>, 830 <&cmu_disp CLK_ACLK_XIU_DECON0X>, 831 <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 832 <&cmu_disp CLK_ACLK_SMMU_DECON1X>, 833 <&cmu_disp CLK_ACLK_XIU_DECON1X>, 834 <&cmu_disp CLK_PCLK_SMMU_DECON1X>, 835 <&cmu_disp CLK_SCLK_DECON_VCLK>, 836 <&cmu_disp CLK_SCLK_DECON_ECLK>; 837 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", 838 "aclk_xiu_decon0x", "pclk_smmu_decon0x", 839 "aclk_smmu_decon1x", "aclk_xiu_decon1x", 840 "pclk_smmu_decon1x", "sclk_decon_vclk", 841 "sclk_decon_eclk"; 842 power-domains = <&pd_disp>; 843 interrupt-names = "fifo", "vsync", "lcd_sys"; 844 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 847 samsung,disp-sysreg = <&syscon_disp>; 848 status = "disabled"; 849 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; 850 iommu-names = "m0", "m1"; 851 852 ports { 853 #address-cells = <1>; 854 #size-cells = <0>; 855 856 port@0 { 857 reg = <0>; 858 decon_to_mic: endpoint { 859 remote-endpoint = 860 <&mic_to_decon>; 861 }; 862 }; 863 }; 864 }; 865 866 decon_tv: decon@13880000 { 867 compatible = "samsung,exynos5433-decon-tv"; 868 reg = <0x13880000 0x20b8>; 869 clocks = <&cmu_disp CLK_PCLK_DECON_TV>, 870 <&cmu_disp CLK_ACLK_DECON_TV>, 871 <&cmu_disp CLK_ACLK_SMMU_TV0X>, 872 <&cmu_disp CLK_ACLK_XIU_TV0X>, 873 <&cmu_disp CLK_PCLK_SMMU_TV0X>, 874 <&cmu_disp CLK_ACLK_SMMU_TV1X>, 875 <&cmu_disp CLK_ACLK_XIU_TV1X>, 876 <&cmu_disp CLK_PCLK_SMMU_TV1X>, 877 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, 878 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>; 879 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", 880 "aclk_xiu_decon0x", "pclk_smmu_decon0x", 881 "aclk_smmu_decon1x", "aclk_xiu_decon1x", 882 "pclk_smmu_decon1x", "sclk_decon_vclk", 883 "sclk_decon_eclk"; 884 samsung,disp-sysreg = <&syscon_disp>; 885 power-domains = <&pd_disp>; 886 interrupt-names = "fifo", "vsync", "lcd_sys"; 887 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 890 status = "disabled"; 891 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>; 892 iommu-names = "m0", "m1"; 893 }; 894 895 dsi: dsi@13900000 { 896 compatible = "samsung,exynos5433-mipi-dsi"; 897 reg = <0x13900000 0xC0>; 898 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 899 phys = <&mipi_phy 1>; 900 phy-names = "dsim"; 901 clocks = <&cmu_disp CLK_PCLK_DSIM0>, 902 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, 903 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, 904 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, 905 <&cmu_disp CLK_SCLK_DSIM0>; 906 clock-names = "bus_clk", 907 "phyclk_mipidphy0_bitclkdiv8", 908 "phyclk_mipidphy0_rxclkesc0", 909 "sclk_rgb_vclk_to_dsim0", 910 "sclk_mipi"; 911 power-domains = <&pd_disp>; 912 status = "disabled"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 916 ports { 917 #address-cells = <1>; 918 #size-cells = <0>; 919 920 port@0 { 921 reg = <0>; 922 dsi_to_mic: endpoint { 923 remote-endpoint = <&mic_to_dsi>; 924 }; 925 }; 926 }; 927 }; 928 929 mic: mic@13930000 { 930 compatible = "samsung,exynos5433-mic"; 931 reg = <0x13930000 0x48>; 932 clocks = <&cmu_disp CLK_PCLK_MIC0>, 933 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; 934 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; 935 power-domains = <&pd_disp>; 936 samsung,disp-syscon = <&syscon_disp>; 937 status = "disabled"; 938 939 ports { 940 #address-cells = <1>; 941 #size-cells = <0>; 942 943 port@0 { 944 reg = <0>; 945 mic_to_decon: endpoint { 946 remote-endpoint = 947 <&decon_to_mic>; 948 }; 949 }; 950 951 port@1 { 952 reg = <1>; 953 mic_to_dsi: endpoint { 954 remote-endpoint = <&dsi_to_mic>; 955 }; 956 }; 957 }; 958 }; 959 960 hdmi: hdmi@13970000 { 961 compatible = "samsung,exynos5433-hdmi"; 962 reg = <0x13970000 0x70000>; 963 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&cmu_disp CLK_PCLK_HDMI>, 965 <&cmu_disp CLK_PCLK_HDMIPHY>, 966 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, 967 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, 968 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, 969 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, 970 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, 971 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, 972 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>; 973 clock-names = "hdmi_pclk", "hdmi_i_pclk", 974 "i_tmds_clk", "i_pixel_clk", 975 "tmds_clko", "tmds_clko_user", 976 "pixel_clko", "pixel_clko_user", 977 "oscclk", "i_spdif_clk"; 978 phy = <&hdmiphy>; 979 ddc = <&hsi2c_11>; 980 samsung,syscon-phandle = <&pmu_system_controller>; 981 samsung,sysreg-phandle = <&syscon_disp>; 982 #sound-dai-cells = <0>; 983 status = "disabled"; 984 }; 985 986 hdmiphy: hdmiphy@13af0000 { 987 reg = <0x13af0000 0x80>; 988 }; 989 990 syscon_disp: syscon@13b80000 { 991 compatible = "syscon"; 992 reg = <0x13b80000 0x1010>; 993 }; 994 995 syscon_cam0: syscon@120f0000 { 996 compatible = "syscon"; 997 reg = <0x120f0000 0x1020>; 998 }; 999 1000 syscon_cam1: syscon@145f0000 { 1001 compatible = "syscon"; 1002 reg = <0x145f0000 0x1038>; 1003 }; 1004 1005 gsc_0: video-scaler@13c00000 { 1006 compatible = "samsung,exynos5433-gsc"; 1007 reg = <0x13c00000 0x1000>; 1008 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1009 clock-names = "pclk", "aclk", "aclk_xiu", 1010 "aclk_gsclbend"; 1011 clocks = <&cmu_gscl CLK_PCLK_GSCL0>, 1012 <&cmu_gscl CLK_ACLK_GSCL0>, 1013 <&cmu_gscl CLK_ACLK_XIU_GSCLX>, 1014 <&cmu_gscl CLK_ACLK_GSCLBEND_333>; 1015 iommus = <&sysmmu_gscl0>; 1016 power-domains = <&pd_gscl>; 1017 }; 1018 1019 gsc_1: video-scaler@13c10000 { 1020 compatible = "samsung,exynos5433-gsc"; 1021 reg = <0x13c10000 0x1000>; 1022 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1023 clock-names = "pclk", "aclk", "aclk_xiu", 1024 "aclk_gsclbend"; 1025 clocks = <&cmu_gscl CLK_PCLK_GSCL1>, 1026 <&cmu_gscl CLK_ACLK_GSCL1>, 1027 <&cmu_gscl CLK_ACLK_XIU_GSCLX>, 1028 <&cmu_gscl CLK_ACLK_GSCLBEND_333>; 1029 iommus = <&sysmmu_gscl1>; 1030 power-domains = <&pd_gscl>; 1031 }; 1032 1033 gsc_2: video-scaler@13c20000 { 1034 compatible = "samsung,exynos5433-gsc"; 1035 reg = <0x13c20000 0x1000>; 1036 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1037 clock-names = "pclk", "aclk", "aclk_xiu", 1038 "aclk_gsclbend"; 1039 clocks = <&cmu_gscl CLK_PCLK_GSCL2>, 1040 <&cmu_gscl CLK_ACLK_GSCL2>, 1041 <&cmu_gscl CLK_ACLK_XIU_GSCLX>, 1042 <&cmu_gscl CLK_ACLK_GSCLBEND_333>; 1043 iommus = <&sysmmu_gscl2>; 1044 power-domains = <&pd_gscl>; 1045 }; 1046 1047 scaler_0: scaler@15000000 { 1048 compatible = "samsung,exynos5433-scaler"; 1049 reg = <0x15000000 0x1294>; 1050 interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>; 1051 clock-names = "pclk", "aclk", "aclk_xiu"; 1052 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>, 1053 <&cmu_mscl CLK_ACLK_M2MSCALER0>, 1054 <&cmu_mscl CLK_ACLK_XIU_MSCLX>; 1055 iommus = <&sysmmu_scaler_0>; 1056 power-domains = <&pd_mscl>; 1057 }; 1058 1059 scaler_1: scaler@15010000 { 1060 compatible = "samsung,exynos5433-scaler"; 1061 reg = <0x15010000 0x1294>; 1062 interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>; 1063 clock-names = "pclk", "aclk", "aclk_xiu"; 1064 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>, 1065 <&cmu_mscl CLK_ACLK_M2MSCALER1>, 1066 <&cmu_mscl CLK_ACLK_XIU_MSCLX>; 1067 iommus = <&sysmmu_scaler_1>; 1068 power-domains = <&pd_mscl>; 1069 }; 1070 1071 jpeg: codec@15020000 { 1072 compatible = "samsung,exynos5433-jpeg"; 1073 reg = <0x15020000 0x10000>; 1074 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; 1075 clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; 1076 clocks = <&cmu_mscl CLK_PCLK_JPEG>, 1077 <&cmu_mscl CLK_ACLK_JPEG>, 1078 <&cmu_mscl CLK_ACLK_XIU_MSCLX>, 1079 <&cmu_mscl CLK_SCLK_JPEG>; 1080 iommus = <&sysmmu_jpeg>; 1081 power-domains = <&pd_mscl>; 1082 }; 1083 1084 mfc: codec@152e0000 { 1085 compatible = "samsung,exynos5433-mfc"; 1086 reg = <0x152E0000 0x10000>; 1087 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1088 clock-names = "pclk", "aclk", "aclk_xiu"; 1089 clocks = <&cmu_mfc CLK_PCLK_MFC>, 1090 <&cmu_mfc CLK_ACLK_MFC>, 1091 <&cmu_mfc CLK_ACLK_XIU_MFCX>; 1092 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; 1093 iommu-names = "left", "right"; 1094 power-domains = <&pd_mfc>; 1095 }; 1096 1097 sysmmu_decon0x: sysmmu@13a00000 { 1098 compatible = "samsung,exynos-sysmmu"; 1099 reg = <0x13a00000 0x1000>; 1100 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1101 clock-names = "pclk", "aclk"; 1102 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 1103 <&cmu_disp CLK_ACLK_SMMU_DECON0X>; 1104 power-domains = <&pd_disp>; 1105 #iommu-cells = <0>; 1106 }; 1107 1108 sysmmu_decon1x: sysmmu@13a10000 { 1109 compatible = "samsung,exynos-sysmmu"; 1110 reg = <0x13a10000 0x1000>; 1111 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1112 clock-names = "pclk", "aclk"; 1113 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>, 1114 <&cmu_disp CLK_ACLK_SMMU_DECON1X>; 1115 #iommu-cells = <0>; 1116 power-domains = <&pd_disp>; 1117 }; 1118 1119 sysmmu_tv0x: sysmmu@13a20000 { 1120 compatible = "samsung,exynos-sysmmu"; 1121 reg = <0x13a20000 0x1000>; 1122 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 1123 clock-names = "pclk", "aclk"; 1124 clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>, 1125 <&cmu_disp CLK_ACLK_SMMU_TV0X>; 1126 #iommu-cells = <0>; 1127 power-domains = <&pd_disp>; 1128 }; 1129 1130 sysmmu_tv1x: sysmmu@13a30000 { 1131 compatible = "samsung,exynos-sysmmu"; 1132 reg = <0x13a30000 0x1000>; 1133 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1134 clock-names = "pclk", "aclk"; 1135 clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>, 1136 <&cmu_disp CLK_ACLK_SMMU_TV1X>; 1137 #iommu-cells = <0>; 1138 power-domains = <&pd_disp>; 1139 }; 1140 1141 sysmmu_gscl0: sysmmu@13c80000 { 1142 compatible = "samsung,exynos-sysmmu"; 1143 reg = <0x13C80000 0x1000>; 1144 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 1145 clock-names = "aclk", "pclk"; 1146 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, 1147 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; 1148 #iommu-cells = <0>; 1149 power-domains = <&pd_gscl>; 1150 }; 1151 1152 sysmmu_gscl1: sysmmu@13c90000 { 1153 compatible = "samsung,exynos-sysmmu"; 1154 reg = <0x13C90000 0x1000>; 1155 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 1156 clock-names = "aclk", "pclk"; 1157 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, 1158 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; 1159 #iommu-cells = <0>; 1160 power-domains = <&pd_gscl>; 1161 }; 1162 1163 sysmmu_gscl2: sysmmu@13ca0000 { 1164 compatible = "samsung,exynos-sysmmu"; 1165 reg = <0x13CA0000 0x1000>; 1166 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 1167 clock-names = "aclk", "pclk"; 1168 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, 1169 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; 1170 #iommu-cells = <0>; 1171 power-domains = <&pd_gscl>; 1172 }; 1173 1174 sysmmu_scaler_0: sysmmu@15040000 { 1175 compatible = "samsung,exynos-sysmmu"; 1176 reg = <0x15040000 0x1000>; 1177 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1178 clock-names = "pclk", "aclk"; 1179 clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>, 1180 <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>; 1181 #iommu-cells = <0>; 1182 power-domains = <&pd_mscl>; 1183 }; 1184 1185 sysmmu_scaler_1: sysmmu@15050000 { 1186 compatible = "samsung,exynos-sysmmu"; 1187 reg = <0x15050000 0x1000>; 1188 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; 1189 clock-names = "pclk", "aclk"; 1190 clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>, 1191 <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>; 1192 #iommu-cells = <0>; 1193 power-domains = <&pd_mscl>; 1194 }; 1195 1196 sysmmu_jpeg: sysmmu@15060000 { 1197 compatible = "samsung,exynos-sysmmu"; 1198 reg = <0x15060000 0x1000>; 1199 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1200 clock-names = "pclk", "aclk"; 1201 clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>, 1202 <&cmu_mscl CLK_ACLK_SMMU_JPEG>; 1203 #iommu-cells = <0>; 1204 power-domains = <&pd_mscl>; 1205 }; 1206 1207 sysmmu_mfc_0: sysmmu@15200000 { 1208 compatible = "samsung,exynos-sysmmu"; 1209 reg = <0x15200000 0x1000>; 1210 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1211 clock-names = "pclk", "aclk"; 1212 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>, 1213 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>; 1214 #iommu-cells = <0>; 1215 power-domains = <&pd_mfc>; 1216 }; 1217 1218 sysmmu_mfc_1: sysmmu@15210000 { 1219 compatible = "samsung,exynos-sysmmu"; 1220 reg = <0x15210000 0x1000>; 1221 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1222 clock-names = "pclk", "aclk"; 1223 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>, 1224 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>; 1225 #iommu-cells = <0>; 1226 power-domains = <&pd_mfc>; 1227 }; 1228 1229 serial_0: serial@14c10000 { 1230 compatible = "samsung,exynos5433-uart"; 1231 reg = <0x14c10000 0x100>; 1232 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1233 clocks = <&cmu_peric CLK_PCLK_UART0>, 1234 <&cmu_peric CLK_SCLK_UART0>; 1235 clock-names = "uart", "clk_uart_baud0"; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&uart0_bus>; 1238 status = "disabled"; 1239 }; 1240 1241 serial_1: serial@14c20000 { 1242 compatible = "samsung,exynos5433-uart"; 1243 reg = <0x14c20000 0x100>; 1244 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&cmu_peric CLK_PCLK_UART1>, 1246 <&cmu_peric CLK_SCLK_UART1>; 1247 clock-names = "uart", "clk_uart_baud0"; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&uart1_bus>; 1250 status = "disabled"; 1251 }; 1252 1253 serial_2: serial@14c30000 { 1254 compatible = "samsung,exynos5433-uart"; 1255 reg = <0x14c30000 0x100>; 1256 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&cmu_peric CLK_PCLK_UART2>, 1258 <&cmu_peric CLK_SCLK_UART2>; 1259 clock-names = "uart", "clk_uart_baud0"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&uart2_bus>; 1262 status = "disabled"; 1263 }; 1264 1265 spi_0: spi@14d20000 { 1266 compatible = "samsung,exynos5433-spi"; 1267 reg = <0x14d20000 0x100>; 1268 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>; 1269 dmas = <&pdma0 9>, <&pdma0 8>; 1270 dma-names = "tx", "rx"; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 clocks = <&cmu_peric CLK_PCLK_SPI0>, 1274 <&cmu_peric CLK_SCLK_SPI0>, 1275 <&cmu_peric CLK_SCLK_IOCLK_SPI0>; 1276 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1277 samsung,spi-src-clk = <0>; 1278 pinctrl-names = "default"; 1279 pinctrl-0 = <&spi0_bus>; 1280 num-cs = <1>; 1281 status = "disabled"; 1282 }; 1283 1284 spi_1: spi@14d30000 { 1285 compatible = "samsung,exynos5433-spi"; 1286 reg = <0x14d30000 0x100>; 1287 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; 1288 dmas = <&pdma0 11>, <&pdma0 10>; 1289 dma-names = "tx", "rx"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 clocks = <&cmu_peric CLK_PCLK_SPI1>, 1293 <&cmu_peric CLK_SCLK_SPI1>, 1294 <&cmu_peric CLK_SCLK_IOCLK_SPI1>; 1295 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1296 samsung,spi-src-clk = <0>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&spi1_bus>; 1299 num-cs = <1>; 1300 status = "disabled"; 1301 }; 1302 1303 spi_2: spi@14d40000 { 1304 compatible = "samsung,exynos5433-spi"; 1305 reg = <0x14d40000 0x100>; 1306 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>; 1307 dmas = <&pdma0 13>, <&pdma0 12>; 1308 dma-names = "tx", "rx"; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 clocks = <&cmu_peric CLK_PCLK_SPI2>, 1312 <&cmu_peric CLK_SCLK_SPI2>, 1313 <&cmu_peric CLK_SCLK_IOCLK_SPI2>; 1314 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1315 samsung,spi-src-clk = <0>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&spi2_bus>; 1318 num-cs = <1>; 1319 status = "disabled"; 1320 }; 1321 1322 spi_3: spi@14d50000 { 1323 compatible = "samsung,exynos5433-spi"; 1324 reg = <0x14d50000 0x100>; 1325 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; 1326 dmas = <&pdma0 23>, <&pdma0 22>; 1327 dma-names = "tx", "rx"; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 clocks = <&cmu_peric CLK_PCLK_SPI3>, 1331 <&cmu_peric CLK_SCLK_SPI3>, 1332 <&cmu_peric CLK_SCLK_IOCLK_SPI3>; 1333 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1334 samsung,spi-src-clk = <0>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&spi3_bus>; 1337 num-cs = <1>; 1338 status = "disabled"; 1339 }; 1340 1341 spi_4: spi@14d00000 { 1342 compatible = "samsung,exynos5433-spi"; 1343 reg = <0x14d00000 0x100>; 1344 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 1345 dmas = <&pdma0 25>, <&pdma0 24>; 1346 dma-names = "tx", "rx"; 1347 #address-cells = <1>; 1348 #size-cells = <0>; 1349 clocks = <&cmu_peric CLK_PCLK_SPI4>, 1350 <&cmu_peric CLK_SCLK_SPI4>, 1351 <&cmu_peric CLK_SCLK_IOCLK_SPI4>; 1352 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1353 samsung,spi-src-clk = <0>; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&spi4_bus>; 1356 num-cs = <1>; 1357 status = "disabled"; 1358 }; 1359 1360 adc: adc@14d10000 { 1361 compatible = "samsung,exynos7-adc"; 1362 reg = <0x14d10000 0x100>; 1363 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 1364 clock-names = "adc"; 1365 clocks = <&cmu_peric CLK_PCLK_ADCIF>; 1366 #io-channel-cells = <1>; 1367 io-channel-ranges; 1368 status = "disabled"; 1369 }; 1370 1371 i2s1: i2s@14d60000 { 1372 compatible = "samsung,exynos7-i2s"; 1373 reg = <0x14d60000 0x100>; 1374 dmas = <&pdma0 31 &pdma0 30>; 1375 dma-names = "tx", "rx"; 1376 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&cmu_peric CLK_PCLK_I2S1>, 1378 <&cmu_peric CLK_PCLK_I2S1>, 1379 <&cmu_peric CLK_SCLK_I2S1>; 1380 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 1381 #clock-cells = <1>; 1382 samsung,supports-6ch; 1383 samsung,supports-rstclr; 1384 samsung,supports-tdm; 1385 samsung,supports-low-rfs; 1386 #sound-dai-cells = <1>; 1387 status = "disabled"; 1388 }; 1389 1390 pwm: pwm@14dd0000 { 1391 compatible = "samsung,exynos4210-pwm"; 1392 reg = <0x14dd0000 0x100>; 1393 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 1398 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 1399 clocks = <&cmu_peric CLK_PCLK_PWM>; 1400 clock-names = "timers"; 1401 #pwm-cells = <3>; 1402 status = "disabled"; 1403 }; 1404 1405 hsi2c_0: hsi2c@14e40000 { 1406 compatible = "samsung,exynos7-hsi2c"; 1407 reg = <0x14e40000 0x1000>; 1408 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&hs_i2c0_bus>; 1413 clocks = <&cmu_peric CLK_PCLK_HSI2C0>; 1414 clock-names = "hsi2c"; 1415 status = "disabled"; 1416 }; 1417 1418 hsi2c_1: hsi2c@14e50000 { 1419 compatible = "samsung,exynos7-hsi2c"; 1420 reg = <0x14e50000 0x1000>; 1421 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 pinctrl-names = "default"; 1425 pinctrl-0 = <&hs_i2c1_bus>; 1426 clocks = <&cmu_peric CLK_PCLK_HSI2C1>; 1427 clock-names = "hsi2c"; 1428 status = "disabled"; 1429 }; 1430 1431 hsi2c_2: hsi2c@14e60000 { 1432 compatible = "samsung,exynos7-hsi2c"; 1433 reg = <0x14e60000 0x1000>; 1434 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&hs_i2c2_bus>; 1439 clocks = <&cmu_peric CLK_PCLK_HSI2C2>; 1440 clock-names = "hsi2c"; 1441 status = "disabled"; 1442 }; 1443 1444 hsi2c_3: hsi2c@14e70000 { 1445 compatible = "samsung,exynos7-hsi2c"; 1446 reg = <0x14e70000 0x1000>; 1447 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&hs_i2c3_bus>; 1452 clocks = <&cmu_peric CLK_PCLK_HSI2C3>; 1453 clock-names = "hsi2c"; 1454 status = "disabled"; 1455 }; 1456 1457 hsi2c_4: hsi2c@14ec0000 { 1458 compatible = "samsung,exynos7-hsi2c"; 1459 reg = <0x14ec0000 0x1000>; 1460 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&hs_i2c4_bus>; 1465 clocks = <&cmu_peric CLK_PCLK_HSI2C4>; 1466 clock-names = "hsi2c"; 1467 status = "disabled"; 1468 }; 1469 1470 hsi2c_5: hsi2c@14ed0000 { 1471 compatible = "samsung,exynos7-hsi2c"; 1472 reg = <0x14ed0000 0x1000>; 1473 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 pinctrl-names = "default"; 1477 pinctrl-0 = <&hs_i2c5_bus>; 1478 clocks = <&cmu_peric CLK_PCLK_HSI2C5>; 1479 clock-names = "hsi2c"; 1480 status = "disabled"; 1481 }; 1482 1483 hsi2c_6: hsi2c@14ee0000 { 1484 compatible = "samsung,exynos7-hsi2c"; 1485 reg = <0x14ee0000 0x1000>; 1486 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>; 1487 #address-cells = <1>; 1488 #size-cells = <0>; 1489 pinctrl-names = "default"; 1490 pinctrl-0 = <&hs_i2c6_bus>; 1491 clocks = <&cmu_peric CLK_PCLK_HSI2C6>; 1492 clock-names = "hsi2c"; 1493 status = "disabled"; 1494 }; 1495 1496 hsi2c_7: hsi2c@14ef0000 { 1497 compatible = "samsung,exynos7-hsi2c"; 1498 reg = <0x14ef0000 0x1000>; 1499 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&hs_i2c7_bus>; 1504 clocks = <&cmu_peric CLK_PCLK_HSI2C7>; 1505 clock-names = "hsi2c"; 1506 status = "disabled"; 1507 }; 1508 1509 hsi2c_8: hsi2c@14d90000 { 1510 compatible = "samsung,exynos7-hsi2c"; 1511 reg = <0x14d90000 0x1000>; 1512 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 pinctrl-names = "default"; 1516 pinctrl-0 = <&hs_i2c8_bus>; 1517 clocks = <&cmu_peric CLK_PCLK_HSI2C8>; 1518 clock-names = "hsi2c"; 1519 status = "disabled"; 1520 }; 1521 1522 hsi2c_9: hsi2c@14da0000 { 1523 compatible = "samsung,exynos7-hsi2c"; 1524 reg = <0x14da0000 0x1000>; 1525 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 pinctrl-names = "default"; 1529 pinctrl-0 = <&hs_i2c9_bus>; 1530 clocks = <&cmu_peric CLK_PCLK_HSI2C9>; 1531 clock-names = "hsi2c"; 1532 status = "disabled"; 1533 }; 1534 1535 hsi2c_10: hsi2c@14de0000 { 1536 compatible = "samsung,exynos7-hsi2c"; 1537 reg = <0x14de0000 0x1000>; 1538 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&hs_i2c10_bus>; 1543 clocks = <&cmu_peric CLK_PCLK_HSI2C10>; 1544 clock-names = "hsi2c"; 1545 status = "disabled"; 1546 }; 1547 1548 hsi2c_11: hsi2c@14df0000 { 1549 compatible = "samsung,exynos7-hsi2c"; 1550 reg = <0x14df0000 0x1000>; 1551 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 pinctrl-names = "default"; 1555 pinctrl-0 = <&hs_i2c11_bus>; 1556 clocks = <&cmu_peric CLK_PCLK_HSI2C11>; 1557 clock-names = "hsi2c"; 1558 status = "disabled"; 1559 }; 1560 1561 usbdrd30: usbdrd { 1562 compatible = "samsung,exynos5250-dwusb3"; 1563 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, 1564 <&cmu_fsys CLK_SCLK_USBDRD30>; 1565 clock-names = "usbdrd30", "usbdrd30_susp_clk"; 1566 #address-cells = <1>; 1567 #size-cells = <1>; 1568 ranges; 1569 status = "disabled"; 1570 1571 usbdrd_dwc3: dwc3@15400000 { 1572 compatible = "snps,dwc3"; 1573 reg = <0x15400000 0x10000>; 1574 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1575 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; 1576 phy-names = "usb2-phy", "usb3-phy"; 1577 }; 1578 }; 1579 1580 usbdrd30_phy: phy@15500000 { 1581 compatible = "samsung,exynos5433-usbdrd-phy"; 1582 reg = <0x15500000 0x100>; 1583 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>, 1584 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, 1585 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, 1586 <&cmu_fsys CLK_SCLK_USBDRD30>; 1587 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", 1588 "itp"; 1589 #phy-cells = <1>; 1590 samsung,pmu-syscon = <&pmu_system_controller>; 1591 status = "disabled"; 1592 }; 1593 1594 usbhost30_phy: phy@15580000 { 1595 compatible = "samsung,exynos5433-usbdrd-phy"; 1596 reg = <0x15580000 0x100>; 1597 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, 1598 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, 1599 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, 1600 <&cmu_fsys CLK_SCLK_USBHOST30>; 1601 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", 1602 "itp"; 1603 #phy-cells = <1>; 1604 samsung,pmu-syscon = <&pmu_system_controller>; 1605 status = "disabled"; 1606 }; 1607 1608 usbhost30: usbhost { 1609 compatible = "samsung,exynos5250-dwusb3"; 1610 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, 1611 <&cmu_fsys CLK_SCLK_USBHOST30>; 1612 clock-names = "usbdrd30", "usbdrd30_susp_clk"; 1613 #address-cells = <1>; 1614 #size-cells = <1>; 1615 ranges; 1616 status = "disabled"; 1617 1618 usbhost_dwc3: dwc3@15a00000 { 1619 compatible = "snps,dwc3"; 1620 reg = <0x15a00000 0x10000>; 1621 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1622 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; 1623 phy-names = "usb2-phy", "usb3-phy"; 1624 }; 1625 }; 1626 1627 mshc_0: mshc@15540000 { 1628 compatible = "samsung,exynos7-dw-mshc-smu"; 1629 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 reg = <0x15540000 0x2000>; 1633 clocks = <&cmu_fsys CLK_ACLK_MMC0>, 1634 <&cmu_fsys CLK_SCLK_MMC0>; 1635 clock-names = "biu", "ciu"; 1636 fifo-depth = <0x40>; 1637 status = "disabled"; 1638 }; 1639 1640 mshc_1: mshc@15550000 { 1641 compatible = "samsung,exynos7-dw-mshc-smu"; 1642 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 reg = <0x15550000 0x2000>; 1646 clocks = <&cmu_fsys CLK_ACLK_MMC1>, 1647 <&cmu_fsys CLK_SCLK_MMC1>; 1648 clock-names = "biu", "ciu"; 1649 fifo-depth = <0x40>; 1650 status = "disabled"; 1651 }; 1652 1653 mshc_2: mshc@15560000 { 1654 compatible = "samsung,exynos7-dw-mshc-smu"; 1655 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 reg = <0x15560000 0x2000>; 1659 clocks = <&cmu_fsys CLK_ACLK_MMC2>, 1660 <&cmu_fsys CLK_SCLK_MMC2>; 1661 clock-names = "biu", "ciu"; 1662 fifo-depth = <0x40>; 1663 status = "disabled"; 1664 }; 1665 1666 amba { 1667 compatible = "simple-bus"; 1668 #address-cells = <1>; 1669 #size-cells = <1>; 1670 ranges; 1671 1672 pdma0: pdma@15610000 { 1673 compatible = "arm,pl330", "arm,primecell"; 1674 reg = <0x15610000 0x1000>; 1675 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1676 clocks = <&cmu_fsys CLK_PDMA0>; 1677 clock-names = "apb_pclk"; 1678 #dma-cells = <1>; 1679 #dma-channels = <8>; 1680 #dma-requests = <32>; 1681 }; 1682 1683 pdma1: pdma@15600000 { 1684 compatible = "arm,pl330", "arm,primecell"; 1685 reg = <0x15600000 0x1000>; 1686 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1687 clocks = <&cmu_fsys CLK_PDMA1>; 1688 clock-names = "apb_pclk"; 1689 #dma-cells = <1>; 1690 #dma-channels = <8>; 1691 #dma-requests = <32>; 1692 }; 1693 }; 1694 1695 audio-subsystem@11400000 { 1696 compatible = "samsung,exynos5433-lpass"; 1697 reg = <0x11400000 0x100>, <0x11500000 0x08>; 1698 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; 1699 clock-names = "sfr0_ctrl"; 1700 samsung,pmu-syscon = <&pmu_system_controller>; 1701 power-domains = <&pd_aud>; 1702 #address-cells = <1>; 1703 #size-cells = <1>; 1704 ranges; 1705 1706 adma: adma@11420000 { 1707 compatible = "arm,pl330", "arm,primecell"; 1708 reg = <0x11420000 0x1000>; 1709 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1710 clocks = <&cmu_aud CLK_ACLK_DMAC>; 1711 clock-names = "apb_pclk"; 1712 #dma-cells = <1>; 1713 #dma-channels = <8>; 1714 #dma-requests = <32>; 1715 power-domains = <&pd_aud>; 1716 }; 1717 1718 i2s0: i2s@11440000 { 1719 compatible = "samsung,exynos7-i2s"; 1720 reg = <0x11440000 0x100>; 1721 dmas = <&adma 0 &adma 2>; 1722 dma-names = "tx", "rx"; 1723 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, 1727 <&cmu_aud CLK_SCLK_AUD_I2S>, 1728 <&cmu_aud CLK_SCLK_I2S_BCLK>; 1729 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 1730 #clock-cells = <1>; 1731 pinctrl-names = "default"; 1732 pinctrl-0 = <&i2s0_bus>; 1733 power-domains = <&pd_aud>; 1734 #sound-dai-cells = <1>; 1735 status = "disabled"; 1736 }; 1737 1738 serial_3: serial@11460000 { 1739 compatible = "samsung,exynos5433-uart"; 1740 reg = <0x11460000 0x100>; 1741 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1742 clocks = <&cmu_aud CLK_PCLK_AUD_UART>, 1743 <&cmu_aud CLK_SCLK_AUD_UART>; 1744 clock-names = "uart", "clk_uart_baud0"; 1745 pinctrl-names = "default"; 1746 pinctrl-0 = <&uart_aud_bus>; 1747 power-domains = <&pd_aud>; 1748 status = "disabled"; 1749 }; 1750 }; 1751 }; 1752 1753 timer: timer { 1754 compatible = "arm,armv8-timer"; 1755 interrupts = <GIC_PPI 13 1756 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 1757 <GIC_PPI 14 1758 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 1759 <GIC_PPI 11 1760 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 1761 <GIC_PPI 10 1762 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1763 }; 1764}; 1765 1766#include "exynos5433-bus.dtsi" 1767#include "exynos5433-pinctrl.dtsi" 1768#include "exynos5433-tmu.dtsi" 1769