1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's Exynos5433 SoC device tree source 4 * 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6 * 7 * Samsung's Exynos5433 SoC device nodes are listed in this file. 8 * Exynos5433 based board files can include this file and provide 9 * values for board specific bindings. 10 * 11 * Note: This file does not include device nodes for all the controllers in 12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, 13 * additional nodes can be added to this file. 14 */ 15 16#include <dt-bindings/clock/exynos5433.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18 19/ { 20 compatible = "samsung,exynos5433"; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 interrupt-parent = <&gic>; 25 26 arm_a53_pmu { 27 compatible = "arm,cortex-a53-pmu"; 28 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 33 }; 34 35 arm_a57_pmu { 36 compatible = "arm,cortex-a57-pmu"; 37 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 41 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 42 }; 43 44 xxti: clock { 45 /* XXTI */ 46 compatible = "fixed-clock"; 47 clock-output-names = "oscclk"; 48 #clock-cells = <0>; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 cpu0: cpu@100 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 enable-method = "psci"; 59 reg = <0x100>; 60 clock-frequency = <1300000000>; 61 clocks = <&cmu_apollo CLK_SCLK_APOLLO>; 62 clock-names = "apolloclk"; 63 operating-points-v2 = <&cluster_a53_opp_table>; 64 #cooling-cells = <2>; 65 }; 66 67 cpu1: cpu@101 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 enable-method = "psci"; 71 reg = <0x101>; 72 clock-frequency = <1300000000>; 73 operating-points-v2 = <&cluster_a53_opp_table>; 74 #cooling-cells = <2>; 75 }; 76 77 cpu2: cpu@102 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 enable-method = "psci"; 81 reg = <0x102>; 82 clock-frequency = <1300000000>; 83 operating-points-v2 = <&cluster_a53_opp_table>; 84 #cooling-cells = <2>; 85 }; 86 87 cpu3: cpu@103 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 enable-method = "psci"; 91 reg = <0x103>; 92 clock-frequency = <1300000000>; 93 operating-points-v2 = <&cluster_a53_opp_table>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu4: cpu@0 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a57"; 100 enable-method = "psci"; 101 reg = <0x0>; 102 clock-frequency = <1900000000>; 103 clocks = <&cmu_atlas CLK_SCLK_ATLAS>; 104 clock-names = "atlasclk"; 105 operating-points-v2 = <&cluster_a57_opp_table>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu5: cpu@1 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a57"; 112 enable-method = "psci"; 113 reg = <0x1>; 114 clock-frequency = <1900000000>; 115 operating-points-v2 = <&cluster_a57_opp_table>; 116 #cooling-cells = <2>; 117 }; 118 119 cpu6: cpu@2 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a57"; 122 enable-method = "psci"; 123 reg = <0x2>; 124 clock-frequency = <1900000000>; 125 operating-points-v2 = <&cluster_a57_opp_table>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu7: cpu@3 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a57"; 132 enable-method = "psci"; 133 reg = <0x3>; 134 clock-frequency = <1900000000>; 135 operating-points-v2 = <&cluster_a57_opp_table>; 136 #cooling-cells = <2>; 137 }; 138 }; 139 140 cluster_a53_opp_table: opp_table0 { 141 compatible = "operating-points-v2"; 142 opp-shared; 143 144 opp-400000000 { 145 opp-hz = /bits/ 64 <400000000>; 146 opp-microvolt = <900000>; 147 }; 148 opp-500000000 { 149 opp-hz = /bits/ 64 <500000000>; 150 opp-microvolt = <925000>; 151 }; 152 opp-600000000 { 153 opp-hz = /bits/ 64 <600000000>; 154 opp-microvolt = <950000>; 155 }; 156 opp-700000000 { 157 opp-hz = /bits/ 64 <700000000>; 158 opp-microvolt = <975000>; 159 }; 160 opp-800000000 { 161 opp-hz = /bits/ 64 <800000000>; 162 opp-microvolt = <1000000>; 163 }; 164 opp-900000000 { 165 opp-hz = /bits/ 64 <900000000>; 166 opp-microvolt = <1050000>; 167 }; 168 opp-1000000000 { 169 opp-hz = /bits/ 64 <1000000000>; 170 opp-microvolt = <1075000>; 171 }; 172 opp-1100000000 { 173 opp-hz = /bits/ 64 <1100000000>; 174 opp-microvolt = <1112500>; 175 }; 176 opp-1200000000 { 177 opp-hz = /bits/ 64 <1200000000>; 178 opp-microvolt = <1112500>; 179 }; 180 opp-1300000000 { 181 opp-hz = /bits/ 64 <1300000000>; 182 opp-microvolt = <1150000>; 183 }; 184 }; 185 186 cluster_a57_opp_table: opp_table1 { 187 compatible = "operating-points-v2"; 188 opp-shared; 189 190 opp-500000000 { 191 opp-hz = /bits/ 64 <500000000>; 192 opp-microvolt = <900000>; 193 }; 194 opp-600000000 { 195 opp-hz = /bits/ 64 <600000000>; 196 opp-microvolt = <900000>; 197 }; 198 opp-700000000 { 199 opp-hz = /bits/ 64 <700000000>; 200 opp-microvolt = <912500>; 201 }; 202 opp-800000000 { 203 opp-hz = /bits/ 64 <800000000>; 204 opp-microvolt = <912500>; 205 }; 206 opp-900000000 { 207 opp-hz = /bits/ 64 <900000000>; 208 opp-microvolt = <937500>; 209 }; 210 opp-1000000000 { 211 opp-hz = /bits/ 64 <1000000000>; 212 opp-microvolt = <975000>; 213 }; 214 opp-1100000000 { 215 opp-hz = /bits/ 64 <1100000000>; 216 opp-microvolt = <1012500>; 217 }; 218 opp-1200000000 { 219 opp-hz = /bits/ 64 <1200000000>; 220 opp-microvolt = <1037500>; 221 }; 222 opp-1300000000 { 223 opp-hz = /bits/ 64 <1300000000>; 224 opp-microvolt = <1062500>; 225 }; 226 opp-1400000000 { 227 opp-hz = /bits/ 64 <1400000000>; 228 opp-microvolt = <1087500>; 229 }; 230 opp-1500000000 { 231 opp-hz = /bits/ 64 <1500000000>; 232 opp-microvolt = <1125000>; 233 }; 234 opp-1600000000 { 235 opp-hz = /bits/ 64 <1600000000>; 236 opp-microvolt = <1137500>; 237 }; 238 opp-1700000000 { 239 opp-hz = /bits/ 64 <1700000000>; 240 opp-microvolt = <1175000>; 241 }; 242 opp-1800000000 { 243 opp-hz = /bits/ 64 <1800000000>; 244 opp-microvolt = <1212500>; 245 }; 246 opp-1900000000 { 247 opp-hz = /bits/ 64 <1900000000>; 248 opp-microvolt = <1262500>; 249 }; 250 }; 251 252 psci { 253 compatible = "arm,psci"; 254 method = "smc"; 255 cpu_off = <0x84000002>; 256 cpu_on = <0xC4000003>; 257 }; 258 259 soc: soc@0 { 260 compatible = "simple-bus"; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges = <0x0 0x0 0x0 0x18000000>; 264 265 chipid@10000000 { 266 compatible = "samsung,exynos4210-chipid"; 267 reg = <0x10000000 0x100>; 268 }; 269 270 cmu_top: clock-controller@10030000 { 271 compatible = "samsung,exynos5433-cmu-top"; 272 reg = <0x10030000 0x1000>; 273 #clock-cells = <1>; 274 275 clock-names = "oscclk", 276 "sclk_mphy_pll", 277 "sclk_mfc_pll", 278 "sclk_bus_pll"; 279 clocks = <&xxti>, 280 <&cmu_cpif CLK_SCLK_MPHY_PLL>, 281 <&cmu_mif CLK_SCLK_MFC_PLL>, 282 <&cmu_mif CLK_SCLK_BUS_PLL>; 283 }; 284 285 cmu_cpif: clock-controller@10fc0000 { 286 compatible = "samsung,exynos5433-cmu-cpif"; 287 reg = <0x10fc0000 0x1000>; 288 #clock-cells = <1>; 289 290 clock-names = "oscclk"; 291 clocks = <&xxti>; 292 }; 293 294 cmu_mif: clock-controller@105b0000 { 295 compatible = "samsung,exynos5433-cmu-mif"; 296 reg = <0x105b0000 0x2000>; 297 #clock-cells = <1>; 298 299 clock-names = "oscclk", 300 "sclk_mphy_pll"; 301 clocks = <&xxti>, 302 <&cmu_cpif CLK_SCLK_MPHY_PLL>; 303 }; 304 305 cmu_peric: clock-controller@14c80000 { 306 compatible = "samsung,exynos5433-cmu-peric"; 307 reg = <0x14c80000 0x1000>; 308 #clock-cells = <1>; 309 }; 310 311 cmu_peris: clock-controller@10040000 { 312 compatible = "samsung,exynos5433-cmu-peris"; 313 reg = <0x10040000 0x1000>; 314 #clock-cells = <1>; 315 }; 316 317 cmu_fsys: clock-controller@156e0000 { 318 compatible = "samsung,exynos5433-cmu-fsys"; 319 reg = <0x156e0000 0x1000>; 320 #clock-cells = <1>; 321 322 clock-names = "oscclk", 323 "sclk_ufs_mphy", 324 "aclk_fsys_200", 325 "sclk_pcie_100_fsys", 326 "sclk_ufsunipro_fsys", 327 "sclk_mmc2_fsys", 328 "sclk_mmc1_fsys", 329 "sclk_mmc0_fsys", 330 "sclk_usbhost30_fsys", 331 "sclk_usbdrd30_fsys"; 332 clocks = <&xxti>, 333 <&cmu_cpif CLK_SCLK_UFS_MPHY>, 334 <&cmu_top CLK_ACLK_FSYS_200>, 335 <&cmu_top CLK_SCLK_PCIE_100_FSYS>, 336 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, 337 <&cmu_top CLK_SCLK_MMC2_FSYS>, 338 <&cmu_top CLK_SCLK_MMC1_FSYS>, 339 <&cmu_top CLK_SCLK_MMC0_FSYS>, 340 <&cmu_top CLK_SCLK_USBHOST30_FSYS>, 341 <&cmu_top CLK_SCLK_USBDRD30_FSYS>; 342 }; 343 344 cmu_g2d: clock-controller@12460000 { 345 compatible = "samsung,exynos5433-cmu-g2d"; 346 reg = <0x12460000 0x1000>; 347 #clock-cells = <1>; 348 349 clock-names = "oscclk", 350 "aclk_g2d_266", 351 "aclk_g2d_400"; 352 clocks = <&xxti>, 353 <&cmu_top CLK_ACLK_G2D_266>, 354 <&cmu_top CLK_ACLK_G2D_400>; 355 power-domains = <&pd_g2d>; 356 }; 357 358 cmu_disp: clock-controller@13b90000 { 359 compatible = "samsung,exynos5433-cmu-disp"; 360 reg = <0x13b90000 0x1000>; 361 #clock-cells = <1>; 362 363 clock-names = "oscclk", 364 "sclk_dsim1_disp", 365 "sclk_dsim0_disp", 366 "sclk_dsd_disp", 367 "sclk_decon_tv_eclk_disp", 368 "sclk_decon_vclk_disp", 369 "sclk_decon_eclk_disp", 370 "sclk_decon_tv_vclk_disp", 371 "aclk_disp_333"; 372 clocks = <&xxti>, 373 <&cmu_mif CLK_SCLK_DSIM1_DISP>, 374 <&cmu_mif CLK_SCLK_DSIM0_DISP>, 375 <&cmu_mif CLK_SCLK_DSD_DISP>, 376 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 377 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, 378 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 379 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, 380 <&cmu_mif CLK_ACLK_DISP_333>; 381 power-domains = <&pd_disp>; 382 }; 383 384 cmu_aud: clock-controller@114c0000 { 385 compatible = "samsung,exynos5433-cmu-aud"; 386 reg = <0x114c0000 0x1000>; 387 #clock-cells = <1>; 388 clock-names = "oscclk", "fout_aud_pll"; 389 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; 390 power-domains = <&pd_aud>; 391 }; 392 393 cmu_bus0: clock-controller@13600000 { 394 compatible = "samsung,exynos5433-cmu-bus0"; 395 reg = <0x13600000 0x1000>; 396 #clock-cells = <1>; 397 398 clock-names = "aclk_bus0_400"; 399 clocks = <&cmu_top CLK_ACLK_BUS0_400>; 400 }; 401 402 cmu_bus1: clock-controller@14800000 { 403 compatible = "samsung,exynos5433-cmu-bus1"; 404 reg = <0x14800000 0x1000>; 405 #clock-cells = <1>; 406 407 clock-names = "aclk_bus1_400"; 408 clocks = <&cmu_top CLK_ACLK_BUS1_400>; 409 }; 410 411 cmu_bus2: clock-controller@13400000 { 412 compatible = "samsung,exynos5433-cmu-bus2"; 413 reg = <0x13400000 0x1000>; 414 #clock-cells = <1>; 415 416 clock-names = "oscclk", "aclk_bus2_400"; 417 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; 418 }; 419 420 cmu_g3d: clock-controller@14aa0000 { 421 compatible = "samsung,exynos5433-cmu-g3d"; 422 reg = <0x14aa0000 0x2000>; 423 #clock-cells = <1>; 424 425 clock-names = "oscclk", "aclk_g3d_400"; 426 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; 427 power-domains = <&pd_g3d>; 428 }; 429 430 cmu_gscl: clock-controller@13cf0000 { 431 compatible = "samsung,exynos5433-cmu-gscl"; 432 reg = <0x13cf0000 0x1000>; 433 #clock-cells = <1>; 434 435 clock-names = "oscclk", 436 "aclk_gscl_111", 437 "aclk_gscl_333"; 438 clocks = <&xxti>, 439 <&cmu_top CLK_ACLK_GSCL_111>, 440 <&cmu_top CLK_ACLK_GSCL_333>; 441 power-domains = <&pd_gscl>; 442 }; 443 444 cmu_apollo: clock-controller@11900000 { 445 compatible = "samsung,exynos5433-cmu-apollo"; 446 reg = <0x11900000 0x2000>; 447 #clock-cells = <1>; 448 449 clock-names = "oscclk", "sclk_bus_pll_apollo"; 450 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; 451 }; 452 453 cmu_atlas: clock-controller@11800000 { 454 compatible = "samsung,exynos5433-cmu-atlas"; 455 reg = <0x11800000 0x2000>; 456 #clock-cells = <1>; 457 458 clock-names = "oscclk", "sclk_bus_pll_atlas"; 459 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; 460 }; 461 462 cmu_mscl: clock-controller@150d0000 { 463 compatible = "samsung,exynos5433-cmu-mscl"; 464 reg = <0x150d0000 0x1000>; 465 #clock-cells = <1>; 466 467 clock-names = "oscclk", 468 "sclk_jpeg_mscl", 469 "aclk_mscl_400"; 470 clocks = <&xxti>, 471 <&cmu_top CLK_SCLK_JPEG_MSCL>, 472 <&cmu_top CLK_ACLK_MSCL_400>; 473 power-domains = <&pd_mscl>; 474 }; 475 476 cmu_mfc: clock-controller@15280000 { 477 compatible = "samsung,exynos5433-cmu-mfc"; 478 reg = <0x15280000 0x1000>; 479 #clock-cells = <1>; 480 481 clock-names = "oscclk", "aclk_mfc_400"; 482 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; 483 power-domains = <&pd_mfc>; 484 }; 485 486 cmu_hevc: clock-controller@14f80000 { 487 compatible = "samsung,exynos5433-cmu-hevc"; 488 reg = <0x14f80000 0x1000>; 489 #clock-cells = <1>; 490 491 clock-names = "oscclk", "aclk_hevc_400"; 492 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; 493 power-domains = <&pd_hevc>; 494 }; 495 496 cmu_isp: clock-controller@146d0000 { 497 compatible = "samsung,exynos5433-cmu-isp"; 498 reg = <0x146d0000 0x1000>; 499 #clock-cells = <1>; 500 501 clock-names = "oscclk", 502 "aclk_isp_dis_400", 503 "aclk_isp_400"; 504 clocks = <&xxti>, 505 <&cmu_top CLK_ACLK_ISP_DIS_400>, 506 <&cmu_top CLK_ACLK_ISP_400>; 507 power-domains = <&pd_isp>; 508 }; 509 510 cmu_cam0: clock-controller@120d0000 { 511 compatible = "samsung,exynos5433-cmu-cam0"; 512 reg = <0x120d0000 0x1000>; 513 #clock-cells = <1>; 514 515 clock-names = "oscclk", 516 "aclk_cam0_333", 517 "aclk_cam0_400", 518 "aclk_cam0_552"; 519 clocks = <&xxti>, 520 <&cmu_top CLK_ACLK_CAM0_333>, 521 <&cmu_top CLK_ACLK_CAM0_400>, 522 <&cmu_top CLK_ACLK_CAM0_552>; 523 power-domains = <&pd_cam0>; 524 }; 525 526 cmu_cam1: clock-controller@145d0000 { 527 compatible = "samsung,exynos5433-cmu-cam1"; 528 reg = <0x145d0000 0x1000>; 529 #clock-cells = <1>; 530 531 clock-names = "oscclk", 532 "sclk_isp_uart_cam1", 533 "sclk_isp_spi1_cam1", 534 "sclk_isp_spi0_cam1", 535 "aclk_cam1_333", 536 "aclk_cam1_400", 537 "aclk_cam1_552"; 538 clocks = <&xxti>, 539 <&cmu_top CLK_SCLK_ISP_UART_CAM1>, 540 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, 541 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, 542 <&cmu_top CLK_ACLK_CAM1_333>, 543 <&cmu_top CLK_ACLK_CAM1_400>, 544 <&cmu_top CLK_ACLK_CAM1_552>; 545 power-domains = <&pd_cam1>; 546 }; 547 548 cmu_imem: clock-controller@11060000 { 549 compatible = "samsung,exynos5433-cmu-imem"; 550 reg = <0x11060000 0x1000>; 551 #clock-cells = <1>; 552 553 clock-names = "oscclk", 554 "aclk_imem_sssx_266", 555 "aclk_imem_266", 556 "aclk_imem_200"; 557 clocks = <&xxti>, 558 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, 559 <&cmu_top CLK_DIV_ACLK_IMEM_266>, 560 <&cmu_top CLK_DIV_ACLK_IMEM_200>; 561 }; 562 563 slim_sss: slim-sss@11140000 { 564 compatible = "samsung,exynos5433-slim-sss"; 565 reg = <0x11140000 0x1000>; 566 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 567 clock-names = "aclk", "pclk"; 568 clocks = <&cmu_imem CLK_ACLK_SLIMSSS>, 569 <&cmu_imem CLK_PCLK_SLIMSSS>; 570 }; 571 572 pd_gscl: power-domain@105c4000 { 573 compatible = "samsung,exynos5433-pd"; 574 reg = <0x105c4000 0x20>; 575 #power-domain-cells = <0>; 576 label = "GSCL"; 577 }; 578 579 pd_cam0: power-domain@105c4020 { 580 compatible = "samsung,exynos5433-pd"; 581 reg = <0x105c4020 0x20>; 582 #power-domain-cells = <0>; 583 power-domains = <&pd_cam1>; 584 label = "CAM0"; 585 }; 586 587 pd_mscl: power-domain@105c4040 { 588 compatible = "samsung,exynos5433-pd"; 589 reg = <0x105c4040 0x20>; 590 #power-domain-cells = <0>; 591 label = "MSCL"; 592 }; 593 594 pd_g3d: power-domain@105c4060 { 595 compatible = "samsung,exynos5433-pd"; 596 reg = <0x105c4060 0x20>; 597 #power-domain-cells = <0>; 598 label = "G3D"; 599 }; 600 601 pd_disp: power-domain@105c4080 { 602 compatible = "samsung,exynos5433-pd"; 603 reg = <0x105c4080 0x20>; 604 #power-domain-cells = <0>; 605 label = "DISP"; 606 }; 607 608 pd_cam1: power-domain@105c40a0 { 609 compatible = "samsung,exynos5433-pd"; 610 reg = <0x105c40a0 0x20>; 611 #power-domain-cells = <0>; 612 label = "CAM1"; 613 }; 614 615 pd_aud: power-domain@105c40c0 { 616 compatible = "samsung,exynos5433-pd"; 617 reg = <0x105c40c0 0x20>; 618 #power-domain-cells = <0>; 619 label = "AUD"; 620 }; 621 622 pd_g2d: power-domain@105c4120 { 623 compatible = "samsung,exynos5433-pd"; 624 reg = <0x105c4120 0x20>; 625 #power-domain-cells = <0>; 626 label = "G2D"; 627 }; 628 629 pd_isp: power-domain@105c4140 { 630 compatible = "samsung,exynos5433-pd"; 631 reg = <0x105c4140 0x20>; 632 #power-domain-cells = <0>; 633 power-domains = <&pd_cam0>; 634 label = "ISP"; 635 }; 636 637 pd_mfc: power-domain@105c4180 { 638 compatible = "samsung,exynos5433-pd"; 639 reg = <0x105c4180 0x20>; 640 #power-domain-cells = <0>; 641 label = "MFC"; 642 }; 643 644 pd_hevc: power-domain@105c41c0 { 645 compatible = "samsung,exynos5433-pd"; 646 reg = <0x105c41c0 0x20>; 647 #power-domain-cells = <0>; 648 label = "HEVC"; 649 }; 650 651 tmu_atlas0: tmu@10060000 { 652 compatible = "samsung,exynos5433-tmu"; 653 reg = <0x10060000 0x200>; 654 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, 656 <&cmu_peris CLK_SCLK_TMU0>; 657 clock-names = "tmu_apbif", "tmu_sclk"; 658 #thermal-sensor-cells = <0>; 659 status = "disabled"; 660 }; 661 662 tmu_atlas1: tmu@10068000 { 663 compatible = "samsung,exynos5433-tmu"; 664 reg = <0x10068000 0x200>; 665 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, 667 <&cmu_peris CLK_SCLK_TMU0>; 668 clock-names = "tmu_apbif", "tmu_sclk"; 669 #thermal-sensor-cells = <0>; 670 status = "disabled"; 671 }; 672 673 tmu_g3d: tmu@10070000 { 674 compatible = "samsung,exynos5433-tmu"; 675 reg = <0x10070000 0x200>; 676 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, 678 <&cmu_peris CLK_SCLK_TMU1>; 679 clock-names = "tmu_apbif", "tmu_sclk"; 680 #thermal-sensor-cells = <0>; 681 status = "disabled"; 682 }; 683 684 tmu_apollo: tmu@10078000 { 685 compatible = "samsung,exynos5433-tmu"; 686 reg = <0x10078000 0x200>; 687 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, 689 <&cmu_peris CLK_SCLK_TMU1>; 690 clock-names = "tmu_apbif", "tmu_sclk"; 691 #thermal-sensor-cells = <0>; 692 status = "disabled"; 693 }; 694 695 tmu_isp: tmu@1007c000 { 696 compatible = "samsung,exynos5433-tmu"; 697 reg = <0x1007c000 0x200>; 698 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, 700 <&cmu_peris CLK_SCLK_TMU1>; 701 clock-names = "tmu_apbif", "tmu_sclk"; 702 #thermal-sensor-cells = <0>; 703 status = "disabled"; 704 }; 705 706 timer@101c0000 { 707 compatible = "samsung,exynos4210-mct"; 708 reg = <0x101c0000 0x800>; 709 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; 722 clock-names = "fin_pll", "mct"; 723 }; 724 725 ppmu_d0_cpu: ppmu@10480000 { 726 compatible = "samsung,exynos-ppmu-v2"; 727 reg = <0x10480000 0x2000>; 728 status = "disabled"; 729 }; 730 731 ppmu_d0_general: ppmu@10490000 { 732 compatible = "samsung,exynos-ppmu-v2"; 733 reg = <0x10490000 0x2000>; 734 status = "disabled"; 735 }; 736 737 ppmu_d1_cpu: ppmu@104b0000 { 738 compatible = "samsung,exynos-ppmu-v2"; 739 reg = <0x104b0000 0x2000>; 740 status = "disabled"; 741 }; 742 743 ppmu_d1_general: ppmu@104c0000 { 744 compatible = "samsung,exynos-ppmu-v2"; 745 reg = <0x104c0000 0x2000>; 746 status = "disabled"; 747 }; 748 749 pinctrl_alive: pinctrl@10580000 { 750 compatible = "samsung,exynos5433-pinctrl"; 751 reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 752 753 wakeup-interrupt-controller { 754 compatible = "samsung,exynos7-wakeup-eint"; 755 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 756 }; 757 }; 758 759 pinctrl_aud: pinctrl@114b0000 { 760 compatible = "samsung,exynos5433-pinctrl"; 761 reg = <0x114b0000 0x1000>; 762 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 763 power-domains = <&pd_aud>; 764 }; 765 766 pinctrl_cpif: pinctrl@10fe0000 { 767 compatible = "samsung,exynos5433-pinctrl"; 768 reg = <0x10fe0000 0x1000>; 769 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 770 }; 771 772 pinctrl_ese: pinctrl@14ca0000 { 773 compatible = "samsung,exynos5433-pinctrl"; 774 reg = <0x14ca0000 0x1000>; 775 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 776 }; 777 778 pinctrl_finger: pinctrl@14cb0000 { 779 compatible = "samsung,exynos5433-pinctrl"; 780 reg = <0x14cb0000 0x1000>; 781 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 782 }; 783 784 pinctrl_fsys: pinctrl@15690000 { 785 compatible = "samsung,exynos5433-pinctrl"; 786 reg = <0x15690000 0x1000>; 787 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 788 }; 789 790 pinctrl_imem: pinctrl@11090000 { 791 compatible = "samsung,exynos5433-pinctrl"; 792 reg = <0x11090000 0x1000>; 793 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 794 }; 795 796 pinctrl_nfc: pinctrl@14cd0000 { 797 compatible = "samsung,exynos5433-pinctrl"; 798 reg = <0x14cd0000 0x1000>; 799 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 800 }; 801 802 pinctrl_peric: pinctrl@14cc0000 { 803 compatible = "samsung,exynos5433-pinctrl"; 804 reg = <0x14cc0000 0x1100>; 805 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 806 }; 807 808 pinctrl_touch: pinctrl@14ce0000 { 809 compatible = "samsung,exynos5433-pinctrl"; 810 reg = <0x14ce0000 0x1100>; 811 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 812 }; 813 814 pmu_system_controller: system-controller@105c0000 { 815 compatible = "samsung,exynos5433-pmu", "syscon"; 816 reg = <0x105c0000 0x5008>; 817 #clock-cells = <1>; 818 clock-names = "clkout16"; 819 clocks = <&xxti>; 820 821 reboot: syscon-reboot { 822 compatible = "syscon-reboot"; 823 regmap = <&pmu_system_controller>; 824 offset = <0x400>; /* SWRESET */ 825 mask = <0x1>; 826 }; 827 }; 828 829 gic: interrupt-controller@11001000 { 830 compatible = "arm,gic-400"; 831 #interrupt-cells = <3>; 832 interrupt-controller; 833 reg = <0x11001000 0x1000>, 834 <0x11002000 0x2000>, 835 <0x11004000 0x2000>, 836 <0x11006000 0x2000>; 837 interrupts = <GIC_PPI 9 0xf04>; 838 }; 839 840 mipi_phy: video-phy { 841 compatible = "samsung,exynos5433-mipi-video-phy"; 842 #phy-cells = <1>; 843 samsung,pmu-syscon = <&pmu_system_controller>; 844 samsung,cam0-sysreg = <&syscon_cam0>; 845 samsung,cam1-sysreg = <&syscon_cam1>; 846 samsung,disp-sysreg = <&syscon_disp>; 847 }; 848 849 decon: decon@13800000 { 850 compatible = "samsung,exynos5433-decon"; 851 reg = <0x13800000 0x2104>; 852 clocks = <&cmu_disp CLK_PCLK_DECON>, 853 <&cmu_disp CLK_ACLK_DECON>, 854 <&cmu_disp CLK_ACLK_SMMU_DECON0X>, 855 <&cmu_disp CLK_ACLK_XIU_DECON0X>, 856 <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 857 <&cmu_disp CLK_ACLK_SMMU_DECON1X>, 858 <&cmu_disp CLK_ACLK_XIU_DECON1X>, 859 <&cmu_disp CLK_PCLK_SMMU_DECON1X>, 860 <&cmu_disp CLK_SCLK_DECON_VCLK>, 861 <&cmu_disp CLK_SCLK_DECON_ECLK>, 862 <&cmu_disp CLK_SCLK_DSD>; 863 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", 864 "aclk_xiu_decon0x", "pclk_smmu_decon0x", 865 "aclk_smmu_decon1x", "aclk_xiu_decon1x", 866 "pclk_smmu_decon1x", "sclk_decon_vclk", 867 "sclk_decon_eclk", "dsd"; 868 power-domains = <&pd_disp>; 869 interrupt-names = "fifo", "vsync", "lcd_sys"; 870 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 873 samsung,disp-sysreg = <&syscon_disp>; 874 status = "disabled"; 875 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; 876 iommu-names = "m0", "m1"; 877 878 ports { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 port@0 { 883 reg = <0>; 884 decon_to_mic: endpoint { 885 remote-endpoint = 886 <&mic_to_decon>; 887 }; 888 }; 889 }; 890 }; 891 892 decon_tv: decon@13880000 { 893 compatible = "samsung,exynos5433-decon-tv"; 894 reg = <0x13880000 0x20b8>; 895 clocks = <&cmu_disp CLK_PCLK_DECON_TV>, 896 <&cmu_disp CLK_ACLK_DECON_TV>, 897 <&cmu_disp CLK_ACLK_SMMU_TV0X>, 898 <&cmu_disp CLK_ACLK_XIU_TV0X>, 899 <&cmu_disp CLK_PCLK_SMMU_TV0X>, 900 <&cmu_disp CLK_ACLK_SMMU_TV1X>, 901 <&cmu_disp CLK_ACLK_XIU_TV1X>, 902 <&cmu_disp CLK_PCLK_SMMU_TV1X>, 903 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, 904 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>, 905 <&cmu_disp CLK_SCLK_DSD>; 906 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", 907 "aclk_xiu_decon0x", "pclk_smmu_decon0x", 908 "aclk_smmu_decon1x", "aclk_xiu_decon1x", 909 "pclk_smmu_decon1x", "sclk_decon_vclk", 910 "sclk_decon_eclk", "dsd"; 911 samsung,disp-sysreg = <&syscon_disp>; 912 power-domains = <&pd_disp>; 913 interrupt-names = "fifo", "vsync", "lcd_sys"; 914 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 917 status = "disabled"; 918 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>; 919 iommu-names = "m0", "m1"; 920 }; 921 922 dsi: dsi@13900000 { 923 compatible = "samsung,exynos5433-mipi-dsi"; 924 reg = <0x13900000 0xC0>; 925 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 926 phys = <&mipi_phy 1>; 927 phy-names = "dsim"; 928 clocks = <&cmu_disp CLK_PCLK_DSIM0>, 929 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, 930 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, 931 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, 932 <&cmu_disp CLK_SCLK_DSIM0>; 933 clock-names = "bus_clk", 934 "phyclk_mipidphy0_bitclkdiv8", 935 "phyclk_mipidphy0_rxclkesc0", 936 "sclk_rgb_vclk_to_dsim0", 937 "sclk_mipi"; 938 power-domains = <&pd_disp>; 939 status = "disabled"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 943 ports { 944 #address-cells = <1>; 945 #size-cells = <0>; 946 947 port@0 { 948 reg = <0>; 949 dsi_to_mic: endpoint { 950 remote-endpoint = <&mic_to_dsi>; 951 }; 952 }; 953 }; 954 }; 955 956 mic: mic@13930000 { 957 compatible = "samsung,exynos5433-mic"; 958 reg = <0x13930000 0x48>; 959 clocks = <&cmu_disp CLK_PCLK_MIC0>, 960 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; 961 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; 962 power-domains = <&pd_disp>; 963 samsung,disp-syscon = <&syscon_disp>; 964 status = "disabled"; 965 966 ports { 967 #address-cells = <1>; 968 #size-cells = <0>; 969 970 port@0 { 971 reg = <0>; 972 mic_to_decon: endpoint { 973 remote-endpoint = 974 <&decon_to_mic>; 975 }; 976 }; 977 978 port@1 { 979 reg = <1>; 980 mic_to_dsi: endpoint { 981 remote-endpoint = <&dsi_to_mic>; 982 }; 983 }; 984 }; 985 }; 986 987 hdmi: hdmi@13970000 { 988 compatible = "samsung,exynos5433-hdmi"; 989 reg = <0x13970000 0x70000>; 990 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&cmu_disp CLK_PCLK_HDMI>, 992 <&cmu_disp CLK_PCLK_HDMIPHY>, 993 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, 994 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, 995 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, 996 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, 997 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, 998 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, 999 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>; 1000 clock-names = "hdmi_pclk", "hdmi_i_pclk", 1001 "i_tmds_clk", "i_pixel_clk", 1002 "tmds_clko", "tmds_clko_user", 1003 "pixel_clko", "pixel_clko_user", 1004 "oscclk", "i_spdif_clk"; 1005 phy = <&hdmiphy>; 1006 ddc = <&hsi2c_11>; 1007 samsung,syscon-phandle = <&pmu_system_controller>; 1008 samsung,sysreg-phandle = <&syscon_disp>; 1009 #sound-dai-cells = <0>; 1010 status = "disabled"; 1011 }; 1012 1013 hdmiphy: hdmiphy@13af0000 { 1014 reg = <0x13af0000 0x80>; 1015 }; 1016 1017 syscon_disp: syscon@13b80000 { 1018 compatible = "syscon"; 1019 reg = <0x13b80000 0x1010>; 1020 }; 1021 1022 syscon_cam0: syscon@120f0000 { 1023 compatible = "syscon"; 1024 reg = <0x120f0000 0x1020>; 1025 }; 1026 1027 syscon_cam1: syscon@145f0000 { 1028 compatible = "syscon"; 1029 reg = <0x145f0000 0x1038>; 1030 }; 1031 1032 gsc_0: video-scaler@13c00000 { 1033 compatible = "samsung,exynos5433-gsc"; 1034 reg = <0x13c00000 0x1000>; 1035 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1036 clock-names = "pclk", "aclk", "aclk_xiu", 1037 "aclk_gsclbend", "gsd"; 1038 clocks = <&cmu_gscl CLK_PCLK_GSCL0>, 1039 <&cmu_gscl CLK_ACLK_GSCL0>, 1040 <&cmu_gscl CLK_ACLK_XIU_GSCLX>, 1041 <&cmu_gscl CLK_ACLK_GSCLBEND_333>, 1042 <&cmu_gscl CLK_ACLK_GSD>; 1043 iommus = <&sysmmu_gscl0>; 1044 power-domains = <&pd_gscl>; 1045 }; 1046 1047 gsc_1: video-scaler@13c10000 { 1048 compatible = "samsung,exynos5433-gsc"; 1049 reg = <0x13c10000 0x1000>; 1050 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1051 clock-names = "pclk", "aclk", "aclk_xiu", 1052 "aclk_gsclbend", "gsd"; 1053 clocks = <&cmu_gscl CLK_PCLK_GSCL1>, 1054 <&cmu_gscl CLK_ACLK_GSCL1>, 1055 <&cmu_gscl CLK_ACLK_XIU_GSCLX>, 1056 <&cmu_gscl CLK_ACLK_GSCLBEND_333>, 1057 <&cmu_gscl CLK_ACLK_GSD>; 1058 iommus = <&sysmmu_gscl1>; 1059 power-domains = <&pd_gscl>; 1060 }; 1061 1062 gsc_2: video-scaler@13c20000 { 1063 compatible = "samsung,exynos5433-gsc"; 1064 reg = <0x13c20000 0x1000>; 1065 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1066 clock-names = "pclk", "aclk", "aclk_xiu", 1067 "aclk_gsclbend", "gsd"; 1068 clocks = <&cmu_gscl CLK_PCLK_GSCL2>, 1069 <&cmu_gscl CLK_ACLK_GSCL2>, 1070 <&cmu_gscl CLK_ACLK_XIU_GSCLX>, 1071 <&cmu_gscl CLK_ACLK_GSCLBEND_333>, 1072 <&cmu_gscl CLK_ACLK_GSD>; 1073 iommus = <&sysmmu_gscl2>; 1074 power-domains = <&pd_gscl>; 1075 }; 1076 1077 gpu: gpu@14ac0000 { 1078 compatible = "samsung,exynos5433-mali", "arm,mali-t760"; 1079 reg = <0x14ac0000 0x5000>; 1080 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 1083 interrupt-names = "job", "mmu", "gpu"; 1084 clocks = <&cmu_g3d CLK_ACLK_G3D>; 1085 clock-names = "core"; 1086 power-domains = <&pd_g3d>; 1087 operating-points-v2 = <&gpu_opp_table>; 1088 status = "disabled"; 1089 1090 gpu_opp_table: opp_table { 1091 compatible = "operating-points-v2"; 1092 1093 opp-160000000 { 1094 opp-hz = /bits/ 64 <160000000>; 1095 opp-microvolt = <1000000>; 1096 }; 1097 opp-267000000 { 1098 opp-hz = /bits/ 64 <267000000>; 1099 opp-microvolt = <1000000>; 1100 }; 1101 opp-350000000 { 1102 opp-hz = /bits/ 64 <350000000>; 1103 opp-microvolt = <1025000>; 1104 }; 1105 opp-420000000 { 1106 opp-hz = /bits/ 64 <420000000>; 1107 opp-microvolt = <1025000>; 1108 }; 1109 opp-500000000 { 1110 opp-hz = /bits/ 64 <500000000>; 1111 opp-microvolt = <1075000>; 1112 }; 1113 opp-550000000 { 1114 opp-hz = /bits/ 64 <550000000>; 1115 opp-microvolt = <1125000>; 1116 }; 1117 opp-600000000 { 1118 opp-hz = /bits/ 64 <600000000>; 1119 opp-microvolt = <1150000>; 1120 }; 1121 opp-700000000 { 1122 opp-hz = /bits/ 64 <700000000>; 1123 opp-microvolt = <1150000>; 1124 }; 1125 }; 1126 }; 1127 1128 scaler_0: scaler@15000000 { 1129 compatible = "samsung,exynos5433-scaler"; 1130 reg = <0x15000000 0x1294>; 1131 interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>; 1132 clock-names = "pclk", "aclk", "aclk_xiu"; 1133 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>, 1134 <&cmu_mscl CLK_ACLK_M2MSCALER0>, 1135 <&cmu_mscl CLK_ACLK_XIU_MSCLX>; 1136 iommus = <&sysmmu_scaler_0>; 1137 power-domains = <&pd_mscl>; 1138 }; 1139 1140 scaler_1: scaler@15010000 { 1141 compatible = "samsung,exynos5433-scaler"; 1142 reg = <0x15010000 0x1294>; 1143 interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>; 1144 clock-names = "pclk", "aclk", "aclk_xiu"; 1145 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>, 1146 <&cmu_mscl CLK_ACLK_M2MSCALER1>, 1147 <&cmu_mscl CLK_ACLK_XIU_MSCLX>; 1148 iommus = <&sysmmu_scaler_1>; 1149 power-domains = <&pd_mscl>; 1150 }; 1151 1152 jpeg: codec@15020000 { 1153 compatible = "samsung,exynos5433-jpeg"; 1154 reg = <0x15020000 0x10000>; 1155 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; 1156 clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; 1157 clocks = <&cmu_mscl CLK_PCLK_JPEG>, 1158 <&cmu_mscl CLK_ACLK_JPEG>, 1159 <&cmu_mscl CLK_ACLK_XIU_MSCLX>, 1160 <&cmu_mscl CLK_SCLK_JPEG>; 1161 iommus = <&sysmmu_jpeg>; 1162 power-domains = <&pd_mscl>; 1163 }; 1164 1165 mfc: codec@152e0000 { 1166 compatible = "samsung,exynos5433-mfc"; 1167 reg = <0x152E0000 0x10000>; 1168 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1169 clock-names = "pclk", "aclk", "aclk_xiu"; 1170 clocks = <&cmu_mfc CLK_PCLK_MFC>, 1171 <&cmu_mfc CLK_ACLK_MFC>, 1172 <&cmu_mfc CLK_ACLK_XIU_MFCX>; 1173 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; 1174 iommu-names = "left", "right"; 1175 power-domains = <&pd_mfc>; 1176 }; 1177 1178 sysmmu_decon0x: sysmmu@13a00000 { 1179 compatible = "samsung,exynos-sysmmu"; 1180 reg = <0x13a00000 0x1000>; 1181 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1182 clock-names = "aclk", "pclk"; 1183 clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>, 1184 <&cmu_disp CLK_PCLK_SMMU_DECON0X>; 1185 power-domains = <&pd_disp>; 1186 #iommu-cells = <0>; 1187 }; 1188 1189 sysmmu_decon1x: sysmmu@13a10000 { 1190 compatible = "samsung,exynos-sysmmu"; 1191 reg = <0x13a10000 0x1000>; 1192 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1193 clock-names = "aclk", "pclk"; 1194 clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>, 1195 <&cmu_disp CLK_PCLK_SMMU_DECON1X>; 1196 #iommu-cells = <0>; 1197 power-domains = <&pd_disp>; 1198 }; 1199 1200 sysmmu_tv0x: sysmmu@13a20000 { 1201 compatible = "samsung,exynos-sysmmu"; 1202 reg = <0x13a20000 0x1000>; 1203 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 1204 clock-names = "aclk", "pclk"; 1205 clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>, 1206 <&cmu_disp CLK_PCLK_SMMU_TV0X>; 1207 #iommu-cells = <0>; 1208 power-domains = <&pd_disp>; 1209 }; 1210 1211 sysmmu_tv1x: sysmmu@13a30000 { 1212 compatible = "samsung,exynos-sysmmu"; 1213 reg = <0x13a30000 0x1000>; 1214 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1215 clock-names = "aclk", "pclk"; 1216 clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>, 1217 <&cmu_disp CLK_PCLK_SMMU_TV1X>; 1218 #iommu-cells = <0>; 1219 power-domains = <&pd_disp>; 1220 }; 1221 1222 sysmmu_gscl0: sysmmu@13c80000 { 1223 compatible = "samsung,exynos-sysmmu"; 1224 reg = <0x13C80000 0x1000>; 1225 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 1226 clock-names = "aclk", "pclk"; 1227 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, 1228 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; 1229 #iommu-cells = <0>; 1230 power-domains = <&pd_gscl>; 1231 }; 1232 1233 sysmmu_gscl1: sysmmu@13c90000 { 1234 compatible = "samsung,exynos-sysmmu"; 1235 reg = <0x13C90000 0x1000>; 1236 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 1237 clock-names = "aclk", "pclk"; 1238 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, 1239 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; 1240 #iommu-cells = <0>; 1241 power-domains = <&pd_gscl>; 1242 }; 1243 1244 sysmmu_gscl2: sysmmu@13ca0000 { 1245 compatible = "samsung,exynos-sysmmu"; 1246 reg = <0x13CA0000 0x1000>; 1247 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 1248 clock-names = "aclk", "pclk"; 1249 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, 1250 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; 1251 #iommu-cells = <0>; 1252 power-domains = <&pd_gscl>; 1253 }; 1254 1255 sysmmu_scaler_0: sysmmu@15040000 { 1256 compatible = "samsung,exynos-sysmmu"; 1257 reg = <0x15040000 0x1000>; 1258 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1259 clock-names = "aclk", "pclk"; 1260 clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>, 1261 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>; 1262 #iommu-cells = <0>; 1263 power-domains = <&pd_mscl>; 1264 }; 1265 1266 sysmmu_scaler_1: sysmmu@15050000 { 1267 compatible = "samsung,exynos-sysmmu"; 1268 reg = <0x15050000 0x1000>; 1269 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; 1270 clock-names = "aclk", "pclk"; 1271 clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>, 1272 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>; 1273 #iommu-cells = <0>; 1274 power-domains = <&pd_mscl>; 1275 }; 1276 1277 sysmmu_jpeg: sysmmu@15060000 { 1278 compatible = "samsung,exynos-sysmmu"; 1279 reg = <0x15060000 0x1000>; 1280 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1281 clock-names = "aclk", "pclk"; 1282 clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>, 1283 <&cmu_mscl CLK_PCLK_SMMU_JPEG>; 1284 #iommu-cells = <0>; 1285 power-domains = <&pd_mscl>; 1286 }; 1287 1288 sysmmu_mfc_0: sysmmu@15200000 { 1289 compatible = "samsung,exynos-sysmmu"; 1290 reg = <0x15200000 0x1000>; 1291 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1292 clock-names = "aclk", "pclk"; 1293 clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>, 1294 <&cmu_mfc CLK_PCLK_SMMU_MFC_0>; 1295 #iommu-cells = <0>; 1296 power-domains = <&pd_mfc>; 1297 }; 1298 1299 sysmmu_mfc_1: sysmmu@15210000 { 1300 compatible = "samsung,exynos-sysmmu"; 1301 reg = <0x15210000 0x1000>; 1302 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1303 clock-names = "aclk", "pclk"; 1304 clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>, 1305 <&cmu_mfc CLK_PCLK_SMMU_MFC_1>; 1306 #iommu-cells = <0>; 1307 power-domains = <&pd_mfc>; 1308 }; 1309 1310 serial_0: serial@14c10000 { 1311 compatible = "samsung,exynos5433-uart"; 1312 reg = <0x14c10000 0x100>; 1313 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1314 clocks = <&cmu_peric CLK_PCLK_UART0>, 1315 <&cmu_peric CLK_SCLK_UART0>; 1316 clock-names = "uart", "clk_uart_baud0"; 1317 pinctrl-names = "default"; 1318 pinctrl-0 = <&uart0_bus>; 1319 status = "disabled"; 1320 }; 1321 1322 serial_1: serial@14c20000 { 1323 compatible = "samsung,exynos5433-uart"; 1324 reg = <0x14c20000 0x100>; 1325 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&cmu_peric CLK_PCLK_UART1>, 1327 <&cmu_peric CLK_SCLK_UART1>; 1328 clock-names = "uart", "clk_uart_baud0"; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&uart1_bus>; 1331 status = "disabled"; 1332 }; 1333 1334 serial_2: serial@14c30000 { 1335 compatible = "samsung,exynos5433-uart"; 1336 reg = <0x14c30000 0x100>; 1337 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&cmu_peric CLK_PCLK_UART2>, 1339 <&cmu_peric CLK_SCLK_UART2>; 1340 clock-names = "uart", "clk_uart_baud0"; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&uart2_bus>; 1343 status = "disabled"; 1344 }; 1345 1346 spi_0: spi@14d20000 { 1347 compatible = "samsung,exynos5433-spi"; 1348 reg = <0x14d20000 0x100>; 1349 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>; 1350 dmas = <&pdma0 9>, <&pdma0 8>; 1351 dma-names = "tx", "rx"; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 clocks = <&cmu_peric CLK_PCLK_SPI0>, 1355 <&cmu_peric CLK_SCLK_SPI0>, 1356 <&cmu_peric CLK_SCLK_IOCLK_SPI0>; 1357 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1358 samsung,spi-src-clk = <0>; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&spi0_bus>; 1361 num-cs = <1>; 1362 status = "disabled"; 1363 }; 1364 1365 spi_1: spi@14d30000 { 1366 compatible = "samsung,exynos5433-spi"; 1367 reg = <0x14d30000 0x100>; 1368 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; 1369 dmas = <&pdma0 11>, <&pdma0 10>; 1370 dma-names = "tx", "rx"; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 clocks = <&cmu_peric CLK_PCLK_SPI1>, 1374 <&cmu_peric CLK_SCLK_SPI1>, 1375 <&cmu_peric CLK_SCLK_IOCLK_SPI1>; 1376 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1377 samsung,spi-src-clk = <0>; 1378 pinctrl-names = "default"; 1379 pinctrl-0 = <&spi1_bus>; 1380 num-cs = <1>; 1381 status = "disabled"; 1382 }; 1383 1384 spi_2: spi@14d40000 { 1385 compatible = "samsung,exynos5433-spi"; 1386 reg = <0x14d40000 0x100>; 1387 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>; 1388 dmas = <&pdma0 13>, <&pdma0 12>; 1389 dma-names = "tx", "rx"; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 clocks = <&cmu_peric CLK_PCLK_SPI2>, 1393 <&cmu_peric CLK_SCLK_SPI2>, 1394 <&cmu_peric CLK_SCLK_IOCLK_SPI2>; 1395 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1396 samsung,spi-src-clk = <0>; 1397 pinctrl-names = "default"; 1398 pinctrl-0 = <&spi2_bus>; 1399 num-cs = <1>; 1400 status = "disabled"; 1401 }; 1402 1403 spi_3: spi@14d50000 { 1404 compatible = "samsung,exynos5433-spi"; 1405 reg = <0x14d50000 0x100>; 1406 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; 1407 dmas = <&pdma0 23>, <&pdma0 22>; 1408 dma-names = "tx", "rx"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 clocks = <&cmu_peric CLK_PCLK_SPI3>, 1412 <&cmu_peric CLK_SCLK_SPI3>, 1413 <&cmu_peric CLK_SCLK_IOCLK_SPI3>; 1414 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1415 samsung,spi-src-clk = <0>; 1416 pinctrl-names = "default"; 1417 pinctrl-0 = <&spi3_bus>; 1418 num-cs = <1>; 1419 status = "disabled"; 1420 }; 1421 1422 spi_4: spi@14d00000 { 1423 compatible = "samsung,exynos5433-spi"; 1424 reg = <0x14d00000 0x100>; 1425 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 1426 dmas = <&pdma0 25>, <&pdma0 24>; 1427 dma-names = "tx", "rx"; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 clocks = <&cmu_peric CLK_PCLK_SPI4>, 1431 <&cmu_peric CLK_SCLK_SPI4>, 1432 <&cmu_peric CLK_SCLK_IOCLK_SPI4>; 1433 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1434 samsung,spi-src-clk = <0>; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&spi4_bus>; 1437 num-cs = <1>; 1438 status = "disabled"; 1439 }; 1440 1441 adc: adc@14d10000 { 1442 compatible = "samsung,exynos7-adc"; 1443 reg = <0x14d10000 0x100>; 1444 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 1445 clock-names = "adc"; 1446 clocks = <&cmu_peric CLK_PCLK_ADCIF>; 1447 #io-channel-cells = <1>; 1448 io-channel-ranges; 1449 status = "disabled"; 1450 }; 1451 1452 i2s1: i2s@14d60000 { 1453 compatible = "samsung,exynos7-i2s"; 1454 reg = <0x14d60000 0x100>; 1455 dmas = <&pdma0 31>, <&pdma0 30>; 1456 dma-names = "tx", "rx"; 1457 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; 1458 clocks = <&cmu_peric CLK_PCLK_I2S1>, 1459 <&cmu_peric CLK_PCLK_I2S1>, 1460 <&cmu_peric CLK_SCLK_I2S1>; 1461 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 1462 #clock-cells = <1>; 1463 samsung,supports-6ch; 1464 samsung,supports-rstclr; 1465 samsung,supports-tdm; 1466 samsung,supports-low-rfs; 1467 #sound-dai-cells = <1>; 1468 status = "disabled"; 1469 }; 1470 1471 pwm: pwm@14dd0000 { 1472 compatible = "samsung,exynos4210-pwm"; 1473 reg = <0x14dd0000 0x100>; 1474 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 1479 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 1480 clocks = <&cmu_peric CLK_PCLK_PWM>; 1481 clock-names = "timers"; 1482 #pwm-cells = <3>; 1483 status = "disabled"; 1484 }; 1485 1486 hsi2c_0: hsi2c@14e40000 { 1487 compatible = "samsung,exynos7-hsi2c"; 1488 reg = <0x14e40000 0x1000>; 1489 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&hs_i2c0_bus>; 1494 clocks = <&cmu_peric CLK_PCLK_HSI2C0>; 1495 clock-names = "hsi2c"; 1496 status = "disabled"; 1497 }; 1498 1499 hsi2c_1: hsi2c@14e50000 { 1500 compatible = "samsung,exynos7-hsi2c"; 1501 reg = <0x14e50000 0x1000>; 1502 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 pinctrl-names = "default"; 1506 pinctrl-0 = <&hs_i2c1_bus>; 1507 clocks = <&cmu_peric CLK_PCLK_HSI2C1>; 1508 clock-names = "hsi2c"; 1509 status = "disabled"; 1510 }; 1511 1512 hsi2c_2: hsi2c@14e60000 { 1513 compatible = "samsung,exynos7-hsi2c"; 1514 reg = <0x14e60000 0x1000>; 1515 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 pinctrl-names = "default"; 1519 pinctrl-0 = <&hs_i2c2_bus>; 1520 clocks = <&cmu_peric CLK_PCLK_HSI2C2>; 1521 clock-names = "hsi2c"; 1522 status = "disabled"; 1523 }; 1524 1525 hsi2c_3: hsi2c@14e70000 { 1526 compatible = "samsung,exynos7-hsi2c"; 1527 reg = <0x14e70000 0x1000>; 1528 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 pinctrl-names = "default"; 1532 pinctrl-0 = <&hs_i2c3_bus>; 1533 clocks = <&cmu_peric CLK_PCLK_HSI2C3>; 1534 clock-names = "hsi2c"; 1535 status = "disabled"; 1536 }; 1537 1538 hsi2c_4: hsi2c@14ec0000 { 1539 compatible = "samsung,exynos7-hsi2c"; 1540 reg = <0x14ec0000 0x1000>; 1541 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 pinctrl-names = "default"; 1545 pinctrl-0 = <&hs_i2c4_bus>; 1546 clocks = <&cmu_peric CLK_PCLK_HSI2C4>; 1547 clock-names = "hsi2c"; 1548 status = "disabled"; 1549 }; 1550 1551 hsi2c_5: hsi2c@14ed0000 { 1552 compatible = "samsung,exynos7-hsi2c"; 1553 reg = <0x14ed0000 0x1000>; 1554 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&hs_i2c5_bus>; 1559 clocks = <&cmu_peric CLK_PCLK_HSI2C5>; 1560 clock-names = "hsi2c"; 1561 status = "disabled"; 1562 }; 1563 1564 hsi2c_6: hsi2c@14ee0000 { 1565 compatible = "samsung,exynos7-hsi2c"; 1566 reg = <0x14ee0000 0x1000>; 1567 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 pinctrl-names = "default"; 1571 pinctrl-0 = <&hs_i2c6_bus>; 1572 clocks = <&cmu_peric CLK_PCLK_HSI2C6>; 1573 clock-names = "hsi2c"; 1574 status = "disabled"; 1575 }; 1576 1577 hsi2c_7: hsi2c@14ef0000 { 1578 compatible = "samsung,exynos7-hsi2c"; 1579 reg = <0x14ef0000 0x1000>; 1580 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>; 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&hs_i2c7_bus>; 1585 clocks = <&cmu_peric CLK_PCLK_HSI2C7>; 1586 clock-names = "hsi2c"; 1587 status = "disabled"; 1588 }; 1589 1590 hsi2c_8: hsi2c@14d90000 { 1591 compatible = "samsung,exynos7-hsi2c"; 1592 reg = <0x14d90000 0x1000>; 1593 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&hs_i2c8_bus>; 1598 clocks = <&cmu_peric CLK_PCLK_HSI2C8>; 1599 clock-names = "hsi2c"; 1600 status = "disabled"; 1601 }; 1602 1603 hsi2c_9: hsi2c@14da0000 { 1604 compatible = "samsung,exynos7-hsi2c"; 1605 reg = <0x14da0000 0x1000>; 1606 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 pinctrl-names = "default"; 1610 pinctrl-0 = <&hs_i2c9_bus>; 1611 clocks = <&cmu_peric CLK_PCLK_HSI2C9>; 1612 clock-names = "hsi2c"; 1613 status = "disabled"; 1614 }; 1615 1616 hsi2c_10: hsi2c@14de0000 { 1617 compatible = "samsung,exynos7-hsi2c"; 1618 reg = <0x14de0000 0x1000>; 1619 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&hs_i2c10_bus>; 1624 clocks = <&cmu_peric CLK_PCLK_HSI2C10>; 1625 clock-names = "hsi2c"; 1626 status = "disabled"; 1627 }; 1628 1629 hsi2c_11: hsi2c@14df0000 { 1630 compatible = "samsung,exynos7-hsi2c"; 1631 reg = <0x14df0000 0x1000>; 1632 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 pinctrl-names = "default"; 1636 pinctrl-0 = <&hs_i2c11_bus>; 1637 clocks = <&cmu_peric CLK_PCLK_HSI2C11>; 1638 clock-names = "hsi2c"; 1639 status = "disabled"; 1640 }; 1641 1642 usbdrd30: usbdrd { 1643 compatible = "samsung,exynos5433-dwusb3"; 1644 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, 1645 <&cmu_fsys CLK_SCLK_USBDRD30>, 1646 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, 1647 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>; 1648 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; 1649 #address-cells = <1>; 1650 #size-cells = <1>; 1651 ranges; 1652 status = "disabled"; 1653 1654 usbdrd_dwc3: dwc3@15400000 { 1655 compatible = "snps,dwc3"; 1656 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>, 1657 <&cmu_fsys CLK_ACLK_USBDRD30>, 1658 <&cmu_fsys CLK_SCLK_USBDRD30>; 1659 clock-names = "ref", "bus_early", "suspend"; 1660 reg = <0x15400000 0x10000>; 1661 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1662 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; 1663 phy-names = "usb2-phy", "usb3-phy"; 1664 }; 1665 }; 1666 1667 usbdrd30_phy: phy@15500000 { 1668 compatible = "samsung,exynos5433-usbdrd-phy"; 1669 reg = <0x15500000 0x100>; 1670 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>, 1671 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, 1672 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, 1673 <&cmu_fsys CLK_SCLK_USBDRD30>; 1674 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", 1675 "itp"; 1676 #phy-cells = <1>; 1677 samsung,pmu-syscon = <&pmu_system_controller>; 1678 status = "disabled"; 1679 }; 1680 1681 usbhost30_phy: phy@15580000 { 1682 compatible = "samsung,exynos5433-usbdrd-phy"; 1683 reg = <0x15580000 0x100>; 1684 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, 1685 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, 1686 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, 1687 <&cmu_fsys CLK_SCLK_USBHOST30>; 1688 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", 1689 "itp"; 1690 #phy-cells = <1>; 1691 samsung,pmu-syscon = <&pmu_system_controller>; 1692 status = "disabled"; 1693 }; 1694 1695 usbhost30: usbhost { 1696 compatible = "samsung,exynos5433-dwusb3"; 1697 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, 1698 <&cmu_fsys CLK_SCLK_USBHOST30>, 1699 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, 1700 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>; 1701 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; 1702 #address-cells = <1>; 1703 #size-cells = <1>; 1704 ranges; 1705 status = "disabled"; 1706 1707 usbhost_dwc3: dwc3@15a00000 { 1708 compatible = "snps,dwc3"; 1709 clocks = <&cmu_fsys CLK_SCLK_USBHOST30>, 1710 <&cmu_fsys CLK_ACLK_USBHOST30>, 1711 <&cmu_fsys CLK_SCLK_USBHOST30>; 1712 clock-names = "ref", "bus_early", "suspend"; 1713 reg = <0x15a00000 0x10000>; 1714 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1715 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; 1716 phy-names = "usb2-phy", "usb3-phy"; 1717 }; 1718 }; 1719 1720 mshc_0: mshc@15540000 { 1721 compatible = "samsung,exynos7-dw-mshc-smu"; 1722 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 reg = <0x15540000 0x2000>; 1726 clocks = <&cmu_fsys CLK_ACLK_MMC0>, 1727 <&cmu_fsys CLK_SCLK_MMC0>; 1728 clock-names = "biu", "ciu"; 1729 fifo-depth = <0x40>; 1730 status = "disabled"; 1731 }; 1732 1733 mshc_1: mshc@15550000 { 1734 compatible = "samsung,exynos7-dw-mshc-smu"; 1735 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 reg = <0x15550000 0x2000>; 1739 clocks = <&cmu_fsys CLK_ACLK_MMC1>, 1740 <&cmu_fsys CLK_SCLK_MMC1>; 1741 clock-names = "biu", "ciu"; 1742 fifo-depth = <0x40>; 1743 status = "disabled"; 1744 }; 1745 1746 mshc_2: mshc@15560000 { 1747 compatible = "samsung,exynos7-dw-mshc-smu"; 1748 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1749 #address-cells = <1>; 1750 #size-cells = <0>; 1751 reg = <0x15560000 0x2000>; 1752 clocks = <&cmu_fsys CLK_ACLK_MMC2>, 1753 <&cmu_fsys CLK_SCLK_MMC2>; 1754 clock-names = "biu", "ciu"; 1755 fifo-depth = <0x40>; 1756 status = "disabled"; 1757 }; 1758 1759 pdma0: pdma@15610000 { 1760 compatible = "arm,pl330", "arm,primecell"; 1761 reg = <0x15610000 0x1000>; 1762 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1763 clocks = <&cmu_fsys CLK_PDMA0>; 1764 clock-names = "apb_pclk"; 1765 #dma-cells = <1>; 1766 #dma-channels = <8>; 1767 #dma-requests = <32>; 1768 }; 1769 1770 pdma1: pdma@15600000 { 1771 compatible = "arm,pl330", "arm,primecell"; 1772 reg = <0x15600000 0x1000>; 1773 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1774 clocks = <&cmu_fsys CLK_PDMA1>; 1775 clock-names = "apb_pclk"; 1776 #dma-cells = <1>; 1777 #dma-channels = <8>; 1778 #dma-requests = <32>; 1779 }; 1780 1781 audio-subsystem@11400000 { 1782 compatible = "samsung,exynos5433-lpass"; 1783 reg = <0x11400000 0x100>, <0x11500000 0x08>; 1784 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; 1785 clock-names = "sfr0_ctrl"; 1786 samsung,pmu-syscon = <&pmu_system_controller>; 1787 power-domains = <&pd_aud>; 1788 #address-cells = <1>; 1789 #size-cells = <1>; 1790 ranges; 1791 1792 adma: adma@11420000 { 1793 compatible = "arm,pl330", "arm,primecell"; 1794 reg = <0x11420000 0x1000>; 1795 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1796 clocks = <&cmu_aud CLK_ACLK_DMAC>; 1797 clock-names = "apb_pclk"; 1798 #dma-cells = <1>; 1799 #dma-channels = <8>; 1800 #dma-requests = <32>; 1801 power-domains = <&pd_aud>; 1802 }; 1803 1804 i2s0: i2s@11440000 { 1805 compatible = "samsung,exynos7-i2s"; 1806 reg = <0x11440000 0x100>; 1807 dmas = <&adma 0>, <&adma 2>; 1808 dma-names = "tx", "rx"; 1809 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, 1813 <&cmu_aud CLK_SCLK_AUD_I2S>, 1814 <&cmu_aud CLK_SCLK_I2S_BCLK>; 1815 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 1816 #clock-cells = <1>; 1817 pinctrl-names = "default"; 1818 pinctrl-0 = <&i2s0_bus>; 1819 power-domains = <&pd_aud>; 1820 #sound-dai-cells = <1>; 1821 status = "disabled"; 1822 }; 1823 1824 serial_3: serial@11460000 { 1825 compatible = "samsung,exynos5433-uart"; 1826 reg = <0x11460000 0x100>; 1827 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1828 clocks = <&cmu_aud CLK_PCLK_AUD_UART>, 1829 <&cmu_aud CLK_SCLK_AUD_UART>; 1830 clock-names = "uart", "clk_uart_baud0"; 1831 pinctrl-names = "default"; 1832 pinctrl-0 = <&uart_aud_bus>; 1833 power-domains = <&pd_aud>; 1834 status = "disabled"; 1835 }; 1836 }; 1837 }; 1838 1839 timer: timer { 1840 compatible = "arm,armv8-timer"; 1841 interrupts = <GIC_PPI 13 1842 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 1843 <GIC_PPI 14 1844 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 1845 <GIC_PPI 11 1846 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 1847 <GIC_PPI 10 1848 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1849 }; 1850}; 1851 1852#include "exynos5433-bus.dtsi" 1853#include "exynos5433-pinctrl.dtsi" 1854#include "exynos5433-tmu.dtsi" 1855