1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos5433 TM2 board device tree source 4 * 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6 * 7 * Common device tree source file for Samsung's TM2 and TM2E boards 8 * which are based on Samsung Exynos5433 SoC. 9 */ 10 11/dts-v1/; 12#include "exynos5433.dtsi" 13#include <dt-bindings/clock/samsung,s2mps11.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/input/input.h> 16#include <dt-bindings/interrupt-controller/irq.h> 17#include <dt-bindings/sound/samsung-i2s.h> 18 19/ { 20 aliases { 21 gsc0 = &gsc_0; 22 gsc1 = &gsc_1; 23 gsc2 = &gsc_2; 24 mmc0 = &mshc_0; 25 mmc2 = &mshc_2; 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_aud; 28 pinctrl2 = &pinctrl_cpif; 29 pinctrl3 = &pinctrl_ese; 30 pinctrl4 = &pinctrl_finger; 31 pinctrl5 = &pinctrl_fsys; 32 pinctrl6 = &pinctrl_imem; 33 pinctrl7 = &pinctrl_nfc; 34 pinctrl8 = &pinctrl_peric; 35 pinctrl9 = &pinctrl_touch; 36 serial0 = &serial_0; 37 serial1 = &serial_1; 38 serial2 = &serial_2; 39 serial3 = &serial_3; 40 spi0 = &spi_0; 41 spi1 = &spi_1; 42 spi2 = &spi_2; 43 spi3 = &spi_3; 44 spi4 = &spi_4; 45 }; 46 47 chosen { 48 stdout-path = &serial_1; 49 }; 50 51 memory@20000000 { 52 device_type = "memory"; 53 reg = <0x0 0x20000000 0x0 0xc0000000>; 54 }; 55 56 gpio-keys { 57 compatible = "gpio-keys"; 58 59 power-key { 60 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>; 61 linux,code = <KEY_POWER>; 62 label = "power key"; 63 debounce-interval = <10>; 64 }; 65 66 volume-up-key { 67 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>; 68 linux,code = <KEY_VOLUMEUP>; 69 label = "volume-up key"; 70 debounce-interval = <10>; 71 }; 72 73 volume-down-key { 74 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>; 75 linux,code = <KEY_VOLUMEDOWN>; 76 label = "volume-down key"; 77 debounce-interval = <10>; 78 }; 79 80 homepage-key { 81 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>; 82 linux,code = <KEY_MENU>; 83 label = "homepage key"; 84 debounce-interval = <10>; 85 }; 86 }; 87 88 i2c_max98504: i2c-gpio-0 { 89 compatible = "i2c-gpio"; 90 sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>; 91 scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>; 92 i2c-gpio,delay-us = <2>; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 96 max98504: amplifier@31 { 97 compatible = "maxim,max98504"; 98 reg = <0x31>; 99 100 DIOVDD-supply = <&ldo3_reg>; 101 DVDD-supply = <&ldo3_reg>; 102 PVDD-supply = <&vph_pwr_regulator>; 103 }; 104 }; 105 106 vph_pwr_regulator: regulator-vph-pwr { 107 compatible = "regulator-fixed"; 108 regulator-name = "VPH_PWR"; 109 regulator-min-microvolt = <4200000>; 110 regulator-max-microvolt = <4200000>; 111 }; 112 113 irda_regulator: regulator-irda { 114 compatible = "regulator-fixed"; 115 enable-active-high; 116 gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>; 117 regulator-name = "irda_regulator"; 118 }; 119 120 sound { 121 compatible = "samsung,tm2-audio"; 122 audio-codec = <&wm5110>, <&hdmi>; 123 i2s-controller = <&i2s0 0>, <&i2s1 0>; 124 audio-amplifier = <&max98504>; 125 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>; 126 model = "wm5110"; 127 samsung,audio-routing = 128 /* Headphone */ 129 "HP", "HPOUT1L", 130 "HP", "HPOUT1R", 131 132 /* Speaker */ 133 "SPK", "SPKOUT", 134 "SPKOUT", "HPOUT2L", 135 "SPKOUT", "HPOUT2R", 136 137 /* Receiver */ 138 "RCV", "HPOUT3L", 139 "RCV", "HPOUT3R"; 140 status = "okay"; 141 }; 142}; 143 144&adc { 145 vdd-supply = <&ldo3_reg>; 146 status = "okay"; 147 148 thermistor-ap { 149 compatible = "murata,ncp03wf104"; 150 pullup-uv = <1800000>; 151 pullup-ohm = <100000>; 152 pulldown-ohm = <0>; 153 io-channels = <&adc 0>; 154 }; 155 156 thermistor-battery { 157 compatible = "murata,ncp03wf104"; 158 pullup-uv = <1800000>; 159 pullup-ohm = <100000>; 160 pulldown-ohm = <0>; 161 io-channels = <&adc 1>; 162 #thermal-sensor-cells = <0>; 163 }; 164 165 thermistor-charger { 166 compatible = "murata,ncp03wf104"; 167 pullup-uv = <1800000>; 168 pullup-ohm = <100000>; 169 pulldown-ohm = <0>; 170 io-channels = <&adc 2>; 171 }; 172}; 173 174&bus_g2d_400 { 175 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>; 176 vdd-supply = <&buck4_reg>; 177 exynos,saturation-ratio = <10>; 178 status = "okay"; 179}; 180 181&bus_g2d_266 { 182 devfreq = <&bus_g2d_400>; 183 status = "okay"; 184}; 185 186&bus_gscl { 187 devfreq = <&bus_g2d_400>; 188 status = "okay"; 189}; 190 191&bus_hevc { 192 devfreq = <&bus_g2d_400>; 193 status = "okay"; 194}; 195 196&bus_jpeg { 197 devfreq = <&bus_g2d_400>; 198 status = "okay"; 199}; 200 201&bus_mfc { 202 devfreq = <&bus_g2d_400>; 203 status = "okay"; 204}; 205 206&bus_mscl { 207 devfreq = <&bus_g2d_400>; 208 status = "okay"; 209}; 210 211&bus_noc0 { 212 devfreq = <&bus_g2d_400>; 213 status = "okay"; 214}; 215 216&bus_noc1 { 217 devfreq = <&bus_g2d_400>; 218 status = "okay"; 219}; 220 221&bus_noc2 { 222 devfreq = <&bus_g2d_400>; 223 status = "okay"; 224}; 225 226&cmu_aud { 227 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>, 228 <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>, 229 <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>, 230 <&cmu_top CLK_MOUT_AUD_PLL>, 231 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, 232 <&cmu_top CLK_MOUT_SCLK_AUDIO0>, 233 <&cmu_top CLK_MOUT_SCLK_AUDIO1>, 234 <&cmu_top CLK_MOUT_SCLK_SPDIF>, 235 236 <&cmu_aud CLK_DIV_AUD_CA5>, 237 <&cmu_aud CLK_DIV_ACLK_AUD>, 238 <&cmu_aud CLK_DIV_PCLK_DBG_AUD>, 239 <&cmu_aud CLK_DIV_SCLK_AUD_I2S>, 240 <&cmu_aud CLK_DIV_SCLK_AUD_PCM>, 241 <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>, 242 <&cmu_aud CLK_DIV_SCLK_AUD_UART>, 243 <&cmu_top CLK_DIV_SCLK_AUDIO0>, 244 <&cmu_top CLK_DIV_SCLK_AUDIO1>, 245 <&cmu_top CLK_DIV_SCLK_PCM1>, 246 <&cmu_top CLK_DIV_SCLK_I2S1>; 247 248 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>, 249 <&cmu_aud CLK_MOUT_AUD_PLL_USER>, 250 <&cmu_aud CLK_MOUT_AUD_PLL_USER>, 251 <&cmu_top CLK_FOUT_AUD_PLL>, 252 <&cmu_top CLK_MOUT_AUD_PLL>, 253 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, 254 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, 255 <&cmu_top CLK_SCLK_AUDIO0>; 256 257 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, 258 <196608001>, <65536001>, <32768001>, <49152001>, 259 <2048001>, <24576001>, <196608001>, 260 <24576001>, <98304001>, <2048001>, <49152001>; 261}; 262 263&cmu_fsys { 264 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, 265 <&cmu_top CLK_MOUT_SCLK_USBHOST30>, 266 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, 267 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, 268 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, 269 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, 270 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, 271 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, 272 <&cmu_top CLK_DIV_SCLK_USBDRD30>, 273 <&cmu_top CLK_DIV_SCLK_USBHOST30>; 274 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>, 275 <&cmu_top CLK_MOUT_BUS_PLL_USER>, 276 <&cmu_top CLK_SCLK_USBDRD30_FSYS>, 277 <&cmu_top CLK_SCLK_USBHOST30_FSYS>, 278 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, 279 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, 280 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, 281 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; 282 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, 283 <66700000>, <66700000>; 284}; 285 286&cmu_gscl { 287 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>, 288 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>; 289 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>, 290 <&cmu_top CLK_ACLK_GSCL_333>; 291}; 292 293&cmu_mfc { 294 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>; 295 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>; 296}; 297 298&cmu_mif { 299 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>; 300 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>; 301 assigned-clock-rates = <0>, <333000000>; 302}; 303 304&cmu_mscl { 305 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>, 306 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, 307 <&cmu_mscl CLK_MOUT_SCLK_JPEG>, 308 <&cmu_top CLK_MOUT_SCLK_JPEG_A>; 309 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>, 310 <&cmu_top CLK_SCLK_JPEG_MSCL>, 311 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, 312 <&cmu_top CLK_MOUT_BUS_PLL_USER>; 313}; 314 315&cmu_top { 316 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>; 317 assigned-clock-rates = <196608001>; 318}; 319 320&cpu0 { 321 cpu-supply = <&buck3_reg>; 322}; 323 324&cpu4 { 325 cpu-supply = <&buck2_reg>; 326}; 327 328&decon { 329 status = "okay"; 330}; 331 332&decon_tv { 333 status = "okay"; 334 335 ports { 336 #address-cells = <1>; 337 #size-cells = <0>; 338 339 port@0 { 340 reg = <0>; 341 tv_to_hdmi: endpoint { 342 remote-endpoint = <&hdmi_to_tv>; 343 }; 344 }; 345 }; 346}; 347 348&dsi { 349 status = "okay"; 350 vddcore-supply = <&ldo6_reg>; 351 vddio-supply = <&ldo7_reg>; 352 samsung,burst-clock-frequency = <512000000>; 353 samsung,esc-clock-frequency = <16000000>; 354 samsung,pll-clock-frequency = <24000000>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&te_irq>; 357}; 358 359&gpu { 360 mali-supply = <&buck6_reg>; 361 status = "okay"; 362}; 363 364&hdmi { 365 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>; 366 status = "okay"; 367 vdd-supply = <&ldo6_reg>; 368 vdd_osc-supply = <&ldo7_reg>; 369 vdd_pll-supply = <&ldo6_reg>; 370 371 ports { 372 #address-cells = <1>; 373 #size-cells = <0>; 374 375 port@0 { 376 reg = <0>; 377 hdmi_to_tv: endpoint { 378 remote-endpoint = <&tv_to_hdmi>; 379 }; 380 }; 381 382 port@1 { 383 reg = <1>; 384 hdmi_to_mhl: endpoint { 385 remote-endpoint = <&mhl_to_hdmi>; 386 }; 387 }; 388 }; 389}; 390 391&hsi2c_0 { 392 status = "okay"; 393 clock-frequency = <2500000>; 394 395 pmic@66 { 396 compatible = "samsung,s2mps13-pmic"; 397 interrupt-parent = <&gpa0>; 398 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 399 reg = <0x66>; 400 samsung,s2mps11-wrstbi-ground; 401 wakeup-source; 402 403 s2mps13_osc: clocks { 404 compatible = "samsung,s2mps13-clk"; 405 #clock-cells = <1>; 406 clock-output-names = "s2mps13_ap", "s2mps13_cp", 407 "s2mps13_bt"; 408 }; 409 410 regulators { 411 ldo1_reg: LDO1 { 412 regulator-name = "VDD_ALIVE_0.9V_AP"; 413 regulator-min-microvolt = <900000>; 414 regulator-max-microvolt = <900000>; 415 regulator-always-on; 416 }; 417 418 ldo2_reg: LDO2 { 419 regulator-name = "VDDQ_MMC2_2.8V_AP"; 420 regulator-min-microvolt = <2800000>; 421 regulator-max-microvolt = <2800000>; 422 regulator-always-on; 423 regulator-state-mem { 424 regulator-off-in-suspend; 425 }; 426 }; 427 428 ldo3_reg: LDO3 { 429 regulator-name = "VDD1_E_1.8V_AP"; 430 regulator-min-microvolt = <1800000>; 431 regulator-max-microvolt = <1800000>; 432 regulator-always-on; 433 }; 434 435 ldo4_reg: LDO4 { 436 regulator-name = "VDD10_MIF_PLL_1.0V_AP"; 437 regulator-min-microvolt = <1300000>; 438 regulator-max-microvolt = <1300000>; 439 regulator-always-on; 440 regulator-state-mem { 441 regulator-off-in-suspend; 442 }; 443 }; 444 445 ldo5_reg: LDO5 { 446 regulator-name = "VDD10_DPLL_1.0V_AP"; 447 regulator-min-microvolt = <1000000>; 448 regulator-max-microvolt = <1000000>; 449 regulator-always-on; 450 regulator-state-mem { 451 regulator-off-in-suspend; 452 }; 453 }; 454 455 ldo6_reg: LDO6 { 456 regulator-name = "VDD10_MIPI2L_1.0V_AP"; 457 regulator-min-microvolt = <1000000>; 458 regulator-max-microvolt = <1000000>; 459 regulator-state-mem { 460 regulator-off-in-suspend; 461 }; 462 }; 463 464 ldo7_reg: LDO7 { 465 regulator-name = "VDD18_MIPI2L_1.8V_AP"; 466 regulator-min-microvolt = <1800000>; 467 regulator-max-microvolt = <1800000>; 468 regulator-always-on; 469 regulator-state-mem { 470 regulator-off-in-suspend; 471 }; 472 }; 473 474 ldo8_reg: LDO8 { 475 regulator-name = "VDD18_LLI_1.8V_AP"; 476 regulator-min-microvolt = <1800000>; 477 regulator-max-microvolt = <1800000>; 478 regulator-always-on; 479 regulator-state-mem { 480 regulator-off-in-suspend; 481 }; 482 }; 483 484 ldo9_reg: LDO9 { 485 regulator-name = "VDD18_ABB_ETC_1.8V_AP"; 486 regulator-min-microvolt = <1800000>; 487 regulator-max-microvolt = <1800000>; 488 regulator-always-on; 489 regulator-state-mem { 490 regulator-off-in-suspend; 491 }; 492 }; 493 494 ldo10_reg: LDO10 { 495 regulator-name = "VDD33_USB30_3.0V_AP"; 496 regulator-min-microvolt = <3000000>; 497 regulator-max-microvolt = <3000000>; 498 regulator-state-mem { 499 regulator-off-in-suspend; 500 }; 501 }; 502 503 ldo11_reg: LDO11 { 504 regulator-name = "VDD_INT_M_1.0V_AP"; 505 regulator-min-microvolt = <1000000>; 506 regulator-max-microvolt = <1000000>; 507 regulator-always-on; 508 regulator-state-mem { 509 regulator-off-in-suspend; 510 }; 511 }; 512 513 ldo12_reg: LDO12 { 514 regulator-name = "VDD_KFC_M_1.1V_AP"; 515 regulator-min-microvolt = <800000>; 516 regulator-max-microvolt = <1350000>; 517 regulator-always-on; 518 }; 519 520 ldo13_reg: LDO13 { 521 regulator-name = "VDD_G3D_M_0.95V_AP"; 522 regulator-min-microvolt = <950000>; 523 regulator-max-microvolt = <950000>; 524 regulator-always-on; 525 regulator-state-mem { 526 regulator-off-in-suspend; 527 }; 528 }; 529 530 ldo14_reg: LDO14 { 531 regulator-name = "VDDQ_M1_LDO_1.2V_AP"; 532 regulator-min-microvolt = <1200000>; 533 regulator-max-microvolt = <1200000>; 534 regulator-always-on; 535 regulator-state-mem { 536 regulator-off-in-suspend; 537 }; 538 }; 539 540 ldo15_reg: LDO15 { 541 regulator-name = "VDDQ_M2_LDO_1.2V_AP"; 542 regulator-min-microvolt = <1200000>; 543 regulator-max-microvolt = <1200000>; 544 regulator-always-on; 545 regulator-state-mem { 546 regulator-off-in-suspend; 547 }; 548 }; 549 550 ldo16_reg: LDO16 { 551 regulator-name = "VDDQ_EFUSE"; 552 regulator-min-microvolt = <1400000>; 553 regulator-max-microvolt = <3400000>; 554 regulator-always-on; 555 }; 556 557 ldo17_reg: LDO17 { 558 regulator-name = "V_TFLASH_2.8V_AP"; 559 regulator-min-microvolt = <2800000>; 560 regulator-max-microvolt = <2800000>; 561 }; 562 563 ldo18_reg: LDO18 { 564 regulator-name = "V_CODEC_1.8V_AP"; 565 regulator-min-microvolt = <1800000>; 566 regulator-max-microvolt = <1800000>; 567 }; 568 569 ldo19_reg: LDO19 { 570 regulator-name = "VDDA_1.8V_COMP"; 571 regulator-min-microvolt = <1800000>; 572 regulator-max-microvolt = <1800000>; 573 regulator-always-on; 574 }; 575 576 ldo20_reg: LDO20 { 577 regulator-name = "VCC_2.8V_AP"; 578 regulator-min-microvolt = <2800000>; 579 regulator-max-microvolt = <2800000>; 580 regulator-always-on; 581 }; 582 583 ldo21_reg: LDO21 { 584 regulator-name = "VT_CAM_1.8V"; 585 regulator-min-microvolt = <1800000>; 586 regulator-max-microvolt = <1800000>; 587 }; 588 589 ldo22_reg: LDO22 { 590 regulator-name = "CAM_IO_1.8V_AP"; 591 regulator-min-microvolt = <1800000>; 592 regulator-max-microvolt = <1800000>; 593 }; 594 595 ldo23_reg: LDO23 { 596 regulator-name = "CAM_SEN_CORE_1.05V_AP"; 597 regulator-min-microvolt = <1050000>; 598 regulator-max-microvolt = <1050000>; 599 }; 600 601 ldo24_reg: LDO24 { 602 regulator-name = "VT_CAM_1.2V"; 603 regulator-min-microvolt = <1200000>; 604 regulator-max-microvolt = <1200000>; 605 }; 606 607 ldo25_reg: LDO25 { 608 regulator-name = "UNUSED_LDO25"; 609 regulator-min-microvolt = <2800000>; 610 regulator-max-microvolt = <2800000>; 611 }; 612 613 ldo26_reg: LDO26 { 614 regulator-name = "CAM_AF_2.8V_AP"; 615 regulator-min-microvolt = <2800000>; 616 regulator-max-microvolt = <2800000>; 617 }; 618 619 ldo27_reg: LDO27 { 620 regulator-name = "VCC_3.0V_LCD_AP"; 621 regulator-min-microvolt = <3000000>; 622 regulator-max-microvolt = <3000000>; 623 }; 624 625 ldo28_reg: LDO28 { 626 regulator-name = "VCC_1.8V_LCD_AP"; 627 regulator-min-microvolt = <1800000>; 628 regulator-max-microvolt = <1800000>; 629 }; 630 631 ldo29_reg: LDO29 { 632 regulator-name = "VT_CAM_2.8V"; 633 regulator-min-microvolt = <3000000>; 634 regulator-max-microvolt = <3000000>; 635 }; 636 637 ldo30_reg: LDO30 { 638 regulator-name = "TSP_AVDD_3.3V_AP"; 639 regulator-min-microvolt = <3300000>; 640 regulator-max-microvolt = <3300000>; 641 }; 642 643 ldo31_reg: LDO31 { 644 /* 645 * LDO31 differs from target to target, 646 * its definition is in the .dts 647 */ 648 }; 649 650 ldo32_reg: LDO32 { 651 regulator-name = "VTOUCH_1.8V_AP"; 652 regulator-min-microvolt = <1800000>; 653 regulator-max-microvolt = <1800000>; 654 }; 655 656 ldo33_reg: LDO33 { 657 regulator-name = "VTOUCH_LED_3.3V"; 658 regulator-min-microvolt = <2500000>; 659 regulator-max-microvolt = <3300000>; 660 regulator-ramp-delay = <12500>; 661 }; 662 663 ldo34_reg: LDO34 { 664 regulator-name = "VCC_1.8V_MHL_AP"; 665 regulator-min-microvolt = <1000000>; 666 regulator-max-microvolt = <2100000>; 667 }; 668 669 ldo35_reg: LDO35 { 670 regulator-name = "OIS_VM_2.8V"; 671 regulator-min-microvolt = <1800000>; 672 regulator-max-microvolt = <2800000>; 673 }; 674 675 ldo36_reg: LDO36 { 676 regulator-name = "VSIL_1.0V"; 677 regulator-min-microvolt = <1000000>; 678 regulator-max-microvolt = <1000000>; 679 }; 680 681 ldo37_reg: LDO37 { 682 regulator-name = "VF_1.8V"; 683 regulator-min-microvolt = <1800000>; 684 regulator-max-microvolt = <1800000>; 685 }; 686 687 ldo38_reg: LDO38 { 688 /* 689 * LDO38 differs from target to target, 690 * its definition is in the .dts 691 */ 692 }; 693 694 ldo39_reg: LDO39 { 695 regulator-name = "V_HRM_1.8V"; 696 regulator-min-microvolt = <1800000>; 697 regulator-max-microvolt = <1800000>; 698 }; 699 700 ldo40_reg: LDO40 { 701 regulator-name = "V_HRM_3.3V"; 702 regulator-min-microvolt = <3300000>; 703 regulator-max-microvolt = <3300000>; 704 }; 705 706 buck1_reg: BUCK1 { 707 regulator-name = "VDD_MIF_0.9V_AP"; 708 regulator-min-microvolt = <600000>; 709 regulator-max-microvolt = <1500000>; 710 regulator-always-on; 711 regulator-state-mem { 712 regulator-off-in-suspend; 713 }; 714 }; 715 716 buck2_reg: BUCK2 { 717 regulator-name = "VDD_EGL_1.0V_AP"; 718 regulator-min-microvolt = <900000>; 719 regulator-max-microvolt = <1300000>; 720 regulator-always-on; 721 regulator-state-mem { 722 regulator-off-in-suspend; 723 }; 724 }; 725 726 buck3_reg: BUCK3 { 727 regulator-name = "VDD_KFC_1.0V_AP"; 728 regulator-min-microvolt = <800000>; 729 regulator-max-microvolt = <1200000>; 730 regulator-always-on; 731 regulator-state-mem { 732 regulator-off-in-suspend; 733 }; 734 }; 735 736 buck4_reg: BUCK4 { 737 regulator-name = "VDD_INT_0.95V_AP"; 738 regulator-min-microvolt = <600000>; 739 regulator-max-microvolt = <1500000>; 740 regulator-always-on; 741 regulator-state-mem { 742 regulator-off-in-suspend; 743 }; 744 }; 745 746 buck5_reg: BUCK5 { 747 regulator-name = "VDD_DISP_CAM0_0.9V_AP"; 748 regulator-min-microvolt = <600000>; 749 regulator-max-microvolt = <1500000>; 750 regulator-always-on; 751 regulator-state-mem { 752 regulator-off-in-suspend; 753 }; 754 }; 755 756 buck6_reg: BUCK6 { 757 regulator-name = "VDD_G3D_0.9V_AP"; 758 regulator-min-microvolt = <600000>; 759 regulator-max-microvolt = <1500000>; 760 regulator-always-on; 761 regulator-state-mem { 762 regulator-off-in-suspend; 763 }; 764 }; 765 766 buck7_reg: BUCK7 { 767 regulator-name = "VDD_MEM1_1.2V_AP"; 768 regulator-min-microvolt = <1200000>; 769 regulator-max-microvolt = <1200000>; 770 regulator-always-on; 771 }; 772 773 buck8_reg: BUCK8 { 774 regulator-name = "VDD_LLDO_1.35V_AP"; 775 regulator-min-microvolt = <1350000>; 776 regulator-max-microvolt = <3300000>; 777 regulator-always-on; 778 }; 779 780 buck9_reg: BUCK9 { 781 regulator-name = "VDD_MLDO_2.0V_AP"; 782 regulator-min-microvolt = <1350000>; 783 regulator-max-microvolt = <3300000>; 784 regulator-always-on; 785 }; 786 787 buck10_reg: BUCK10 { 788 regulator-name = "vdd_mem2"; 789 regulator-min-microvolt = <550000>; 790 regulator-max-microvolt = <1500000>; 791 regulator-always-on; 792 }; 793 }; 794 }; 795}; 796 797&hsi2c_4 { 798 status = "okay"; 799 800 s3fwrn5: nfc@27 { 801 compatible = "samsung,s3fwrn5-i2c"; 802 reg = <0x27>; 803 interrupt-parent = <&gpa1>; 804 interrupts = <3 IRQ_TYPE_EDGE_RISING>; 805 en-gpios = <&gpf1 4 GPIO_ACTIVE_LOW>; 806 wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>; 807 }; 808}; 809 810&hsi2c_5 { 811 status = "okay"; 812 813 stmfts: touchscreen@49 { 814 compatible = "st,stmfts"; 815 reg = <0x49>; 816 interrupt-parent = <&gpa1>; 817 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 818 avdd-supply = <&ldo30_reg>; 819 vdd-supply = <&ldo31_reg>; 820 }; 821}; 822 823&hsi2c_7 { 824 status = "okay"; 825 clock-frequency = <1000000>; 826 827 bridge@39 { 828 reg = <0x39>; 829 compatible = "sil,sii8620"; 830 cvcc10-supply = <&ldo36_reg>; 831 iovcc18-supply = <&ldo34_reg>; 832 interrupt-parent = <&gpf0>; 833 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 834 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>; 835 clocks = <&pmu_system_controller 0>; 836 clock-names = "xtal"; 837 838 ports { 839 #address-cells = <1>; 840 #size-cells = <0>; 841 842 port@0 { 843 reg = <0>; 844 mhl_to_hdmi: endpoint { 845 remote-endpoint = <&hdmi_to_mhl>; 846 }; 847 }; 848 849 port@1 { 850 reg = <1>; 851 mhl_to_musb_con: endpoint { 852 remote-endpoint = <&musb_con_to_mhl>; 853 }; 854 }; 855 }; 856 }; 857}; 858 859&hsi2c_8 { 860 status = "okay"; 861 862 pmic@66 { 863 compatible = "maxim,max77843"; 864 interrupt-parent = <&gpa1>; 865 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 866 reg = <0x66>; 867 868 muic: extcon { 869 compatible = "maxim,max77843-muic"; 870 871 musb_con: connector { 872 compatible = "samsung,usb-connector-11pin", 873 "usb-b-connector"; 874 label = "micro-USB"; 875 type = "micro"; 876 877 ports { 878 #address-cells = <1>; 879 #size-cells = <0>; 880 881 port@0 { 882 /* 883 * TODO: The DTS this is based on does not have 884 * port@0 which is a required property. The ports 885 * look incomplete and need fixing. 886 * Add a disabled port just to satisfy dtschema. 887 */ 888 reg = <0>; 889 status = "disabled"; 890 }; 891 892 port@3 { 893 reg = <3>; 894 musb_con_to_mhl: endpoint { 895 remote-endpoint = <&mhl_to_musb_con>; 896 }; 897 }; 898 }; 899 }; 900 901 ports { 902 port { 903 muic_to_usb: endpoint { 904 remote-endpoint = <&usb_to_muic>; 905 }; 906 }; 907 }; 908 }; 909 910 regulators { 911 compatible = "maxim,max77843-regulator"; 912 safeout1_reg: SAFEOUT1 { 913 regulator-name = "SAFEOUT1"; 914 regulator-min-microvolt = <3300000>; 915 regulator-max-microvolt = <4950000>; 916 }; 917 918 safeout2_reg: SAFEOUT2 { 919 regulator-name = "SAFEOUT2"; 920 regulator-min-microvolt = <3300000>; 921 regulator-max-microvolt = <4950000>; 922 }; 923 924 charger_reg: CHARGER { 925 regulator-name = "CHARGER"; 926 regulator-min-microamp = <100000>; 927 regulator-max-microamp = <3150000>; 928 }; 929 }; 930 931 haptic: motor-driver { 932 compatible = "maxim,max77843-haptic"; 933 haptic-supply = <&ldo38_reg>; 934 pwms = <&pwm 0 33670 0>; 935 }; 936 }; 937}; 938 939&hsi2c_11 { 940 status = "okay"; 941}; 942 943&i2s0 { 944 status = "okay"; 945}; 946 947&i2s1 { 948 assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>; 949 assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>; 950 status = "okay"; 951}; 952 953&mshc_0 { 954 status = "okay"; 955 mmc-ddr-1_8v; 956 mmc-hs200-1_8v; 957 mmc-hs400-1_8v; 958 cap-mmc-highspeed; 959 non-removable; 960 card-detect-delay = <200>; 961 samsung,dw-mshc-ciu-div = <3>; 962 samsung,dw-mshc-sdr-timing = <0 4>; 963 samsung,dw-mshc-ddr-timing = <0 2>; 964 samsung,dw-mshc-hs400-timing = <0 3>; 965 samsung,read-strobe-delay = <90>; 966 fifo-depth = <0x80>; 967 pinctrl-names = "default"; 968 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 969 &sd0_bus8 &sd0_rdqs>; 970 bus-width = <8>; 971 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>; 972 assigned-clock-rates = <800000000>; 973}; 974 975&mshc_2 { 976 status = "okay"; 977 cap-sd-highspeed; 978 disable-wp; 979 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; 980 card-detect-delay = <200>; 981 samsung,dw-mshc-ciu-div = <3>; 982 samsung,dw-mshc-sdr-timing = <0 4>; 983 samsung,dw-mshc-ddr-timing = <0 2>; 984 fifo-depth = <0x80>; 985 pinctrl-names = "default"; 986 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; 987 bus-width = <4>; 988}; 989 990&pcie { 991 status = "okay"; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&pcie_bus &pcie_wlanen>; 994 vdd10-supply = <&ldo6_reg>; 995 vdd18-supply = <&ldo7_reg>; 996 assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>, 997 <&cmu_top CLK_MOUT_SCLK_PCIE_100>; 998 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>, 999 <&cmu_top CLK_MOUT_BUS_PLL_USER>; 1000 assigned-clock-rates = <0>, <100000000>; 1001 interrupt-map-mask = <0 0 0 0>; 1002 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1003}; 1004 1005&pcie_phy { 1006 status = "okay"; 1007}; 1008 1009&ppmu_d0_general { 1010 status = "okay"; 1011 events { 1012 ppmu_event0_d0_general: ppmu-event0-d0-general { 1013 event-name = "ppmu-event0-d0-general"; 1014 }; 1015 }; 1016}; 1017 1018&ppmu_d1_general { 1019 status = "okay"; 1020 events { 1021 ppmu_event0_d1_general: ppmu-event0-d1-general { 1022 event-name = "ppmu-event0-d1-general"; 1023 }; 1024 }; 1025}; 1026 1027&pinctrl_alive { 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&initial_alive>; 1030 1031 initial_alive: initial-state { 1032 PIN_IN(gpa0-0, DOWN, FAST_SR1); 1033 PIN_IN(gpa0-1, NONE, FAST_SR1); 1034 PIN_IN(gpa0-2, DOWN, FAST_SR1); 1035 PIN_IN(gpa0-3, NONE, FAST_SR1); 1036 PIN_IN(gpa0-4, NONE, FAST_SR1); 1037 PIN_IN(gpa0-5, DOWN, FAST_SR1); 1038 PIN_IN(gpa0-6, NONE, FAST_SR1); 1039 PIN_IN(gpa0-7, NONE, FAST_SR1); 1040 1041 PIN_IN(gpa1-0, UP, FAST_SR1); 1042 PIN_IN(gpa1-1, UP, FAST_SR1); 1043 PIN_IN(gpa1-2, NONE, FAST_SR1); 1044 PIN_IN(gpa1-3, DOWN, FAST_SR1); 1045 PIN_IN(gpa1-4, DOWN, FAST_SR1); 1046 PIN_IN(gpa1-5, NONE, FAST_SR1); 1047 PIN_IN(gpa1-6, NONE, FAST_SR1); 1048 PIN_IN(gpa1-7, NONE, FAST_SR1); 1049 1050 PIN_IN(gpa2-0, NONE, FAST_SR1); 1051 PIN_IN(gpa2-1, NONE, FAST_SR1); 1052 PIN_IN(gpa2-2, NONE, FAST_SR1); 1053 PIN_IN(gpa2-3, DOWN, FAST_SR1); 1054 PIN_IN(gpa2-4, NONE, FAST_SR1); 1055 PIN_IN(gpa2-5, DOWN, FAST_SR1); 1056 PIN_IN(gpa2-6, DOWN, FAST_SR1); 1057 PIN_IN(gpa2-7, NONE, FAST_SR1); 1058 1059 PIN_IN(gpa3-0, DOWN, FAST_SR1); 1060 PIN_IN(gpa3-1, DOWN, FAST_SR1); 1061 PIN_IN(gpa3-2, NONE, FAST_SR1); 1062 PIN_IN(gpa3-3, DOWN, FAST_SR1); 1063 PIN_IN(gpa3-4, NONE, FAST_SR1); 1064 PIN_IN(gpa3-5, DOWN, FAST_SR1); 1065 PIN_IN(gpa3-6, DOWN, FAST_SR1); 1066 PIN_IN(gpa3-7, DOWN, FAST_SR1); 1067 1068 PIN_IN(gpf1-0, NONE, FAST_SR1); 1069 PIN_IN(gpf1-1, NONE, FAST_SR1); 1070 PIN_IN(gpf1-2, DOWN, FAST_SR1); 1071 PIN_IN(gpf1-4, UP, FAST_SR1); 1072 PIN_OT(gpf1-5, NONE, FAST_SR1); 1073 PIN_IN(gpf1-6, DOWN, FAST_SR1); 1074 PIN_IN(gpf1-7, DOWN, FAST_SR1); 1075 1076 PIN_IN(gpf2-0, DOWN, FAST_SR1); 1077 PIN_IN(gpf2-1, DOWN, FAST_SR1); 1078 PIN_IN(gpf2-2, DOWN, FAST_SR1); 1079 PIN_IN(gpf2-3, DOWN, FAST_SR1); 1080 1081 PIN_IN(gpf3-0, DOWN, FAST_SR1); 1082 PIN_IN(gpf3-1, DOWN, FAST_SR1); 1083 PIN_IN(gpf3-2, NONE, FAST_SR1); 1084 PIN_IN(gpf3-3, DOWN, FAST_SR1); 1085 1086 PIN_IN(gpf4-0, DOWN, FAST_SR1); 1087 PIN_IN(gpf4-1, DOWN, FAST_SR1); 1088 PIN_IN(gpf4-2, DOWN, FAST_SR1); 1089 PIN_IN(gpf4-3, DOWN, FAST_SR1); 1090 PIN_IN(gpf4-4, DOWN, FAST_SR1); 1091 PIN_IN(gpf4-5, DOWN, FAST_SR1); 1092 PIN_IN(gpf4-6, DOWN, FAST_SR1); 1093 PIN_IN(gpf4-7, DOWN, FAST_SR1); 1094 1095 PIN_IN(gpf5-0, DOWN, FAST_SR1); 1096 PIN_IN(gpf5-1, DOWN, FAST_SR1); 1097 PIN_IN(gpf5-2, DOWN, FAST_SR1); 1098 PIN_IN(gpf5-3, DOWN, FAST_SR1); 1099 PIN_OT(gpf5-4, NONE, FAST_SR1); 1100 PIN_IN(gpf5-5, DOWN, FAST_SR1); 1101 PIN_IN(gpf5-6, DOWN, FAST_SR1); 1102 PIN_IN(gpf5-7, DOWN, FAST_SR1); 1103 }; 1104 1105 te_irq: te-irq-pins { 1106 samsung,pins = "gpf1-3"; 1107 samsung,pin-function = <0xf>; 1108 }; 1109}; 1110 1111&pinctrl_cpif { 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&initial_cpif>; 1114 1115 initial_cpif: initial-state { 1116 PIN_IN(gpv6-0, DOWN, FAST_SR1); 1117 PIN_IN(gpv6-1, DOWN, FAST_SR1); 1118 }; 1119}; 1120 1121&pinctrl_ese { 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&initial_ese>; 1124 1125 pcie_wlanen: pcie-wlanen-pins { 1126 samsung,pins = "gpj2-0"; 1127 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 1128 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 1129 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>; 1130 }; 1131 1132 initial_ese: initial-state { 1133 PIN_IN(gpj2-1, DOWN, FAST_SR1); 1134 PIN_IN(gpj2-2, DOWN, FAST_SR1); 1135 }; 1136}; 1137 1138&pinctrl_fsys { 1139 pinctrl-names = "default"; 1140 pinctrl-0 = <&initial_fsys>; 1141 1142 initial_fsys: initial-state { 1143 PIN_IN(gpr3-0, NONE, FAST_SR1); 1144 PIN_IN(gpr3-1, DOWN, FAST_SR1); 1145 PIN_IN(gpr3-2, DOWN, FAST_SR1); 1146 PIN_IN(gpr3-3, DOWN, FAST_SR1); 1147 PIN_IN(gpr3-7, NONE, FAST_SR1); 1148 }; 1149}; 1150 1151&pinctrl_imem { 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&initial_imem>; 1154 1155 initial_imem: initial-state { 1156 PIN_IN(gpf0-0, UP, FAST_SR1); 1157 PIN_IN(gpf0-1, UP, FAST_SR1); 1158 PIN_IN(gpf0-2, DOWN, FAST_SR1); 1159 PIN_IN(gpf0-3, UP, FAST_SR1); 1160 PIN_IN(gpf0-4, DOWN, FAST_SR1); 1161 PIN_IN(gpf0-5, NONE, FAST_SR1); 1162 PIN_IN(gpf0-6, DOWN, FAST_SR1); 1163 PIN_IN(gpf0-7, UP, FAST_SR1); 1164 }; 1165}; 1166 1167&pinctrl_nfc { 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&initial_nfc>; 1170 1171 initial_nfc: initial-state { 1172 PIN_IN(gpj0-2, DOWN, FAST_SR1); 1173 }; 1174}; 1175 1176&pinctrl_peric { 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&initial_peric>; 1179 1180 initial_peric: initial-state { 1181 PIN_IN(gpv7-0, DOWN, FAST_SR1); 1182 PIN_IN(gpv7-1, DOWN, FAST_SR1); 1183 PIN_IN(gpv7-2, NONE, FAST_SR1); 1184 PIN_IN(gpv7-3, DOWN, FAST_SR1); 1185 PIN_IN(gpv7-4, DOWN, FAST_SR1); 1186 PIN_IN(gpv7-5, DOWN, FAST_SR1); 1187 1188 PIN_IN(gpb0-4, DOWN, FAST_SR1); 1189 1190 PIN_IN(gpc0-2, DOWN, FAST_SR1); 1191 PIN_IN(gpc0-5, DOWN, FAST_SR1); 1192 PIN_IN(gpc0-7, DOWN, FAST_SR1); 1193 1194 PIN_IN(gpc1-1, DOWN, FAST_SR1); 1195 1196 PIN_IN(gpc3-4, NONE, FAST_SR1); 1197 PIN_IN(gpc3-5, NONE, FAST_SR1); 1198 PIN_IN(gpc3-6, NONE, FAST_SR1); 1199 PIN_IN(gpc3-7, NONE, FAST_SR1); 1200 1201 PIN_OT(gpg0-0, NONE, FAST_SR1); 1202 PIN_F2(gpg0-1, DOWN, FAST_SR1); 1203 1204 PIN_IN(gpd2-5, DOWN, FAST_SR1); 1205 1206 PIN_IN(gpd4-0, NONE, FAST_SR1); 1207 PIN_IN(gpd4-1, DOWN, FAST_SR1); 1208 PIN_IN(gpd4-2, DOWN, FAST_SR1); 1209 PIN_IN(gpd4-3, DOWN, FAST_SR1); 1210 PIN_IN(gpd4-4, DOWN, FAST_SR1); 1211 1212 PIN_IN(gpd6-3, DOWN, FAST_SR1); 1213 1214 PIN_IN(gpd8-1, UP, FAST_SR1); 1215 1216 PIN_IN(gpg1-0, DOWN, FAST_SR1); 1217 PIN_IN(gpg1-1, DOWN, FAST_SR1); 1218 PIN_IN(gpg1-2, DOWN, FAST_SR1); 1219 PIN_IN(gpg1-3, DOWN, FAST_SR1); 1220 PIN_IN(gpg1-4, DOWN, FAST_SR1); 1221 1222 PIN_IN(gpg2-0, DOWN, FAST_SR1); 1223 PIN_IN(gpg2-1, DOWN, FAST_SR1); 1224 1225 PIN_IN(gpg3-0, DOWN, FAST_SR1); 1226 PIN_IN(gpg3-1, DOWN, FAST_SR1); 1227 PIN_IN(gpg3-5, DOWN, FAST_SR1); 1228 }; 1229}; 1230 1231&pinctrl_touch { 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&initial_touch>; 1234 1235 initial_touch: initial-state { 1236 PIN_IN(gpj1-2, DOWN, FAST_SR1); 1237 }; 1238}; 1239 1240&pwm { 1241 pinctrl-0 = <&pwm0_out>; 1242 pinctrl-names = "default"; 1243 status = "okay"; 1244}; 1245 1246&mic { 1247 status = "okay"; 1248}; 1249 1250&pmu_system_controller { 1251 assigned-clocks = <&pmu_system_controller 0>; 1252 assigned-clock-parents = <&xxti>; 1253}; 1254 1255&serial_1 { 1256 status = "okay"; 1257}; 1258 1259&serial_3 { 1260 status = "okay"; 1261 1262 bluetooth { 1263 compatible = "brcm,bcm43438-bt"; 1264 max-speed = <3000000>; 1265 shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>; 1266 device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>; 1267 host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>; 1268 clocks = <&s2mps13_osc S2MPS11_CLK_BT>; 1269 clock-names = "extclk"; 1270 }; 1271}; 1272 1273&spi_1 { 1274 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; 1275 status = "okay"; 1276 1277 wm5110: audio-codec@0 { 1278 compatible = "wlf,wm5110"; 1279 reg = <0x0>; 1280 spi-max-frequency = <20000000>; 1281 interrupt-parent = <&gpa0>; 1282 interrupts = <4 IRQ_TYPE_NONE>; 1283 clocks = <&pmu_system_controller 0>, 1284 <&s2mps13_osc S2MPS11_CLK_BT>; 1285 clock-names = "mclk1", "mclk2"; 1286 1287 gpio-controller; 1288 #gpio-cells = <2>; 1289 interrupt-controller; 1290 #interrupt-cells = <2>; 1291 1292 wlf,micd-detect-debounce = <300>; 1293 wlf,micd-bias-start-time = <0x1>; 1294 wlf,micd-rate = <0x7>; 1295 wlf,micd-dbtime = <0x2>; 1296 wlf,micd-force-micbias; 1297 wlf,micd-configs = <0x0 1 0>; 1298 wlf,hpdet-channel = <1>; 1299 wlf,gpsw = <0x1>; 1300 wlf,inmode = <2 0 2 0>; 1301 1302 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>; 1303 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>; 1304 1305 /* core supplies */ 1306 AVDD-supply = <&ldo18_reg>; 1307 DBVDD1-supply = <&ldo18_reg>; 1308 CPVDD-supply = <&ldo18_reg>; 1309 DBVDD2-supply = <&ldo18_reg>; 1310 DBVDD3-supply = <&ldo18_reg>; 1311 SPKVDDL-supply = <&vph_pwr_regulator>; 1312 SPKVDDR-supply = <&vph_pwr_regulator>; 1313 1314 controller-data { 1315 samsung,spi-feedback-delay = <0>; 1316 }; 1317 }; 1318}; 1319 1320&spi_3 { 1321 status = "okay"; 1322 no-cs-readback; 1323 1324 irled@0 { 1325 compatible = "ir-spi-led"; 1326 reg = <0x0>; 1327 spi-max-frequency = <5000000>; 1328 power-supply = <&irda_regulator>; 1329 duty-cycle = /bits/ 8 <60>; 1330 led-active-low; 1331 1332 controller-data { 1333 samsung,spi-feedback-delay = <0>; 1334 }; 1335 }; 1336}; 1337 1338&timer { 1339 clock-frequency = <24000000>; 1340}; 1341 1342&tmu_atlas0 { 1343 vtmu-supply = <&ldo3_reg>; 1344 status = "okay"; 1345}; 1346 1347&tmu_apollo { 1348 vtmu-supply = <&ldo3_reg>; 1349 status = "okay"; 1350}; 1351 1352&tmu_g3d { 1353 vtmu-supply = <&ldo3_reg>; 1354 status = "okay"; 1355}; 1356 1357&usbdrd30 { 1358 vdd33-supply = <&ldo10_reg>; 1359 vdd10-supply = <&ldo6_reg>; 1360 status = "okay"; 1361}; 1362 1363&usbdrd_dwc3 { 1364 dr_mode = "otg"; 1365}; 1366 1367&usbdrd30_phy { 1368 vbus-supply = <&safeout1_reg>; 1369 status = "okay"; 1370 1371 port { 1372 usb_to_muic: endpoint { 1373 remote-endpoint = <&muic_to_usb>; 1374 }; 1375 }; 1376}; 1377 1378&xxti { 1379 clock-frequency = <24000000>; 1380}; 1381