1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/clock/bcm-sr.h> 34 35 osc: oscillator { 36 #clock-cells = <0>; 37 compatible = "fixed-clock"; 38 clock-frequency = <50000000>; 39 }; 40 41 crmu_ref25m: crmu_ref25m { 42 #clock-cells = <0>; 43 compatible = "fixed-factor-clock"; 44 clocks = <&osc>; 45 clock-div = <2>; 46 clock-mult = <1>; 47 }; 48 49 genpll0: genpll0@1d104 { 50 #clock-cells = <1>; 51 compatible = "brcm,sr-genpll0"; 52 reg = <0x0001d104 0x32>, 53 <0x0001c854 0x4>; 54 clocks = <&osc>; 55 clock-output-names = "genpll0", "clk_125", "clk_scr", 56 "clk_250", "clk_pcie_axi", 57 "clk_paxc_axi_x2", 58 "clk_paxc_axi"; 59 }; 60 61 genpll3: genpll3@1d1e0 { 62 #clock-cells = <1>; 63 compatible = "brcm,sr-genpll3"; 64 reg = <0x0001d1e0 0x32>, 65 <0x0001c854 0x4>; 66 clocks = <&osc>; 67 clock-output-names = "genpll3", "clk_hsls", 68 "clk_sdio"; 69 }; 70 71 genpll4: genpll4@1d214 { 72 #clock-cells = <1>; 73 compatible = "brcm,sr-genpll4"; 74 reg = <0x0001d214 0x32>, 75 <0x0001c854 0x4>; 76 clocks = <&osc>; 77 clock-output-names = "genpll4", "clk_ccn", 78 "clk_tpiu_pll", "noc_clk", 79 "pll_chclk_fs4", 80 "clk_bridge_fscpu"; 81 }; 82 83 genpll5: genpll5@1d248 { 84 #clock-cells = <1>; 85 compatible = "brcm,sr-genpll5"; 86 reg = <0x0001d248 0x32>, 87 <0x0001c870 0x4>; 88 clocks = <&osc>; 89 clock-output-names = "genpll5", "fs4_hf_clk", 90 "crypto_ae_clk", "raid_ae_clk"; 91 }; 92 93 lcpll0: lcpll0@1d0c4 { 94 #clock-cells = <1>; 95 compatible = "brcm,sr-lcpll0"; 96 reg = <0x0001d0c4 0x3c>, 97 <0x0001c870 0x4>; 98 clocks = <&osc>; 99 clock-output-names = "lcpll0", "clk_sata_refp", 100 "clk_sata_refn", "clk_sata_350", 101 "clk_sata_500"; 102 }; 103 104 lcpll1: lcpll1@1d138 { 105 #clock-cells = <1>; 106 compatible = "brcm,sr-lcpll1"; 107 reg = <0x0001d138 0x3c>, 108 <0x0001c870 0x4>; 109 clocks = <&osc>; 110 clock-output-names = "lcpll1", "clk_wanpn", 111 "clk_usb_ref", 112 "timesync_evt_clk"; 113 }; 114 115 hsls_clk: hsls_clk { 116 #clock-cells = <0>; 117 compatible = "fixed-factor-clock"; 118 clocks = <&genpll3 1>; 119 clock-div = <1>; 120 clock-mult = <1>; 121 }; 122 123 hsls_div2_clk: hsls_div2_clk { 124 #clock-cells = <0>; 125 compatible = "fixed-factor-clock"; 126 clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; 127 clock-div = <2>; 128 clock-mult = <1>; 129 130 }; 131 132 hsls_div4_clk: hsls_div4_clk { 133 #clock-cells = <0>; 134 compatible = "fixed-factor-clock"; 135 clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; 136 clock-div = <4>; 137 clock-mult = <1>; 138 }; 139 140 hsls_25m_clk: hsls_25m_clk { 141 #clock-cells = <0>; 142 compatible = "fixed-factor-clock"; 143 clocks = <&crmu_ref25m>; 144 clock-div = <1>; 145 clock-mult = <1>; 146 }; 147 148 hsls_25m_div2_clk: hsls_25m_div2_clk { 149 #clock-cells = <0>; 150 compatible = "fixed-factor-clock"; 151 clocks = <&hsls_25m_clk>; 152 clock-div = <2>; 153 clock-mult = <1>; 154 }; 155 156 sdio0_clk: sdio0_clk { 157 #clock-cells = <0>; 158 compatible = "fixed-factor-clock"; 159 clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; 160 clock-div = <1>; 161 clock-mult = <1>; 162 }; 163 164 sdio1_clk: sdio1_clk { 165 #clock-cells = <0>; 166 compatible = "fixed-factor-clock"; 167 clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; 168 clock-div = <1>; 169 clock-mult = <1>; 170 }; 171