1/*
2 *  BSD LICENSE
3 *
4 *  Copyright (c) 2015 Broadcom.  All rights reserved.
5 *
6 *  Redistribution and use in source and binary forms, with or without
7 *  modification, are permitted provided that the following conditions
8 *  are met:
9 *
10 *    * Redistributions of source code must retain the above copyright
11 *      notice, this list of conditions and the following disclaimer.
12 *    * Redistributions in binary form must reproduce the above copyright
13 *      notice, this list of conditions and the following disclaimer in
14 *      the documentation and/or other materials provided with the
15 *      distribution.
16 *    * Neither the name of Broadcom Corporation nor the names of its
17 *      contributors may be used to endorse or promote products derived
18 *      from this software without specific prior written permission.
19 *
20 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/memreserve/ 0x81000000 0x00200000;
34
35#include <dt-bindings/interrupt-controller/arm-gic.h>
36#include <dt-bindings/clock/bcm-ns2.h>
37
38/ {
39	compatible = "brcm,ns2";
40	interrupt-parent = <&gic>;
41	#address-cells = <2>;
42	#size-cells = <2>;
43
44	cpus {
45		#address-cells = <2>;
46		#size-cells = <0>;
47
48		A57_0: cpu@0 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a57";
51			reg = <0 0>;
52			enable-method = "psci";
53			next-level-cache = <&CLUSTER0_L2>;
54		};
55
56		A57_1: cpu@1 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a57";
59			reg = <0 1>;
60			enable-method = "psci";
61			next-level-cache = <&CLUSTER0_L2>;
62		};
63
64		A57_2: cpu@2 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a57";
67			reg = <0 2>;
68			enable-method = "psci";
69			next-level-cache = <&CLUSTER0_L2>;
70		};
71
72		A57_3: cpu@3 {
73			device_type = "cpu";
74			compatible = "arm,cortex-a57";
75			reg = <0 3>;
76			enable-method = "psci";
77			next-level-cache = <&CLUSTER0_L2>;
78		};
79
80		CLUSTER0_L2: l2-cache@0 {
81			compatible = "cache";
82			cache-level = <2>;
83		};
84	};
85
86	psci {
87		compatible = "arm,psci-1.0";
88		method = "smc";
89	};
90
91	timer {
92		compatible = "arm,armv8-timer";
93		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
94			      IRQ_TYPE_LEVEL_LOW)>,
95			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
96			      IRQ_TYPE_LEVEL_LOW)>,
97			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
98			      IRQ_TYPE_LEVEL_LOW)>,
99			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
100			      IRQ_TYPE_LEVEL_LOW)>;
101	};
102
103	pmu {
104		compatible = "arm,armv8-pmuv3";
105		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
106			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
107			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
108			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
109		interrupt-affinity = <&A57_0>,
110				     <&A57_1>,
111				     <&A57_2>,
112				     <&A57_3>;
113	};
114
115	pcie0: pcie@20020000 {
116		compatible = "brcm,iproc-pcie";
117		reg = <0 0x20020000 0 0x1000>;
118		dma-coherent;
119
120		#interrupt-cells = <1>;
121		interrupt-map-mask = <0 0 0 0>;
122		interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
123
124		linux,pci-domain = <0>;
125
126		bus-range = <0x00 0xff>;
127
128		#address-cells = <3>;
129		#size-cells = <2>;
130		device_type = "pci";
131		ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
132
133		brcm,pcie-ob;
134		brcm,pcie-ob-oarr-size;
135		brcm,pcie-ob-axi-offset = <0x00000000>;
136		brcm,pcie-ob-window-size = <256>;
137
138		status = "disabled";
139
140		phys = <&pci_phy0>;
141		phy-names = "pcie-phy";
142
143		msi-parent = <&v2m0>;
144	};
145
146	pcie4: pcie@50020000 {
147		compatible = "brcm,iproc-pcie";
148		reg = <0 0x50020000 0 0x1000>;
149		dma-coherent;
150
151		#interrupt-cells = <1>;
152		interrupt-map-mask = <0 0 0 0>;
153		interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
154
155		linux,pci-domain = <4>;
156
157		bus-range = <0x00 0xff>;
158
159		#address-cells = <3>;
160		#size-cells = <2>;
161		device_type = "pci";
162		ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
163
164		brcm,pcie-ob;
165		brcm,pcie-ob-oarr-size;
166		brcm,pcie-ob-axi-offset = <0x30000000>;
167		brcm,pcie-ob-window-size = <256>;
168
169		status = "disabled";
170
171		phys = <&pci_phy1>;
172		phy-names = "pcie-phy";
173
174		msi-parent = <&v2m0>;
175	};
176
177	pcie8: pcie@60c00000 {
178		compatible = "brcm,iproc-pcie-paxc";
179		reg = <0 0x60c00000 0 0x1000>;
180		dma-coherent;
181		linux,pci-domain = <8>;
182
183		bus-range = <0x0 0x1>;
184
185		#address-cells = <3>;
186		#size-cells = <2>;
187		device_type = "pci";
188		ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
189
190		status = "disabled";
191
192		msi-parent = <&v2m0>;
193	};
194
195	soc: soc {
196		compatible = "simple-bus";
197		#address-cells = <1>;
198		#size-cells = <1>;
199		ranges = <0 0 0 0xffffffff>;
200
201		#include "ns2-clock.dtsi"
202
203		enet: ethernet@61000000 {
204			compatible = "brcm,ns2-amac";
205			reg = <0x61000000 0x1000>,
206			      <0x61090000 0x1000>,
207			      <0x61030000 0x100>;
208			reg-names = "amac_base", "idm_base", "nicpm_base";
209			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
210			dma-coherent;
211			phy-handle = <&gphy0>;
212			phy-mode = "rgmii";
213			status = "disabled";
214		};
215
216		pdc0: iproc-pdc0@612c0000 {
217			compatible = "brcm,iproc-pdc-mbox";
218			reg = <0x612c0000 0x445>;  /* PDC FS0 regs */
219			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
220			#mbox-cells = <1>;
221			dma-coherent;
222			brcm,rx-status-len = <32>;
223			brcm,use-bcm-hdr;
224		};
225
226		crypto0: crypto@612d0000 {
227			compatible = "brcm,spum-crypto";
228			reg = <0x612d0000 0x900>;
229			mboxes = <&pdc0 0>;
230		};
231
232		pdc1: iproc-pdc1@612e0000 {
233			compatible = "brcm,iproc-pdc-mbox";
234			reg = <0x612e0000 0x445>;  /* PDC FS1 regs */
235			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
236			#mbox-cells = <1>;
237			dma-coherent;
238			brcm,rx-status-len = <32>;
239			brcm,use-bcm-hdr;
240		};
241
242		crypto1: crypto@612f0000 {
243			compatible = "brcm,spum-crypto";
244			reg = <0x612f0000 0x900>;
245			mboxes = <&pdc1 0>;
246		};
247
248		pdc2: iproc-pdc2@61300000 {
249			compatible = "brcm,iproc-pdc-mbox";
250			reg = <0x61300000 0x445>;  /* PDC FS2 regs */
251			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
252			#mbox-cells = <1>;
253			dma-coherent;
254			brcm,rx-status-len = <32>;
255			brcm,use-bcm-hdr;
256		};
257
258		crypto2: crypto@61310000 {
259			compatible = "brcm,spum-crypto";
260			reg = <0x61310000 0x900>;
261			mboxes = <&pdc2 0>;
262		};
263
264		pdc3: iproc-pdc3@61320000 {
265			compatible = "brcm,iproc-pdc-mbox";
266			reg = <0x61320000 0x445>;  /* PDC FS3 regs */
267			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
268			#mbox-cells = <1>;
269			dma-coherent;
270			brcm,rx-status-len = <32>;
271			brcm,use-bcm-hdr;
272		};
273
274		crypto3: crypto@61330000 {
275			compatible = "brcm,spum-crypto";
276			reg = <0x61330000 0x900>;
277			mboxes = <&pdc3 0>;
278		};
279
280		dma0: dma-controller@61360000 {
281			compatible = "arm,pl330", "arm,primecell";
282			reg = <0x61360000 0x1000>;
283			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
284				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
285				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
286				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
287				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
288				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
289				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
290				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
291				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
292			#dma-cells = <1>;
293			clocks = <&iprocslow>;
294			clock-names = "apb_pclk";
295		};
296
297		smmu: mmu@64000000 {
298			compatible = "arm,mmu-500";
299			reg = <0x64000000 0x40000>;
300			#global-interrupts = <2>;
301			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
302				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
303				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
304				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
305				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
306				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
307				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
308				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
309				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
310				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
311				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
312				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
313				     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
314				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
315				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
316				     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
317				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
318				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
319				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
320				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
321				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
322				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
323				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
324				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
325				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
326				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
327				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
328				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
329				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
330				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
331				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
332				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
333				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
334				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
335			#iommu-cells = <1>;
336		};
337
338		pinctrl: pinctrl@6501d130 {
339			compatible = "brcm,ns2-pinmux";
340			reg = <0x6501d130 0x08>,
341			      <0x660a0028 0x04>,
342			      <0x660009b0 0x40>;
343		};
344
345		gpio_aon: gpio@65024800 {
346			compatible = "brcm,iproc-gpio";
347			reg = <0x65024800 0x50>,
348			      <0x65024008 0x18>;
349			ngpios = <6>;
350			#gpio-cells = <2>;
351			gpio-controller;
352		};
353
354		gic: interrupt-controller@65210000 {
355			compatible = "arm,gic-400";
356			#interrupt-cells = <3>;
357			interrupt-controller;
358			reg = <0x65210000 0x1000>,
359			      <0x65220000 0x1000>,
360			      <0x65240000 0x2000>,
361			      <0x65260000 0x1000>;
362			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
363				      IRQ_TYPE_LEVEL_HIGH)>;
364
365			#address-cells = <1>;
366			#size-cells = <1>;
367			ranges = <0 0x652e0000 0x80000>;
368
369			v2m0: v2m@0 {
370				compatible = "arm,gic-v2m-frame";
371				interrupt-parent = <&gic>;
372				msi-controller;
373				reg = <0x00000 0x1000>;
374				arm,msi-base-spi = <72>;
375				arm,msi-num-spis = <16>;
376			};
377
378			v2m1: v2m@10000 {
379				compatible = "arm,gic-v2m-frame";
380				interrupt-parent = <&gic>;
381				msi-controller;
382				reg = <0x10000 0x1000>;
383				arm,msi-base-spi = <88>;
384				arm,msi-num-spis = <16>;
385			};
386
387			v2m2: v2m@20000 {
388				compatible = "arm,gic-v2m-frame";
389				interrupt-parent = <&gic>;
390				msi-controller;
391				reg = <0x20000 0x1000>;
392				arm,msi-base-spi = <104>;
393				arm,msi-num-spis = <16>;
394			};
395
396			v2m3: v2m@30000 {
397				compatible = "arm,gic-v2m-frame";
398				interrupt-parent = <&gic>;
399				msi-controller;
400				reg = <0x30000 0x1000>;
401				arm,msi-base-spi = <120>;
402				arm,msi-num-spis = <16>;
403			};
404
405			v2m4: v2m@40000 {
406				compatible = "arm,gic-v2m-frame";
407				interrupt-parent = <&gic>;
408				msi-controller;
409				reg = <0x40000 0x1000>;
410				arm,msi-base-spi = <136>;
411				arm,msi-num-spis = <16>;
412			};
413
414			v2m5: v2m@50000 {
415				compatible = "arm,gic-v2m-frame";
416				interrupt-parent = <&gic>;
417				msi-controller;
418				reg = <0x50000 0x1000>;
419				arm,msi-base-spi = <152>;
420				arm,msi-num-spis = <16>;
421			};
422
423			v2m6: v2m@60000 {
424				compatible = "arm,gic-v2m-frame";
425				interrupt-parent = <&gic>;
426				msi-controller;
427				reg = <0x60000 0x1000>;
428				arm,msi-base-spi = <168>;
429				arm,msi-num-spis = <16>;
430			};
431
432			v2m7: v2m@70000 {
433				compatible = "arm,gic-v2m-frame";
434				interrupt-parent = <&gic>;
435				msi-controller;
436				reg = <0x70000 0x1000>;
437				arm,msi-base-spi = <184>;
438				arm,msi-num-spis = <16>;
439			};
440		};
441
442		cci@65590000 {
443			compatible = "arm,cci-400";
444			#address-cells = <1>;
445			#size-cells = <1>;
446			reg = <0x65590000 0x1000>;
447			ranges = <0 0x65590000 0x10000>;
448
449			pmu@9000 {
450				compatible = "arm,cci-400-pmu,r1",
451					     "arm,cci-400-pmu";
452				reg = <0x9000 0x4000>;
453				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
454					     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
455					     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
456					     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
457					     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
458					     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
459			};
460		};
461
462		usbdrd_phy: phy@66000960 {
463			#phy-cells = <0>;
464			compatible = "brcm,ns2-drd-phy";
465			reg = <0x66000960 0x24>,
466			      <0x67012800 0x4>,
467			      <0x6501d148 0x4>,
468			      <0x664d0700 0x4>;
469			reg-names = "icfg", "rst-ctrl",
470				    "crmu-ctrl", "usb2-strap";
471			id-gpios = <&gpio_g 30 0>;
472			vbus-gpios = <&gpio_g 31 0>;
473			status = "disabled";
474		};
475
476		pwm: pwm@66010000 {
477			compatible = "brcm,iproc-pwm";
478			reg = <0x66010000 0x28>;
479			clocks = <&osc>;
480			#pwm-cells = <3>;
481			status = "disabled";
482		};
483
484		mdio_mux_iproc: mdio-mux@66020000 {
485			compatible = "brcm,mdio-mux-iproc";
486			reg = <0x66020000 0x250>;
487			#address-cells = <1>;
488			#size-cells = <0>;
489
490			mdio@0 {
491				reg = <0x0>;
492				#address-cells = <1>;
493				#size-cells = <0>;
494
495				pci_phy0: pci-phy@0 {
496					compatible = "brcm,ns2-pcie-phy";
497					reg = <0x0>;
498					#phy-cells = <0>;
499					status = "disabled";
500				};
501			};
502
503			mdio@7 {
504				reg = <0x7>;
505				#address-cells = <1>;
506				#size-cells = <0>;
507
508				pci_phy1: pci-phy@0 {
509					compatible = "brcm,ns2-pcie-phy";
510					reg = <0x0>;
511					#phy-cells = <0>;
512					status = "disabled";
513				};
514			};
515
516			mdio@10 {
517				reg = <0x10>;
518				#address-cells = <1>;
519				#size-cells = <0>;
520			};
521		};
522
523		timer0: timer@66030000 {
524			compatible = "arm,sp804", "arm,primecell";
525			reg = <0x66030000 0x1000>;
526			interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
527			clocks = <&iprocslow>,
528				 <&iprocslow>,
529				 <&iprocslow>;
530			clock-names = "timer1", "timer2", "apb_pclk";
531		};
532
533		timer1: timer@66040000 {
534			compatible = "arm,sp804", "arm,primecell";
535			reg = <0x66040000 0x1000>;
536			interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
537			clocks = <&iprocslow>,
538				 <&iprocslow>,
539				 <&iprocslow>;
540			clock-names = "timer1", "timer2", "apb_pclk";
541		};
542
543		timer2: timer@66050000 {
544			compatible = "arm,sp804", "arm,primecell";
545			reg = <0x66050000 0x1000>;
546			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
547			clocks = <&iprocslow>,
548				 <&iprocslow>,
549				 <&iprocslow>;
550			clock-names = "timer1", "timer2", "apb_pclk";
551		};
552
553		timer3: timer@66060000 {
554			compatible = "arm,sp804", "arm,primecell";
555			reg = <0x66060000 0x1000>;
556			interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
557			clocks = <&iprocslow>,
558				 <&iprocslow>,
559				 <&iprocslow>;
560			clock-names = "timer1", "timer2", "apb_pclk";
561		};
562
563		i2c0: i2c@66080000 {
564			compatible = "brcm,iproc-i2c";
565			reg = <0x66080000 0x100>;
566			#address-cells = <1>;
567			#size-cells = <0>;
568			interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
569			clock-frequency = <100000>;
570			status = "disabled";
571		};
572
573		wdt0: watchdog@66090000 {
574			compatible = "arm,sp805", "arm,primecell";
575			reg = <0x66090000 0x1000>;
576			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
577			clocks = <&iprocslow>, <&iprocslow>;
578			clock-names = "wdog_clk", "apb_pclk";
579		};
580
581		gpio_g: gpio@660a0000 {
582			compatible = "brcm,iproc-gpio";
583			reg = <0x660a0000 0x50>;
584			ngpios = <32>;
585			#gpio-cells = <2>;
586			gpio-controller;
587			interrupt-controller;
588			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
589		};
590
591		i2c1: i2c@660b0000 {
592			compatible = "brcm,iproc-i2c";
593			reg = <0x660b0000 0x100>;
594			#address-cells = <1>;
595			#size-cells = <0>;
596			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
597			clock-frequency = <100000>;
598			status = "disabled";
599		};
600
601		uart0: serial@66100000 {
602			compatible = "snps,dw-apb-uart";
603			reg = <0x66100000 0x100>;
604			interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
605			clocks = <&iprocslow>;
606			reg-shift = <2>;
607			reg-io-width = <4>;
608			status = "disabled";
609		};
610
611		uart1: serial@66110000 {
612			compatible = "snps,dw-apb-uart";
613			reg = <0x66110000 0x100>;
614			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
615			clocks = <&iprocslow>;
616			reg-shift = <2>;
617			reg-io-width = <4>;
618			status = "disabled";
619		};
620
621		uart2: serial@66120000 {
622			compatible = "snps,dw-apb-uart";
623			reg = <0x66120000 0x100>;
624			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
625			clocks = <&iprocslow>;
626			reg-shift = <2>;
627			reg-io-width = <4>;
628			status = "disabled";
629		};
630
631		uart3: serial@66130000 {
632			compatible = "snps,dw-apb-uart";
633			reg = <0x66130000 0x100>;
634			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
635			reg-shift = <2>;
636			reg-io-width = <4>;
637			clocks = <&osc>;
638			status = "disabled";
639		};
640
641		ssp0: spi@66180000 {
642			compatible = "arm,pl022", "arm,primecell";
643			reg = <0x66180000 0x1000>;
644			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
645			clocks = <&iprocslow>, <&iprocslow>;
646			clock-names = "sspclk", "apb_pclk";
647			#address-cells = <1>;
648			#size-cells = <0>;
649			status = "disabled";
650		};
651
652		ssp1: spi@66190000 {
653			compatible = "arm,pl022", "arm,primecell";
654			reg = <0x66190000 0x1000>;
655			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
656			clocks = <&iprocslow>, <&iprocslow>;
657			clock-names = "sspclk", "apb_pclk";
658			#address-cells = <1>;
659			#size-cells = <0>;
660			status = "disabled";
661		};
662
663		hwrng: hwrng@66220000 {
664			compatible = "brcm,iproc-rng200";
665			reg = <0x66220000 0x28>;
666		};
667
668		sata_phy: sata_phy@663f0100 {
669			compatible = "brcm,iproc-ns2-sata-phy";
670			reg = <0x663f0100 0x1f00>,
671			      <0x663f004c 0x10>;
672			reg-names = "phy", "phy-ctrl";
673			#address-cells = <1>;
674			#size-cells = <0>;
675
676			sata_phy0: sata-phy@0 {
677				reg = <0>;
678				#phy-cells = <0>;
679				status = "disabled";
680			};
681
682			sata_phy1: sata-phy@1 {
683				reg = <1>;
684				#phy-cells = <0>;
685				status = "disabled";
686			};
687		};
688
689		sata: sata@663f2000 {
690			compatible = "brcm,iproc-ahci", "generic-ahci";
691			reg = <0x663f2000 0x1000>;
692			dma-coherent;
693			reg-names = "ahci";
694			interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
695			#address-cells = <1>;
696			#size-cells = <0>;
697			status = "disabled";
698
699			sata0: sata-port@0 {
700				reg = <0>;
701				phys = <&sata_phy0>;
702				phy-names = "sata-phy";
703			};
704
705			sata1: sata-port@1 {
706				reg = <1>;
707				phys = <&sata_phy1>;
708				phy-names = "sata-phy";
709			};
710		};
711
712		sdio0: sdhci@66420000 {
713			compatible = "brcm,sdhci-iproc-cygnus";
714			reg = <0x66420000 0x100>;
715			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
716			dma-coherent;
717			bus-width = <8>;
718			clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
719			status = "disabled";
720		};
721
722		sdio1: sdhci@66430000 {
723			compatible = "brcm,sdhci-iproc-cygnus";
724			reg = <0x66430000 0x100>;
725			interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
726			dma-coherent;
727			bus-width = <8>;
728			clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
729			status = "disabled";
730		};
731
732		nand: nand@66460000 {
733			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
734			reg = <0x66460000 0x600>,
735			      <0x67015408 0x600>,
736			      <0x66460f00 0x20>;
737			reg-names = "nand", "iproc-idm", "iproc-ext";
738			interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
739
740			#address-cells = <1>;
741			#size-cells = <0>;
742
743			brcm,nand-has-wp;
744		};
745
746		qspi: spi@66470200 {
747			compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
748			reg = <0x66470200 0x184>,
749				<0x66470000 0x124>,
750				<0x67017408 0x004>,
751				<0x664703a0 0x01c>;
752			reg-names = "mspi", "bspi", "intr_regs",
753				"intr_status_reg";
754			interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
755			interrupt-names = "spi_l1_intr";
756			clocks = <&iprocmed>;
757			clock-names = "iprocmed";
758			num-cs = <2>;
759			#address-cells = <1>;
760			#size-cells = <0>;
761		};
762
763	};
764};
765