1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	compatible = "brcm,bcm63146", "brcm,bcmbca";
11	#address-cells = <2>;
12	#size-cells = <2>;
13
14	interrupt-parent = <&gic>;
15
16	cpus {
17		#address-cells = <2>;
18		#size-cells = <0>;
19
20		B53_0: cpu@0 {
21			compatible = "brcm,brahma-b53";
22			device_type = "cpu";
23			reg = <0x0 0x0>;
24			next-level-cache = <&L2_0>;
25			enable-method = "psci";
26		};
27
28		B53_1: cpu@1 {
29			compatible = "brcm,brahma-b53";
30			device_type = "cpu";
31			reg = <0x0 0x1>;
32			next-level-cache = <&L2_0>;
33			enable-method = "psci";
34		};
35
36		L2_0: l2-cache0 {
37			compatible = "cache";
38			cache-level = <2>;
39		};
40	};
41
42	timer {
43		compatible = "arm,armv8-timer";
44		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
45			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
48	};
49
50	pmu: pmu {
51		compatible = "arm,cortex-a53-pmu";
52		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
53			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
54		interrupt-affinity = <&B53_0>, <&B53_1>;
55	};
56
57	clocks: clocks {
58		periph_clk: periph-clk {
59			compatible = "fixed-clock";
60			#clock-cells = <0>;
61			clock-frequency = <200000000>;
62		};
63		uart_clk: uart-clk {
64			compatible = "fixed-factor-clock";
65			#clock-cells = <0>;
66			clocks = <&periph_clk>;
67			clock-div = <4>;
68			clock-mult = <1>;
69		};
70	};
71
72	psci {
73		compatible = "arm,psci-0.2";
74		method = "smc";
75	};
76
77	axi@81000000 {
78		compatible = "simple-bus";
79		#address-cells = <1>;
80		#size-cells = <1>;
81		ranges = <0x0 0x0 0x81000000 0x8000>;
82
83		gic: interrupt-controller@1000 {
84			compatible = "arm,gic-400";
85			#interrupt-cells = <3>;
86			interrupt-controller;
87			reg = <0x1000 0x1000>,
88				<0x2000 0x2000>,
89				<0x4000 0x2000>,
90				<0x6000 0x2000>;
91			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
92					IRQ_TYPE_LEVEL_HIGH)>;
93		};
94	};
95
96	bus@ff800000 {
97		compatible = "simple-bus";
98		#address-cells = <1>;
99		#size-cells = <1>;
100		ranges = <0x0 0x0 0xff800000 0x800000>;
101
102		uart0: serial@12000 {
103			compatible = "arm,pl011", "arm,primecell";
104			reg = <0x12000 0x1000>;
105			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
106			clocks = <&uart_clk>, <&uart_clk>;
107			clock-names = "uartclk", "apb_pclk";
108			status = "disabled";
109		};
110	};
111};
112