1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	compatible = "brcm,bcm4912", "brcm,bcmbca";
11	#address-cells = <2>;
12	#size-cells = <2>;
13
14	interrupt-parent = <&gic>;
15
16	cpus {
17		#address-cells = <2>;
18		#size-cells = <0>;
19
20		B53_0: cpu@0 {
21			compatible = "brcm,brahma-b53";
22			device_type = "cpu";
23			reg = <0x0 0x0>;
24			next-level-cache = <&L2_0>;
25			enable-method = "psci";
26		};
27
28		B53_1: cpu@1 {
29			compatible = "brcm,brahma-b53";
30			device_type = "cpu";
31			reg = <0x0 0x1>;
32			next-level-cache = <&L2_0>;
33			enable-method = "psci";
34		};
35
36		B53_2: cpu@2 {
37			compatible = "brcm,brahma-b53";
38			device_type = "cpu";
39			reg = <0x0 0x2>;
40			next-level-cache = <&L2_0>;
41			enable-method = "psci";
42		};
43
44		B53_3: cpu@3 {
45			compatible = "brcm,brahma-b53";
46			device_type = "cpu";
47			reg = <0x0 0x3>;
48			next-level-cache = <&L2_0>;
49			enable-method = "psci";
50		};
51
52		L2_0: l2-cache0 {
53			compatible = "cache";
54		};
55	};
56
57	timer {
58		compatible = "arm,armv8-timer";
59		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
60			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
63	};
64
65	pmu: pmu {
66		compatible = "arm,cortex-a53-pmu";
67		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
68			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
69			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
70			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
71		interrupt-affinity = <&B53_0>, <&B53_1>,
72			<&B53_2>, <&B53_3>;
73	};
74
75	clocks: clocks {
76		periph_clk: periph-clk {
77			compatible = "fixed-clock";
78			#clock-cells = <0>;
79			clock-frequency = <200000000>;
80		};
81		uart_clk: uart-clk {
82			compatible = "fixed-factor-clock";
83			#clock-cells = <0>;
84			clocks = <&periph_clk>;
85			clock-div = <4>;
86			clock-mult = <1>;
87		};
88	};
89
90	psci {
91		compatible = "arm,psci-0.2";
92		method = "smc";
93	};
94
95	axi@81000000 {
96		compatible = "simple-bus";
97		#address-cells = <1>;
98		#size-cells = <1>;
99		ranges = <0x0 0x0 0x81000000 0x8000>;
100
101		gic: interrupt-controller@1000 {
102			compatible = "arm,gic-400";
103			#interrupt-cells = <3>;
104			interrupt-controller;
105			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
106			reg = <0x1000 0x1000>,
107				<0x2000 0x2000>,
108				<0x4000 0x2000>,
109				<0x6000 0x2000>;
110		};
111	};
112
113	bus@ff800000 {
114		compatible = "simple-bus";
115		#address-cells = <1>;
116		#size-cells = <1>;
117		ranges = <0x0 0x0 0xff800000 0x800000>;
118
119		uart0: serial@12000 {
120			compatible = "arm,pl011", "arm,primecell";
121			reg = <0x12000 0x1000>;
122			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
123			clocks = <&uart_clk>, <&uart_clk>;
124			clock-names = "uartclk", "apb_pclk";
125			status = "disabled";
126		};
127	};
128};
129