1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Linaro Ltd.
4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/bitmain,bm1880-reset.h>
9
10/ {
11	compatible = "bitmain,bm1880";
12	interrupt-parent = <&gic>;
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a53";
23			reg = <0x0>;
24			enable-method = "psci";
25		};
26
27		cpu1: cpu@1 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a53";
30			reg = <0x1>;
31			enable-method = "psci";
32		};
33	};
34
35	reserved-memory {
36		#address-cells = <2>;
37		#size-cells = <2>;
38		ranges;
39
40		secmon@100000000 {
41			reg = <0x1 0x00000000 0x0 0x20000>;
42			no-map;
43		};
44
45		jpu@130000000 {
46			reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
47			no-map;
48		};
49
50		vpu@138000000 {
51			reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
52			no-map;
53		};
54	};
55
56	psci {
57		compatible = "arm,psci-0.2";
58		method = "smc";
59	};
60
61	timer {
62		compatible = "arm,armv8-timer";
63		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
64			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
65			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
66			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
67	};
68
69	soc {
70		compatible = "simple-bus";
71		#address-cells = <2>;
72		#size-cells = <2>;
73		ranges;
74
75		gic: interrupt-controller@50001000 {
76			compatible = "arm,gic-400";
77			reg = <0x0 0x50001000 0x0 0x1000>,
78			      <0x0 0x50002000 0x0 0x2000>;
79			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
80			interrupt-controller;
81			#interrupt-cells = <3>;
82		};
83
84		sctrl: system-controller@50010000 {
85			compatible = "bitmain,bm1880-sctrl", "syscon",
86				     "simple-mfd";
87			reg = <0x0 0x50010000 0x0 0x1000>;
88			#address-cells = <1>;
89			#size-cells = <1>;
90			ranges = <0x0 0x0 0x50010000 0x1000>;
91
92			pinctrl: pinctrl@400 {
93				compatible = "bitmain,bm1880-pinctrl";
94				reg = <0x400 0x120>;
95			};
96
97			rst: reset-controller@c00 {
98				compatible = "bitmain,bm1880-reset";
99				reg = <0xc00 0x8>;
100				#reset-cells = <1>;
101			};
102		};
103
104		gpio0: gpio@50027000 {
105			#address-cells = <1>;
106			#size-cells = <0>;
107			compatible = "snps,dw-apb-gpio";
108			reg = <0x0 0x50027000 0x0 0x400>;
109
110			porta: gpio-controller@0 {
111				compatible = "snps,dw-apb-gpio-port";
112				gpio-controller;
113				#gpio-cells = <2>;
114				snps,nr-gpios = <32>;
115				reg = <0>;
116				interrupt-controller;
117				#interrupt-cells = <2>;
118				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
119			};
120		};
121
122		gpio1: gpio@50027400 {
123			#address-cells = <1>;
124			#size-cells = <0>;
125			compatible = "snps,dw-apb-gpio";
126			reg = <0x0 0x50027400 0x0 0x400>;
127
128			portb: gpio-controller@0 {
129				compatible = "snps,dw-apb-gpio-port";
130				gpio-controller;
131				#gpio-cells = <2>;
132				snps,nr-gpios = <32>;
133				reg = <0>;
134				interrupt-controller;
135				#interrupt-cells = <2>;
136				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
137			};
138		};
139
140		gpio2: gpio@50027800 {
141			#address-cells = <1>;
142			#size-cells = <0>;
143			compatible = "snps,dw-apb-gpio";
144			reg = <0x0 0x50027800 0x0 0x400>;
145
146			portc: gpio-controller@0 {
147				compatible = "snps,dw-apb-gpio-port";
148				gpio-controller;
149				#gpio-cells = <2>;
150				snps,nr-gpios = <8>;
151				reg = <0>;
152				interrupt-controller;
153				#interrupt-cells = <2>;
154				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
155			};
156		};
157
158		uart0: serial@58018000 {
159			compatible = "snps,dw-apb-uart";
160			reg = <0x0 0x58018000 0x0 0x2000>;
161			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
162			reg-shift = <2>;
163			reg-io-width = <4>;
164			resets = <&rst BM1880_RST_UART0_1_CLK>;
165			status = "disabled";
166		};
167
168		uart1: serial@5801A000 {
169			compatible = "snps,dw-apb-uart";
170			reg = <0x0 0x5801a000 0x0 0x2000>;
171			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
172			reg-shift = <2>;
173			reg-io-width = <4>;
174			resets = <&rst BM1880_RST_UART0_1_ACLK>;
175			status = "disabled";
176		};
177
178		uart2: serial@5801C000 {
179			compatible = "snps,dw-apb-uart";
180			reg = <0x0 0x5801c000 0x0 0x2000>;
181			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
182			reg-shift = <2>;
183			reg-io-width = <4>;
184			resets = <&rst BM1880_RST_UART2_3_CLK>;
185			status = "disabled";
186		};
187
188		uart3: serial@5801E000 {
189			compatible = "snps,dw-apb-uart";
190			reg = <0x0 0x5801e000 0x0 0x2000>;
191			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
192			reg-shift = <2>;
193			reg-io-width = <4>;
194			resets = <&rst BM1880_RST_UART2_3_ACLK>;
195			status = "disabled";
196		};
197	};
198};
199