1/*
2 * ARM Ltd. Versatile Express
3 *
4 * LogicTile Express 20MG
5 * V2F-1XV7
6 *
7 * Cortex-A53 (2 cores) Soft Macrocell Model
8 *
9 * HBI-0247C
10 */
11
12/dts-v1/;
13
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16/ {
17	model = "V2F-1XV7 Cortex-A53x2 SMM";
18	arm,hbi = <0x247>;
19	arm,vexpress,site = <0xf>;
20	compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
21	interrupt-parent = <&gic>;
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	chosen {
26		stdout-path = "serial0:38400n8";
27	};
28
29	aliases {
30		serial0 = &v2m_serial0;
31		serial1 = &v2m_serial1;
32		serial2 = &v2m_serial2;
33		serial3 = &v2m_serial3;
34		i2c0 = &v2m_i2c_dvi;
35		i2c1 = &v2m_i2c_pcie;
36	};
37
38	cpus {
39		#address-cells = <2>;
40		#size-cells = <0>;
41
42		cpu@0 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a53", "arm,armv8";
45			reg = <0 0>;
46			next-level-cache = <&L2_0>;
47		};
48
49		cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53", "arm,armv8";
52			reg = <0 1>;
53			next-level-cache = <&L2_0>;
54		};
55
56		L2_0: l2-cache0 {
57			compatible = "cache";
58		};
59	};
60
61	memory@80000000 {
62		device_type = "memory";
63		reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
64	};
65
66	gic: interrupt-controller@2c001000 {
67		compatible = "arm,gic-400";
68		#interrupt-cells = <3>;
69		#address-cells = <0>;
70		interrupt-controller;
71		reg = <0 0x2c001000 0 0x1000>,
72		      <0 0x2c002000 0 0x2000>,
73		      <0 0x2c004000 0 0x2000>,
74		      <0 0x2c006000 0 0x2000>;
75		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
76	};
77
78	timer {
79		compatible = "arm,armv8-timer";
80		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
81			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
82			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
83			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
84	};
85
86	pmu {
87		compatible = "arm,armv8-pmuv3";
88		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
89			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
90	};
91
92	dcc {
93		compatible = "arm,vexpress,config-bus";
94		arm,vexpress,config-bridge = <&v2m_sysreg>;
95
96		smbclk: osc@4 {
97			/* SMC clock */
98			compatible = "arm,vexpress-osc";
99			arm,vexpress-sysreg,func = <1 4>;
100			freq-range = <40000000 40000000>;
101			#clock-cells = <0>;
102			clock-output-names = "smclk";
103		};
104
105		volt@0 {
106			/* VIO to expansion board above */
107			compatible = "arm,vexpress-volt";
108			arm,vexpress-sysreg,func = <2 0>;
109			regulator-name = "VIO_UP";
110			regulator-min-microvolt = <800000>;
111			regulator-max-microvolt = <1800000>;
112			regulator-always-on;
113		};
114
115		volt@1 {
116			/* 12V from power connector J6 */
117			compatible = "arm,vexpress-volt";
118			arm,vexpress-sysreg,func = <2 1>;
119			regulator-name = "12";
120			regulator-always-on;
121		};
122
123		temp@0 {
124			/* FPGA temperature */
125			compatible = "arm,vexpress-temp";
126			arm,vexpress-sysreg,func = <4 0>;
127			label = "FPGA";
128		};
129	};
130
131	smb {
132		compatible = "simple-bus";
133
134		#address-cells = <2>;
135		#size-cells = <1>;
136		ranges = <0 0 0 0x08000000 0x04000000>,
137			 <1 0 0 0x14000000 0x04000000>,
138			 <2 0 0 0x18000000 0x04000000>,
139			 <3 0 0 0x1c000000 0x04000000>,
140			 <4 0 0 0x0c000000 0x04000000>,
141			 <5 0 0 0x10000000 0x04000000>;
142
143		#interrupt-cells = <1>;
144		interrupt-map-mask = <0 0 63>;
145		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
146				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
147				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
148				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
149				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
150				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
151				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
152				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
153				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
154				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
155				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
156				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
157				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
158				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
159				<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
160				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
161				<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
162				<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
163				<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
164				<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
165				<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
166				<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
167				<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
168				<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
169				<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
170				<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
171				<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
172				<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
173				<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
174				<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
175				<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
176				<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
177				<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
178				<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
179				<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
180				<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
181				<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
182				<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
183				<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
184				<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
185				<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
186				<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
187				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
188
189		/include/ "vexpress-v2m-rs1.dtsi"
190	};
191};
192