1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * LogicTile Express 20MG
6 * V2F-1XV7
7 *
8 * Cortex-A53 (2 cores) Soft Macrocell Model
9 *
10 * HBI-0247C
11 */
12
13/dts-v1/;
14
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18	model = "V2F-1XV7 Cortex-A53x2 SMM";
19	arm,hbi = <0x247>;
20	arm,vexpress,site = <0xf>;
21	compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
22	interrupt-parent = <&gic>;
23	#address-cells = <2>;
24	#size-cells = <2>;
25
26	chosen {
27		stdout-path = "serial0:38400n8";
28	};
29
30	aliases {
31		serial0 = &v2m_serial0;
32		serial1 = &v2m_serial1;
33		serial2 = &v2m_serial2;
34		serial3 = &v2m_serial3;
35		i2c0 = &v2m_i2c_dvi;
36		i2c1 = &v2m_i2c_pcie;
37	};
38
39	cpus {
40		#address-cells = <2>;
41		#size-cells = <0>;
42
43		cpu@0 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53", "arm,armv8";
46			reg = <0 0>;
47			next-level-cache = <&L2_0>;
48		};
49
50		cpu@1 {
51			device_type = "cpu";
52			compatible = "arm,cortex-a53", "arm,armv8";
53			reg = <0 1>;
54			next-level-cache = <&L2_0>;
55		};
56
57		L2_0: l2-cache0 {
58			compatible = "cache";
59		};
60	};
61
62	memory@80000000 {
63		device_type = "memory";
64		reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
65	};
66
67	gic: interrupt-controller@2c001000 {
68		compatible = "arm,gic-400";
69		#interrupt-cells = <3>;
70		#address-cells = <0>;
71		interrupt-controller;
72		reg = <0 0x2c001000 0 0x1000>,
73		      <0 0x2c002000 0 0x2000>,
74		      <0 0x2c004000 0 0x2000>,
75		      <0 0x2c006000 0 0x2000>;
76		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
77	};
78
79	timer {
80		compatible = "arm,armv8-timer";
81		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
82			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
83			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
84			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
85	};
86
87	pmu {
88		compatible = "arm,armv8-pmuv3";
89		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
90			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
91	};
92
93	dcc {
94		compatible = "arm,vexpress,config-bus";
95		arm,vexpress,config-bridge = <&v2m_sysreg>;
96
97		smbclk: smclk {
98			/* SMC clock */
99			compatible = "arm,vexpress-osc";
100			arm,vexpress-sysreg,func = <1 4>;
101			freq-range = <40000000 40000000>;
102			#clock-cells = <0>;
103			clock-output-names = "smclk";
104		};
105
106		volt-vio {
107			/* VIO to expansion board above */
108			compatible = "arm,vexpress-volt";
109			arm,vexpress-sysreg,func = <2 0>;
110			regulator-name = "VIO_UP";
111			regulator-min-microvolt = <800000>;
112			regulator-max-microvolt = <1800000>;
113			regulator-always-on;
114		};
115
116		volt-12v {
117			/* 12V from power connector J6 */
118			compatible = "arm,vexpress-volt";
119			arm,vexpress-sysreg,func = <2 1>;
120			regulator-name = "12";
121			regulator-always-on;
122		};
123
124		temp-fpga {
125			/* FPGA temperature */
126			compatible = "arm,vexpress-temp";
127			arm,vexpress-sysreg,func = <4 0>;
128			label = "FPGA";
129		};
130	};
131
132	smb@8000000 {
133		compatible = "simple-bus";
134
135		#address-cells = <2>;
136		#size-cells = <1>;
137		ranges = <0 0 0 0x08000000 0x04000000>,
138			 <1 0 0 0x14000000 0x04000000>,
139			 <2 0 0 0x18000000 0x04000000>,
140			 <3 0 0 0x1c000000 0x04000000>,
141			 <4 0 0 0x0c000000 0x04000000>,
142			 <5 0 0 0x10000000 0x04000000>;
143
144		#interrupt-cells = <1>;
145		interrupt-map-mask = <0 0 63>;
146		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
147				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
148				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
149				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
150				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
151				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
152				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
153				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
154				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
155				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
156				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
157				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
158				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
159				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
160				<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
161				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
162				<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
163				<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
164				<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
165				<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
166				<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
167				<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
168				<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
169				<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
170				<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
171				<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
172				<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
173				<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
174				<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
175				<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
176				<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
177				<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
178				<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
179				<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
180				<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
181				<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
182				<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
183				<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
184				<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
185				<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
186				<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
187				<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
188				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
189
190		/include/ "vexpress-v2m-rs1.dtsi"
191	};
192};
193