1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Fast Models
4 *
5 * Versatile Express (VE) system model
6 * Motherboard component
7 *
8 * VEMotherBoard.lisa
9 */
10
11	motherboard {
12		arm,v2m-memory-map = "rs1";
13		compatible = "arm,vexpress,v2m-p1", "simple-bus";
14		#address-cells = <2>; /* SMB chipselect number and offset */
15		#size-cells = <1>;
16		#interrupt-cells = <1>;
17		ranges;
18
19		flash@0,00000000 {
20			compatible = "arm,vexpress-flash", "cfi-flash";
21			reg = <0 0x00000000 0x04000000>,
22			      <4 0x00000000 0x04000000>;
23			bank-width = <4>;
24		};
25
26		v2m_video_ram: vram@2,00000000 {
27			compatible = "arm,vexpress-vram";
28			reg = <2 0x00000000 0x00800000>;
29		};
30
31		ethernet@2,02000000 {
32			compatible = "smsc,lan91c111";
33			reg = <2 0x02000000 0x10000>;
34			interrupts = <15>;
35		};
36
37		v2m_clk24mhz: clk24mhz {
38			compatible = "fixed-clock";
39			#clock-cells = <0>;
40			clock-frequency = <24000000>;
41			clock-output-names = "v2m:clk24mhz";
42		};
43
44		v2m_refclk1mhz: refclk1mhz {
45			compatible = "fixed-clock";
46			#clock-cells = <0>;
47			clock-frequency = <1000000>;
48			clock-output-names = "v2m:refclk1mhz";
49		};
50
51		v2m_refclk32khz: refclk32khz {
52			compatible = "fixed-clock";
53			#clock-cells = <0>;
54			clock-frequency = <32768>;
55			clock-output-names = "v2m:refclk32khz";
56		};
57
58		iofpga@3,00000000 {
59			compatible = "simple-bus";
60			#address-cells = <1>;
61			#size-cells = <1>;
62			ranges = <0 3 0 0x200000>;
63
64			v2m_sysreg: sysreg@10000 {
65				compatible = "arm,vexpress-sysreg";
66				reg = <0x010000 0x1000>;
67				gpio-controller;
68				#gpio-cells = <2>;
69			};
70
71			v2m_sysctl: sysctl@20000 {
72				compatible = "arm,sp810", "arm,primecell";
73				reg = <0x020000 0x1000>;
74				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
75				clock-names = "refclk", "timclk", "apb_pclk";
76				#clock-cells = <1>;
77				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
78				assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
79				assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
80			};
81
82			aaci@40000 {
83				compatible = "arm,pl041", "arm,primecell";
84				reg = <0x040000 0x1000>;
85				interrupts = <11>;
86				clocks = <&v2m_clk24mhz>;
87				clock-names = "apb_pclk";
88			};
89
90			mmci@50000 {
91				compatible = "arm,pl180", "arm,primecell";
92				reg = <0x050000 0x1000>;
93				interrupts = <9 10>;
94				cd-gpios = <&v2m_sysreg 0 0>;
95				wp-gpios = <&v2m_sysreg 1 0>;
96				max-frequency = <12000000>;
97				vmmc-supply = <&v2m_fixed_3v3>;
98				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
99				clock-names = "mclk", "apb_pclk";
100			};
101
102			kmi@60000 {
103				compatible = "arm,pl050", "arm,primecell";
104				reg = <0x060000 0x1000>;
105				interrupts = <12>;
106				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
107				clock-names = "KMIREFCLK", "apb_pclk";
108			};
109
110			kmi@70000 {
111				compatible = "arm,pl050", "arm,primecell";
112				reg = <0x070000 0x1000>;
113				interrupts = <13>;
114				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
115				clock-names = "KMIREFCLK", "apb_pclk";
116			};
117
118			v2m_serial0: uart@90000 {
119				compatible = "arm,pl011", "arm,primecell";
120				reg = <0x090000 0x1000>;
121				interrupts = <5>;
122				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
123				clock-names = "uartclk", "apb_pclk";
124			};
125
126			v2m_serial1: uart@a0000 {
127				compatible = "arm,pl011", "arm,primecell";
128				reg = <0x0a0000 0x1000>;
129				interrupts = <6>;
130				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
131				clock-names = "uartclk", "apb_pclk";
132			};
133
134			v2m_serial2: uart@b0000 {
135				compatible = "arm,pl011", "arm,primecell";
136				reg = <0x0b0000 0x1000>;
137				interrupts = <7>;
138				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
139				clock-names = "uartclk", "apb_pclk";
140			};
141
142			v2m_serial3: uart@c0000 {
143				compatible = "arm,pl011", "arm,primecell";
144				reg = <0x0c0000 0x1000>;
145				interrupts = <8>;
146				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
147				clock-names = "uartclk", "apb_pclk";
148			};
149
150			wdt@f0000 {
151				compatible = "arm,sp805", "arm,primecell";
152				reg = <0x0f0000 0x1000>;
153				interrupts = <0>;
154				clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
155				clock-names = "wdogclk", "apb_pclk";
156			};
157
158			v2m_timer01: timer@110000 {
159				compatible = "arm,sp804", "arm,primecell";
160				reg = <0x110000 0x1000>;
161				interrupts = <2>;
162				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
163				clock-names = "timclken1", "timclken2", "apb_pclk";
164			};
165
166			v2m_timer23: timer@120000 {
167				compatible = "arm,sp804", "arm,primecell";
168				reg = <0x120000 0x1000>;
169				interrupts = <3>;
170				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
171				clock-names = "timclken1", "timclken2", "apb_pclk";
172			};
173
174			rtc@170000 {
175				compatible = "arm,pl031", "arm,primecell";
176				reg = <0x170000 0x1000>;
177				interrupts = <4>;
178				clocks = <&v2m_clk24mhz>;
179				clock-names = "apb_pclk";
180			};
181
182			clcd@1f0000 {
183				compatible = "arm,pl111", "arm,primecell";
184				reg = <0x1f0000 0x1000>;
185				interrupt-names = "combined";
186				interrupts = <14>;
187				clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
188				clock-names = "clcdclk", "apb_pclk";
189				arm,pl11x,framebuffer = <0x18000000 0x00180000>;
190				memory-region = <&v2m_video_ram>;
191				max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
192
193				port {
194					v2m_clcd_pads: endpoint {
195						remote-endpoint = <&v2m_clcd_panel>;
196						arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
197					};
198				};
199
200				panel {
201					compatible = "panel-dpi";
202
203					port {
204						v2m_clcd_panel: endpoint {
205							remote-endpoint = <&v2m_clcd_pads>;
206						};
207					};
208
209					panel-timing {
210						clock-frequency = <63500127>;
211						hactive = <1024>;
212						hback-porch = <152>;
213						hfront-porch = <48>;
214						hsync-len = <104>;
215						vactive = <768>;
216						vback-porch = <23>;
217						vfront-porch = <3>;
218						vsync-len = <4>;
219					};
220				};
221			};
222
223			virtio-block@130000 {
224				compatible = "virtio,mmio";
225				reg = <0x130000 0x200>;
226				interrupts = <42>;
227			};
228		};
229
230		v2m_fixed_3v3: v2m-3v3 {
231			compatible = "regulator-fixed";
232			regulator-name = "3V3";
233			regulator-min-microvolt = <3300000>;
234			regulator-max-microvolt = <3300000>;
235			regulator-always-on;
236		};
237
238		mcc {
239			compatible = "arm,vexpress,config-bus";
240			arm,vexpress,config-bridge = <&v2m_sysreg>;
241
242			v2m_oscclk1: oscclk1 {
243				/* CLCD clock */
244				compatible = "arm,vexpress-osc";
245				arm,vexpress-sysreg,func = <1 1>;
246				freq-range = <23750000 63500000>;
247				#clock-cells = <0>;
248				clock-output-names = "v2m:oscclk1";
249			};
250
251			reset {
252				compatible = "arm,vexpress-reset";
253				arm,vexpress-sysreg,func = <5 0>;
254			};
255
256			muxfpga {
257				compatible = "arm,vexpress-muxfpga";
258				arm,vexpress-sysreg,func = <7 0>;
259			};
260
261			shutdown {
262				compatible = "arm,vexpress-shutdown";
263				arm,vexpress-sysreg,func = <8 0>;
264			};
265
266			reboot {
267				compatible = "arm,vexpress-reboot";
268				arm,vexpress-sysreg,func = <9 0>;
269			};
270
271			dvimode {
272				compatible = "arm,vexpress-dvimode";
273				arm,vexpress-sysreg,func = <11 0>;
274			};
275		};
276	};
277