1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Fast Models
4 *
5 * Versatile Express (VE) system model
6 * Motherboard component
7 *
8 * VEMotherBoard.lisa
9 */
10/ {
11	v2m_clk24mhz: clk24mhz {
12		compatible = "fixed-clock";
13		#clock-cells = <0>;
14		clock-frequency = <24000000>;
15		clock-output-names = "v2m:clk24mhz";
16	};
17
18	v2m_refclk1mhz: refclk1mhz {
19		compatible = "fixed-clock";
20		#clock-cells = <0>;
21		clock-frequency = <1000000>;
22		clock-output-names = "v2m:refclk1mhz";
23	};
24
25	v2m_refclk32khz: refclk32khz {
26		compatible = "fixed-clock";
27		#clock-cells = <0>;
28		clock-frequency = <32768>;
29		clock-output-names = "v2m:refclk32khz";
30	};
31
32	v2m_fixed_3v3: v2m-3v3 {
33		compatible = "regulator-fixed";
34		regulator-name = "3V3";
35		regulator-min-microvolt = <3300000>;
36		regulator-max-microvolt = <3300000>;
37		regulator-always-on;
38	};
39
40	mcc {
41		compatible = "arm,vexpress,config-bus";
42		arm,vexpress,config-bridge = <&v2m_sysreg>;
43
44		v2m_oscclk1: oscclk1 {
45			/* CLCD clock */
46			compatible = "arm,vexpress-osc";
47			arm,vexpress-sysreg,func = <1 1>;
48			freq-range = <23750000 63500000>;
49			#clock-cells = <0>;
50			clock-output-names = "v2m:oscclk1";
51		};
52
53		reset {
54			compatible = "arm,vexpress-reset";
55			arm,vexpress-sysreg,func = <5 0>;
56		};
57
58		muxfpga {
59			compatible = "arm,vexpress-muxfpga";
60			arm,vexpress-sysreg,func = <7 0>;
61		};
62
63		shutdown {
64			compatible = "arm,vexpress-shutdown";
65			arm,vexpress-sysreg,func = <8 0>;
66		};
67
68		reboot {
69			compatible = "arm,vexpress-reboot";
70			arm,vexpress-sysreg,func = <9 0>;
71		};
72
73		dvimode {
74			compatible = "arm,vexpress-dvimode";
75			arm,vexpress-sysreg,func = <11 0>;
76		};
77	};
78
79	bus@8000000 {
80		compatible = "simple-bus";
81		#address-cells = <2>;
82		#size-cells = <1>;
83		ranges = <0 0x8000000 0 0x8000000 0x18000000>;
84
85		motherboard-bus@8000000 {
86			compatible = "arm,vexpress,v2m-p1", "simple-bus";
87			#address-cells = <2>; /* SMB chipselect number and offset */
88			#size-cells = <1>;
89			ranges = <0 0 0 0x08000000 0x04000000>,
90				 <1 0 0 0x14000000 0x04000000>,
91				 <2 0 0 0x18000000 0x04000000>,
92				 <3 0 0 0x1c000000 0x04000000>,
93				 <4 0 0 0x0c000000 0x04000000>,
94				 <5 0 0 0x10000000 0x04000000>;
95
96			flash@0 {
97				compatible = "arm,vexpress-flash", "cfi-flash";
98				reg = <0 0x00000000 0x04000000>,
99				      <4 0x00000000 0x04000000>;
100				bank-width = <4>;
101			};
102
103			ethernet@202000000 {
104				compatible = "smsc,lan91c111";
105				reg = <2 0x02000000 0x10000>;
106				interrupts = <15>;
107			};
108
109			iofpga-bus@300000000 {
110				compatible = "simple-bus";
111				#address-cells = <1>;
112				#size-cells = <1>;
113				ranges = <0 3 0 0x200000>;
114
115				v2m_sysreg: sysreg@10000 {
116					compatible = "arm,vexpress-sysreg";
117					reg = <0x010000 0x1000>;
118					gpio-controller;
119					#gpio-cells = <2>;
120				};
121
122				v2m_sysctl: sysctl@20000 {
123					compatible = "arm,sp810", "arm,primecell";
124					reg = <0x020000 0x1000>;
125					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
126					clock-names = "refclk", "timclk", "apb_pclk";
127					#clock-cells = <1>;
128					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
129					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
130					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
131				};
132
133				aaci@40000 {
134					compatible = "arm,pl041", "arm,primecell";
135					reg = <0x040000 0x1000>;
136					interrupts = <11>;
137					clocks = <&v2m_clk24mhz>;
138					clock-names = "apb_pclk";
139				};
140
141				mmc@50000 {
142					compatible = "arm,pl180", "arm,primecell";
143					reg = <0x050000 0x1000>;
144					interrupts = <9>, <10>;
145					cd-gpios = <&v2m_sysreg 0 0>;
146					wp-gpios = <&v2m_sysreg 1 0>;
147					max-frequency = <12000000>;
148					vmmc-supply = <&v2m_fixed_3v3>;
149					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
150					clock-names = "mclk", "apb_pclk";
151				};
152
153				kmi@60000 {
154					compatible = "arm,pl050", "arm,primecell";
155					reg = <0x060000 0x1000>;
156					interrupts = <12>;
157					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
158					clock-names = "KMIREFCLK", "apb_pclk";
159				};
160
161				kmi@70000 {
162					compatible = "arm,pl050", "arm,primecell";
163					reg = <0x070000 0x1000>;
164					interrupts = <13>;
165					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
166					clock-names = "KMIREFCLK", "apb_pclk";
167				};
168
169				v2m_serial0: serial@90000 {
170					compatible = "arm,pl011", "arm,primecell";
171					reg = <0x090000 0x1000>;
172					interrupts = <5>;
173					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
174					clock-names = "uartclk", "apb_pclk";
175				};
176
177				v2m_serial1: serial@a0000 {
178					compatible = "arm,pl011", "arm,primecell";
179					reg = <0x0a0000 0x1000>;
180					interrupts = <6>;
181					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
182					clock-names = "uartclk", "apb_pclk";
183				};
184
185				v2m_serial2: serial@b0000 {
186					compatible = "arm,pl011", "arm,primecell";
187					reg = <0x0b0000 0x1000>;
188					interrupts = <7>;
189					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
190					clock-names = "uartclk", "apb_pclk";
191				};
192
193				v2m_serial3: serial@c0000 {
194					compatible = "arm,pl011", "arm,primecell";
195					reg = <0x0c0000 0x1000>;
196					interrupts = <8>;
197					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
198					clock-names = "uartclk", "apb_pclk";
199				};
200
201				watchdog@f0000 {
202					compatible = "arm,sp805", "arm,primecell";
203					reg = <0x0f0000 0x1000>;
204					interrupts = <0>;
205					clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
206					clock-names = "wdog_clk", "apb_pclk";
207				};
208
209				v2m_timer01: timer@110000 {
210					compatible = "arm,sp804", "arm,primecell";
211					reg = <0x110000 0x1000>;
212					interrupts = <2>;
213					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
214					clock-names = "timclken1", "timclken2", "apb_pclk";
215				};
216
217				v2m_timer23: timer@120000 {
218					compatible = "arm,sp804", "arm,primecell";
219					reg = <0x120000 0x1000>;
220					interrupts = <3>;
221					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
222					clock-names = "timclken1", "timclken2", "apb_pclk";
223				};
224
225				virtio-block@130000 {
226					compatible = "virtio,mmio";
227					reg = <0x130000 0x200>;
228					interrupts = <42>;
229				};
230
231				rtc@170000 {
232					compatible = "arm,pl031", "arm,primecell";
233					reg = <0x170000 0x1000>;
234					interrupts = <4>;
235					clocks = <&v2m_clk24mhz>;
236					clock-names = "apb_pclk";
237				};
238
239				clcd@1f0000 {
240					compatible = "arm,pl111", "arm,primecell";
241					reg = <0x1f0000 0x1000>;
242					interrupt-names = "combined";
243					interrupts = <14>;
244					clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
245					clock-names = "clcdclk", "apb_pclk";
246					memory-region = <&vram>;
247
248					port {
249						clcd_pads: endpoint {
250							remote-endpoint = <&panel_in>;
251							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
252						};
253					};
254				};
255			};
256		};
257	};
258};
259