1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Fast Models
4 *
5 * Architecture Envelope Model (AEM) ARMv8-A
6 * ARMAEMv8AMPCT
7 *
8 * RTSM_VE_AEMv8A.lisa
9 */
10
11/dts-v1/;
12
13/memreserve/ 0x80000000 0x00010000;
14
15#include "rtsm_ve-motherboard.dtsi"
16
17/ {
18	model = "RTSM_VE_AEMv8A";
19	compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
20	interrupt-parent = <&gic>;
21	#address-cells = <2>;
22	#size-cells = <2>;
23
24	chosen { };
25
26	aliases {
27		serial0 = &v2m_serial0;
28		serial1 = &v2m_serial1;
29		serial2 = &v2m_serial2;
30		serial3 = &v2m_serial3;
31	};
32
33	cpus {
34		#address-cells = <2>;
35		#size-cells = <0>;
36
37		cpu@0 {
38			device_type = "cpu";
39			compatible = "arm,armv8";
40			reg = <0x0 0x0>;
41			enable-method = "spin-table";
42			cpu-release-addr = <0x0 0x8000fff8>;
43			next-level-cache = <&L2_0>;
44		};
45		cpu@1 {
46			device_type = "cpu";
47			compatible = "arm,armv8";
48			reg = <0x0 0x1>;
49			enable-method = "spin-table";
50			cpu-release-addr = <0x0 0x8000fff8>;
51			next-level-cache = <&L2_0>;
52		};
53		cpu@2 {
54			device_type = "cpu";
55			compatible = "arm,armv8";
56			reg = <0x0 0x2>;
57			enable-method = "spin-table";
58			cpu-release-addr = <0x0 0x8000fff8>;
59			next-level-cache = <&L2_0>;
60		};
61		cpu@3 {
62			device_type = "cpu";
63			compatible = "arm,armv8";
64			reg = <0x0 0x3>;
65			enable-method = "spin-table";
66			cpu-release-addr = <0x0 0x8000fff8>;
67			next-level-cache = <&L2_0>;
68		};
69
70		L2_0: l2-cache0 {
71			compatible = "cache";
72		};
73	};
74
75	memory@80000000 {
76		device_type = "memory";
77		reg = <0x00000000 0x80000000 0 0x80000000>,
78		      <0x00000008 0x80000000 0 0x80000000>;
79	};
80
81	reserved-memory {
82		#address-cells = <2>;
83		#size-cells = <2>;
84		ranges;
85
86		/* Chipselect 2,00000000 is physically at 0x18000000 */
87		vram: vram@18000000 {
88			/* 8 MB of designated video RAM */
89			compatible = "shared-dma-pool";
90			reg = <0x00000000 0x18000000 0 0x00800000>;
91			no-map;
92		};
93	};
94
95	gic: interrupt-controller@2c001000 {
96		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
97		#interrupt-cells = <3>;
98		#address-cells = <0>;
99		interrupt-controller;
100		reg = <0x0 0x2c001000 0 0x1000>,
101		      <0x0 0x2c002000 0 0x2000>,
102		      <0x0 0x2c004000 0 0x2000>,
103		      <0x0 0x2c006000 0 0x2000>;
104		interrupts = <1 9 0xf04>;
105	};
106
107	timer {
108		compatible = "arm,armv8-timer";
109		interrupts = <1 13 0xf08>,
110			     <1 14 0xf08>,
111			     <1 11 0xf08>,
112			     <1 10 0xf08>;
113		clock-frequency = <100000000>;
114	};
115
116	pmu {
117		compatible = "arm,armv8-pmuv3";
118		interrupts = <0 60 4>,
119			     <0 61 4>,
120			     <0 62 4>,
121			     <0 63 4>;
122	};
123
124	panel {
125		compatible = "arm,rtsm-display";
126		port {
127			panel_in: endpoint {
128				remote-endpoint = <&clcd_pads>;
129			};
130		};
131	};
132
133	smb@8000000 {
134		compatible = "simple-bus";
135
136		#address-cells = <2>;
137		#size-cells = <1>;
138		ranges = <0 0 0 0x08000000 0x04000000>,
139			 <1 0 0 0x14000000 0x04000000>,
140			 <2 0 0 0x18000000 0x04000000>,
141			 <3 0 0 0x1c000000 0x04000000>,
142			 <4 0 0 0x0c000000 0x04000000>,
143			 <5 0 0 0x10000000 0x04000000>;
144
145		#interrupt-cells = <1>;
146		interrupt-map-mask = <0 0 63>;
147		interrupt-map = <0 0  0 &gic 0  0 4>,
148				<0 0  1 &gic 0  1 4>,
149				<0 0  2 &gic 0  2 4>,
150				<0 0  3 &gic 0  3 4>,
151				<0 0  4 &gic 0  4 4>,
152				<0 0  5 &gic 0  5 4>,
153				<0 0  6 &gic 0  6 4>,
154				<0 0  7 &gic 0  7 4>,
155				<0 0  8 &gic 0  8 4>,
156				<0 0  9 &gic 0  9 4>,
157				<0 0 10 &gic 0 10 4>,
158				<0 0 11 &gic 0 11 4>,
159				<0 0 12 &gic 0 12 4>,
160				<0 0 13 &gic 0 13 4>,
161				<0 0 14 &gic 0 14 4>,
162				<0 0 15 &gic 0 15 4>,
163				<0 0 16 &gic 0 16 4>,
164				<0 0 17 &gic 0 17 4>,
165				<0 0 18 &gic 0 18 4>,
166				<0 0 19 &gic 0 19 4>,
167				<0 0 20 &gic 0 20 4>,
168				<0 0 21 &gic 0 21 4>,
169				<0 0 22 &gic 0 22 4>,
170				<0 0 23 &gic 0 23 4>,
171				<0 0 24 &gic 0 24 4>,
172				<0 0 25 &gic 0 25 4>,
173				<0 0 26 &gic 0 26 4>,
174				<0 0 27 &gic 0 27 4>,
175				<0 0 28 &gic 0 28 4>,
176				<0 0 29 &gic 0 29 4>,
177				<0 0 30 &gic 0 30 4>,
178				<0 0 31 &gic 0 31 4>,
179				<0 0 32 &gic 0 32 4>,
180				<0 0 33 &gic 0 33 4>,
181				<0 0 34 &gic 0 34 4>,
182				<0 0 35 &gic 0 35 4>,
183				<0 0 36 &gic 0 36 4>,
184				<0 0 37 &gic 0 37 4>,
185				<0 0 38 &gic 0 38 4>,
186				<0 0 39 &gic 0 39 4>,
187				<0 0 40 &gic 0 40 4>,
188				<0 0 41 &gic 0 41 4>,
189				<0 0 42 &gic 0 42 4>;
190	};
191};
192