1/* 2 * ARM Ltd. Juno Platform 3 * 4 * Copyright (c) 2013-2014 ARM Ltd. 5 * 6 * This file is licensed under a dual GPLv2 or BSD license. 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/ { 14 model = "ARM Juno development board (r0)"; 15 compatible = "arm,juno", "arm,vexpress"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &soc_uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 psci { 29 compatible = "arm,psci-0.2"; 30 method = "smc"; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 A57_0: cpu@0 { 38 compatible = "arm,cortex-a57","arm,armv8"; 39 reg = <0x0 0x0>; 40 device_type = "cpu"; 41 enable-method = "psci"; 42 next-level-cache = <&A57_L2>; 43 }; 44 45 A57_1: cpu@1 { 46 compatible = "arm,cortex-a57","arm,armv8"; 47 reg = <0x0 0x1>; 48 device_type = "cpu"; 49 enable-method = "psci"; 50 next-level-cache = <&A57_L2>; 51 }; 52 53 A53_0: cpu@100 { 54 compatible = "arm,cortex-a53","arm,armv8"; 55 reg = <0x0 0x100>; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 next-level-cache = <&A53_L2>; 59 }; 60 61 A53_1: cpu@101 { 62 compatible = "arm,cortex-a53","arm,armv8"; 63 reg = <0x0 0x101>; 64 device_type = "cpu"; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 }; 68 69 A53_2: cpu@102 { 70 compatible = "arm,cortex-a53","arm,armv8"; 71 reg = <0x0 0x102>; 72 device_type = "cpu"; 73 enable-method = "psci"; 74 next-level-cache = <&A53_L2>; 75 }; 76 77 A53_3: cpu@103 { 78 compatible = "arm,cortex-a53","arm,armv8"; 79 reg = <0x0 0x103>; 80 device_type = "cpu"; 81 enable-method = "psci"; 82 next-level-cache = <&A53_L2>; 83 }; 84 85 A57_L2: l2-cache0 { 86 compatible = "cache"; 87 }; 88 89 A53_L2: l2-cache1 { 90 compatible = "cache"; 91 }; 92 }; 93 94 memory@80000000 { 95 device_type = "memory"; 96 /* last 16MB of the first memory area is reserved for secure world use by firmware */ 97 reg = <0x00000000 0x80000000 0x0 0x7f000000>, 98 <0x00000008 0x80000000 0x1 0x80000000>; 99 }; 100 101 gic: interrupt-controller@2c001000 { 102 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 103 reg = <0x0 0x2c010000 0 0x1000>, 104 <0x0 0x2c02f000 0 0x2000>, 105 <0x0 0x2c04f000 0 0x2000>, 106 <0x0 0x2c06f000 0 0x2000>; 107 #address-cells = <0>; 108 #interrupt-cells = <3>; 109 interrupt-controller; 110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 111 }; 112 113 timer { 114 compatible = "arm,armv8-timer"; 115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 119 }; 120 121 pmu { 122 compatible = "arm,armv8-pmuv3"; 123 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-affinity = <&A57_0>, 130 <&A57_1>, 131 <&A53_0>, 132 <&A53_1>, 133 <&A53_2>, 134 <&A53_3>; 135 }; 136 137 /include/ "juno-clocks.dtsi" 138 139 dma@7ff00000 { 140 compatible = "arm,pl330", "arm,primecell"; 141 reg = <0x0 0x7ff00000 0 0x1000>; 142 #dma-cells = <1>; 143 #dma-channels = <8>; 144 #dma-requests = <32>; 145 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&soc_faxiclk>; 154 clock-names = "apb_pclk"; 155 }; 156 157 soc_uart0: uart@7ff80000 { 158 compatible = "arm,pl011", "arm,primecell"; 159 reg = <0x0 0x7ff80000 0x0 0x1000>; 160 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&soc_uartclk>, <&soc_refclk100mhz>; 162 clock-names = "uartclk", "apb_pclk"; 163 }; 164 165 i2c@7ffa0000 { 166 compatible = "snps,designware-i2c"; 167 reg = <0x0 0x7ffa0000 0x0 0x1000>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 171 clock-frequency = <400000>; 172 i2c-sda-hold-time-ns = <500>; 173 clocks = <&soc_smc50mhz>; 174 175 dvi0: dvi-transmitter@70 { 176 compatible = "nxp,tda998x"; 177 reg = <0x70>; 178 }; 179 180 dvi1: dvi-transmitter@71 { 181 compatible = "nxp,tda998x"; 182 reg = <0x71>; 183 }; 184 }; 185 186 ohci@7ffb0000 { 187 compatible = "generic-ohci"; 188 reg = <0x0 0x7ffb0000 0x0 0x10000>; 189 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&soc_usb48mhz>; 191 }; 192 193 ehci@7ffc0000 { 194 compatible = "generic-ehci"; 195 reg = <0x0 0x7ffc0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&soc_usb48mhz>; 198 }; 199 200 memory-controller@7ffd0000 { 201 compatible = "arm,pl354", "arm,primecell"; 202 reg = <0 0x7ffd0000 0 0x1000>; 203 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&soc_smc50mhz>; 206 clock-names = "apb_pclk"; 207 }; 208 209 smb { 210 compatible = "simple-bus"; 211 #address-cells = <2>; 212 #size-cells = <1>; 213 ranges = <0 0 0 0x08000000 0x04000000>, 214 <1 0 0 0x14000000 0x04000000>, 215 <2 0 0 0x18000000 0x04000000>, 216 <3 0 0 0x1c000000 0x04000000>, 217 <4 0 0 0x0c000000 0x04000000>, 218 <5 0 0 0x10000000 0x04000000>; 219 220 #interrupt-cells = <1>; 221 interrupt-map-mask = <0 0 15>; 222 interrupt-map = <0 0 0 &gic 0 68 IRQ_TYPE_LEVEL_HIGH>, 223 <0 0 1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, 224 <0 0 2 &gic 0 70 IRQ_TYPE_LEVEL_HIGH>, 225 <0 0 3 &gic 0 160 IRQ_TYPE_LEVEL_HIGH>, 226 <0 0 4 &gic 0 161 IRQ_TYPE_LEVEL_HIGH>, 227 <0 0 5 &gic 0 162 IRQ_TYPE_LEVEL_HIGH>, 228 <0 0 6 &gic 0 163 IRQ_TYPE_LEVEL_HIGH>, 229 <0 0 7 &gic 0 164 IRQ_TYPE_LEVEL_HIGH>, 230 <0 0 8 &gic 0 165 IRQ_TYPE_LEVEL_HIGH>, 231 <0 0 9 &gic 0 166 IRQ_TYPE_LEVEL_HIGH>, 232 <0 0 10 &gic 0 167 IRQ_TYPE_LEVEL_HIGH>, 233 <0 0 11 &gic 0 168 IRQ_TYPE_LEVEL_HIGH>, 234 <0 0 12 &gic 0 169 IRQ_TYPE_LEVEL_HIGH>; 235 236 /include/ "juno-motherboard.dtsi" 237 }; 238}; 239