1/* 2 * ARM Ltd. Juno Platform 3 * 4 * Copyright (c) 2015 ARM Ltd. 5 * 6 * This file is licensed under a dual GPLv2 or BSD license. 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include "juno-base.dtsi" 13#include "juno-cs-r1r2.dtsi" 14 15/ { 16 model = "ARM Juno development board (r1)"; 17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &soc_uart0; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 psci { 31 compatible = "arm,psci-0.2"; 32 method = "smc"; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&A57_0>; 43 }; 44 core1 { 45 cpu = <&A57_1>; 46 }; 47 }; 48 49 cluster1 { 50 core0 { 51 cpu = <&A53_0>; 52 }; 53 core1 { 54 cpu = <&A53_1>; 55 }; 56 core2 { 57 cpu = <&A53_2>; 58 }; 59 core3 { 60 cpu = <&A53_3>; 61 }; 62 }; 63 }; 64 65 idle-states { 66 entry-method = "psci"; 67 68 CPU_SLEEP_0: cpu-sleep-0 { 69 compatible = "arm,idle-state"; 70 arm,psci-suspend-param = <0x0010000>; 71 local-timer-stop; 72 entry-latency-us = <300>; 73 exit-latency-us = <1200>; 74 min-residency-us = <2000>; 75 }; 76 77 CLUSTER_SLEEP_0: cluster-sleep-0 { 78 compatible = "arm,idle-state"; 79 arm,psci-suspend-param = <0x1010000>; 80 local-timer-stop; 81 entry-latency-us = <400>; 82 exit-latency-us = <1200>; 83 min-residency-us = <2500>; 84 }; 85 }; 86 87 A57_0: cpu@0 { 88 compatible = "arm,cortex-a57","arm,armv8"; 89 reg = <0x0 0x0>; 90 device_type = "cpu"; 91 enable-method = "psci"; 92 i-cache-size = <0xc000>; 93 i-cache-line-size = <64>; 94 i-cache-sets = <256>; 95 d-cache-size = <0x8000>; 96 d-cache-line-size = <64>; 97 d-cache-sets = <256>; 98 next-level-cache = <&A57_L2>; 99 clocks = <&scpi_dvfs 0>; 100 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 101 capacity-dmips-mhz = <1024>; 102 }; 103 104 A57_1: cpu@1 { 105 compatible = "arm,cortex-a57","arm,armv8"; 106 reg = <0x0 0x1>; 107 device_type = "cpu"; 108 enable-method = "psci"; 109 i-cache-size = <0xc000>; 110 i-cache-line-size = <64>; 111 i-cache-sets = <256>; 112 d-cache-size = <0x8000>; 113 d-cache-line-size = <64>; 114 d-cache-sets = <256>; 115 next-level-cache = <&A57_L2>; 116 clocks = <&scpi_dvfs 0>; 117 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 118 capacity-dmips-mhz = <1024>; 119 }; 120 121 A53_0: cpu@100 { 122 compatible = "arm,cortex-a53","arm,armv8"; 123 reg = <0x0 0x100>; 124 device_type = "cpu"; 125 enable-method = "psci"; 126 i-cache-size = <0x8000>; 127 i-cache-line-size = <64>; 128 i-cache-sets = <256>; 129 d-cache-size = <0x8000>; 130 d-cache-line-size = <64>; 131 d-cache-sets = <128>; 132 next-level-cache = <&A53_L2>; 133 clocks = <&scpi_dvfs 1>; 134 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 135 capacity-dmips-mhz = <578>; 136 }; 137 138 A53_1: cpu@101 { 139 compatible = "arm,cortex-a53","arm,armv8"; 140 reg = <0x0 0x101>; 141 device_type = "cpu"; 142 enable-method = "psci"; 143 i-cache-size = <0x8000>; 144 i-cache-line-size = <64>; 145 i-cache-sets = <256>; 146 d-cache-size = <0x8000>; 147 d-cache-line-size = <64>; 148 d-cache-sets = <128>; 149 next-level-cache = <&A53_L2>; 150 clocks = <&scpi_dvfs 1>; 151 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 152 capacity-dmips-mhz = <578>; 153 }; 154 155 A53_2: cpu@102 { 156 compatible = "arm,cortex-a53","arm,armv8"; 157 reg = <0x0 0x102>; 158 device_type = "cpu"; 159 enable-method = "psci"; 160 i-cache-size = <0x8000>; 161 i-cache-line-size = <64>; 162 i-cache-sets = <256>; 163 d-cache-size = <0x8000>; 164 d-cache-line-size = <64>; 165 d-cache-sets = <128>; 166 next-level-cache = <&A53_L2>; 167 clocks = <&scpi_dvfs 1>; 168 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 169 capacity-dmips-mhz = <578>; 170 }; 171 172 A53_3: cpu@103 { 173 compatible = "arm,cortex-a53","arm,armv8"; 174 reg = <0x0 0x103>; 175 device_type = "cpu"; 176 enable-method = "psci"; 177 i-cache-size = <0x8000>; 178 i-cache-line-size = <64>; 179 i-cache-sets = <256>; 180 d-cache-size = <0x8000>; 181 d-cache-line-size = <64>; 182 d-cache-sets = <128>; 183 next-level-cache = <&A53_L2>; 184 clocks = <&scpi_dvfs 1>; 185 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 186 capacity-dmips-mhz = <578>; 187 }; 188 189 A57_L2: l2-cache0 { 190 compatible = "cache"; 191 cache-size = <0x200000>; 192 cache-line-size = <64>; 193 cache-sets = <2048>; 194 }; 195 196 A53_L2: l2-cache1 { 197 compatible = "cache"; 198 cache-size = <0x100000>; 199 cache-line-size = <64>; 200 cache-sets = <1024>; 201 }; 202 }; 203 204 pmu-a57 { 205 compatible = "arm,cortex-a57-pmu"; 206 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-affinity = <&A57_0>, 209 <&A57_1>; 210 }; 211 212 pmu-a53 { 213 compatible = "arm,cortex-a53-pmu"; 214 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 218 interrupt-affinity = <&A53_0>, 219 <&A53_1>, 220 <&A53_2>, 221 <&A53_3>; 222 }; 223}; 224 225&memtimer { 226 status = "okay"; 227}; 228 229&pcie_ctlr { 230 status = "okay"; 231}; 232 233&etm0 { 234 cpu = <&A57_0>; 235}; 236 237&etm1 { 238 cpu = <&A57_1>; 239}; 240 241&etm2 { 242 cpu = <&A53_0>; 243}; 244 245&etm3 { 246 cpu = <&A53_1>; 247}; 248 249&etm4 { 250 cpu = <&A53_2>; 251}; 252 253&etm5 { 254 cpu = <&A53_3>; 255}; 256 257&big_cluster_thermal_zone { 258 status = "okay"; 259}; 260 261&little_cluster_thermal_zone { 262 status = "okay"; 263}; 264 265&gpu0_thermal_zone { 266 status = "okay"; 267}; 268 269&gpu1_thermal_zone { 270 status = "okay"; 271}; 272 273&etf0_out_port { 274 remote-endpoint = <&csys2_funnel_in_port0>; 275}; 276 277&replicator_in_port0 { 278 remote-endpoint = <&csys2_funnel_out_port>; 279}; 280 281&csys1_funnel_in_port0 { 282 remote-endpoint = <&stm_out_port>; 283}; 284 285&stm_out_port { 286 remote-endpoint = <&csys1_funnel_in_port0>; 287}; 288 289&cpu_debug0 { 290 cpu = <&A57_0>; 291}; 292 293&cpu_debug1 { 294 cpu = <&A57_1>; 295}; 296 297&cpu_debug2 { 298 cpu = <&A53_0>; 299}; 300 301&cpu_debug3 { 302 cpu = <&A53_1>; 303}; 304 305&cpu_debug4 { 306 cpu = <&A53_2>; 307}; 308 309&cpu_debug5 { 310 cpu = <&A53_3>; 311}; 312