1/* 2 * ARM Juno Platform motherboard peripherals 3 * 4 * Copyright (c) 2013-2014 ARM Ltd 5 * 6 * This file is licensed under a dual GPLv2 or BSD license. 7 * 8 */ 9 10 mb_clk24mhz: clk24mhz { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <24000000>; 14 clock-output-names = "juno_mb:clk24mhz"; 15 }; 16 17 mb_clk25mhz: clk25mhz { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <25000000>; 21 clock-output-names = "juno_mb:clk25mhz"; 22 }; 23 24 v2m_refclk1mhz: refclk1mhz { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <1000000>; 28 clock-output-names = "juno_mb:refclk1mhz"; 29 }; 30 31 v2m_refclk32khz: refclk32khz { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <32768>; 35 clock-output-names = "juno_mb:refclk32khz"; 36 }; 37 38 motherboard { 39 compatible = "arm,vexpress,v2p-p1", "simple-bus"; 40 #address-cells = <2>; /* SMB chipselect number and offset */ 41 #size-cells = <1>; 42 #interrupt-cells = <1>; 43 ranges; 44 model = "V2M-Juno"; 45 arm,hbi = <0x252>; 46 arm,vexpress,site = <0>; 47 arm,v2m-memory-map = "rs1"; 48 49 mb_fixed_3v3: fixedregulator@0 { 50 compatible = "regulator-fixed"; 51 regulator-name = "MCC_SB_3V3"; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 regulator-always-on; 55 }; 56 57 gpio_keys { 58 compatible = "gpio-keys"; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 button@1 { 63 debounce_interval = <50>; 64 wakeup = <1>; 65 linux,code = <116>; 66 label = "POWER"; 67 gpios = <&iofpga_gpio0 0 0x4>; 68 }; 69 button@2 { 70 debounce_interval = <50>; 71 wakeup = <1>; 72 linux,code = <102>; 73 label = "HOME"; 74 gpios = <&iofpga_gpio0 1 0x4>; 75 }; 76 button@3 { 77 debounce_interval = <50>; 78 wakeup = <1>; 79 linux,code = <152>; 80 label = "RLOCK"; 81 gpios = <&iofpga_gpio0 2 0x4>; 82 }; 83 button@4 { 84 debounce_interval = <50>; 85 wakeup = <1>; 86 linux,code = <115>; 87 label = "VOL+"; 88 gpios = <&iofpga_gpio0 3 0x4>; 89 }; 90 button@5 { 91 debounce_interval = <50>; 92 wakeup = <1>; 93 linux,code = <114>; 94 label = "VOL-"; 95 gpios = <&iofpga_gpio0 4 0x4>; 96 }; 97 button@6 { 98 debounce_interval = <50>; 99 wakeup = <1>; 100 linux,code = <99>; 101 label = "NMI"; 102 gpios = <&iofpga_gpio0 5 0x4>; 103 }; 104 }; 105 106 ethernet@2,00000000 { 107 compatible = "smsc,lan9118", "smsc,lan9115"; 108 reg = <2 0x00000000 0x10000>; 109 interrupts = <3>; 110 phy-mode = "mii"; 111 reg-io-width = <4>; 112 smsc,irq-active-high; 113 smsc,irq-push-pull; 114 clocks = <&mb_clk25mhz>; 115 vdd33a-supply = <&mb_fixed_3v3>; 116 vddvario-supply = <&mb_fixed_3v3>; 117 }; 118 119 usb@5,00000000 { 120 compatible = "nxp,usb-isp1763"; 121 reg = <5 0x00000000 0x20000>; 122 bus-width = <16>; 123 interrupts = <4>; 124 }; 125 126 iofpga@3,00000000 { 127 compatible = "arm,amba-bus", "simple-bus"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges = <0 3 0 0x200000>; 131 132 v2m_sysctl: sysctl@020000 { 133 compatible = "arm,sp810", "arm,primecell"; 134 reg = <0x020000 0x1000>; 135 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>; 136 clock-names = "refclk", "timclk", "apb_pclk"; 137 #clock-cells = <1>; 138 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 139 }; 140 141 apbregs@010000 { 142 compatible = "syscon", "simple-mfd"; 143 reg = <0x010000 0x1000>; 144 145 led@08.0 { 146 compatible = "register-bit-led"; 147 offset = <0x08>; 148 mask = <0x01>; 149 label = "vexpress:0"; 150 linux,default-trigger = "heartbeat"; 151 default-state = "on"; 152 }; 153 led@08.1 { 154 compatible = "register-bit-led"; 155 offset = <0x08>; 156 mask = <0x02>; 157 label = "vexpress:1"; 158 linux,default-trigger = "mmc0"; 159 default-state = "off"; 160 }; 161 led@08.2 { 162 compatible = "register-bit-led"; 163 offset = <0x08>; 164 mask = <0x04>; 165 label = "vexpress:2"; 166 linux,default-trigger = "cpu0"; 167 default-state = "off"; 168 }; 169 led@08.3 { 170 compatible = "register-bit-led"; 171 offset = <0x08>; 172 mask = <0x08>; 173 label = "vexpress:3"; 174 linux,default-trigger = "cpu1"; 175 default-state = "off"; 176 }; 177 led@08.4 { 178 compatible = "register-bit-led"; 179 offset = <0x08>; 180 mask = <0x10>; 181 label = "vexpress:4"; 182 linux,default-trigger = "cpu2"; 183 default-state = "off"; 184 }; 185 led@08.5 { 186 compatible = "register-bit-led"; 187 offset = <0x08>; 188 mask = <0x20>; 189 label = "vexpress:5"; 190 linux,default-trigger = "cpu3"; 191 default-state = "off"; 192 }; 193 led@08.6 { 194 compatible = "register-bit-led"; 195 offset = <0x08>; 196 mask = <0x40>; 197 label = "vexpress:6"; 198 default-state = "off"; 199 }; 200 led@08.7 { 201 compatible = "register-bit-led"; 202 offset = <0x08>; 203 mask = <0x80>; 204 label = "vexpress:7"; 205 default-state = "off"; 206 }; 207 }; 208 209 mmci@050000 { 210 compatible = "arm,pl180", "arm,primecell"; 211 reg = <0x050000 0x1000>; 212 interrupts = <5>; 213 /* cd-gpios = <&v2m_mmc_gpios 0 0>; 214 wp-gpios = <&v2m_mmc_gpios 1 0>; */ 215 max-frequency = <12000000>; 216 vmmc-supply = <&mb_fixed_3v3>; 217 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 218 clock-names = "mclk", "apb_pclk"; 219 }; 220 221 kmi@060000 { 222 compatible = "arm,pl050", "arm,primecell"; 223 reg = <0x060000 0x1000>; 224 interrupts = <8>; 225 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 226 clock-names = "KMIREFCLK", "apb_pclk"; 227 }; 228 229 kmi@070000 { 230 compatible = "arm,pl050", "arm,primecell"; 231 reg = <0x070000 0x1000>; 232 interrupts = <8>; 233 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 234 clock-names = "KMIREFCLK", "apb_pclk"; 235 }; 236 237 wdt@0f0000 { 238 compatible = "arm,sp805", "arm,primecell"; 239 reg = <0x0f0000 0x10000>; 240 interrupts = <7>; 241 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 242 clock-names = "wdogclk", "apb_pclk"; 243 }; 244 245 v2m_timer01: timer@110000 { 246 compatible = "arm,sp804", "arm,primecell"; 247 reg = <0x110000 0x10000>; 248 interrupts = <9>; 249 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>; 250 clock-names = "timclken1", "timclken2", "apb_pclk"; 251 }; 252 253 v2m_timer23: timer@120000 { 254 compatible = "arm,sp804", "arm,primecell"; 255 reg = <0x120000 0x10000>; 256 interrupts = <9>; 257 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>; 258 clock-names = "timclken1", "timclken2", "apb_pclk"; 259 }; 260 261 rtc@170000 { 262 compatible = "arm,pl031", "arm,primecell"; 263 reg = <0x170000 0x10000>; 264 interrupts = <0>; 265 clocks = <&soc_smc50mhz>; 266 clock-names = "apb_pclk"; 267 }; 268 269 iofpga_gpio0: gpio@1d0000 { 270 compatible = "arm,pl061", "arm,primecell"; 271 reg = <0x1d0000 0x1000>; 272 interrupts = <6>; 273 clocks = <&soc_smc50mhz>; 274 clock-names = "apb_pclk"; 275 gpio-controller; 276 #gpio-cells = <2>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 }; 280 }; 281 }; 282