1/*
2 * ARM Juno Platform motherboard peripherals
3 *
4 * Copyright (c) 2013-2014 ARM Ltd
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 *
8 */
9
10		mb_clk24mhz: clk24mhz {
11			compatible = "fixed-clock";
12			#clock-cells = <0>;
13			clock-frequency = <24000000>;
14			clock-output-names = "juno_mb:clk24mhz";
15		};
16
17		mb_clk25mhz: clk25mhz {
18			compatible = "fixed-clock";
19			#clock-cells = <0>;
20			clock-frequency = <25000000>;
21			clock-output-names = "juno_mb:clk25mhz";
22		};
23
24		motherboard {
25			compatible = "arm,vexpress,v2p-p1", "simple-bus";
26			#address-cells = <2>;  /* SMB chipselect number and offset */
27			#size-cells = <1>;
28			#interrupt-cells = <1>;
29			ranges;
30			model = "V2M-Juno";
31			arm,hbi = <0x252>;
32			arm,vexpress,site = <0>;
33			arm,v2m-memory-map = "rs1";
34
35			mb_fixed_3v3: fixedregulator@0 {
36				compatible = "regulator-fixed";
37				regulator-name = "MCC_SB_3V3";
38				regulator-min-microvolt = <3300000>;
39				regulator-max-microvolt = <3300000>;
40				regulator-always-on;
41			};
42
43			ethernet@2,00000000 {
44				compatible = "smsc,lan9118", "smsc,lan9115";
45				reg = <2 0x00000000 0x10000>;
46				interrupts = <3>;
47				phy-mode = "mii";
48				reg-io-width = <4>;
49				smsc,irq-active-high;
50				smsc,irq-push-pull;
51				clocks = <&mb_clk25mhz>;
52				vdd33a-supply = <&mb_fixed_3v3>;
53				vddvario-supply = <&mb_fixed_3v3>;
54			};
55
56			usb@5,00000000 {
57				compatible = "nxp,usb-isp1763";
58				reg = <5 0x00000000 0x20000>;
59				bus-width = <16>;
60				interrupts = <4>;
61			};
62
63			iofpga@3,00000000 {
64				compatible = "arm,amba-bus", "simple-bus";
65				#address-cells = <1>;
66				#size-cells = <1>;
67				ranges = <0 3 0 0x200000>;
68
69				mmci@050000 {
70					compatible = "arm,pl180", "arm,primecell";
71					reg = <0x050000 0x1000>;
72					interrupts = <5>;
73					/* cd-gpios = <&v2m_mmc_gpios 0 0>;
74					wp-gpios = <&v2m_mmc_gpios 1 0>; */
75					max-frequency = <12000000>;
76					vmmc-supply = <&mb_fixed_3v3>;
77					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
78					clock-names = "mclk", "apb_pclk";
79				};
80
81				kmi@060000 {
82					compatible = "arm,pl050", "arm,primecell";
83					reg = <0x060000 0x1000>;
84					interrupts = <8>;
85					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
86					clock-names = "KMIREFCLK", "apb_pclk";
87				};
88
89				kmi@070000 {
90					compatible = "arm,pl050", "arm,primecell";
91					reg = <0x070000 0x1000>;
92					interrupts = <8>;
93					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
94					clock-names = "KMIREFCLK", "apb_pclk";
95				};
96
97				wdt@0f0000 {
98					compatible = "arm,sp805", "arm,primecell";
99					reg = <0x0f0000 0x10000>;
100					interrupts = <7>;
101					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
102					clock-names = "wdogclk", "apb_pclk";
103				};
104
105				v2m_timer01: timer@110000 {
106					compatible = "arm,sp804", "arm,primecell";
107					reg = <0x110000 0x10000>;
108					interrupts = <9>;
109					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
110					clock-names = "timclken1", "apb_pclk";
111				};
112
113				v2m_timer23: timer@120000 {
114					compatible = "arm,sp804", "arm,primecell";
115					reg = <0x120000 0x10000>;
116					interrupts = <9>;
117					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
118					clock-names = "timclken1", "apb_pclk";
119				};
120
121				rtc@170000 {
122					compatible = "arm,pl031", "arm,primecell";
123					reg = <0x170000 0x10000>;
124					interrupts = <0>;
125					clocks = <&soc_smc50mhz>;
126					clock-names = "apb_pclk";
127				};
128			};
129		};
130