1#include "juno-clocks.dtsi" 2 3/ { 4 /* 5 * Devices shared by all Juno boards 6 */ 7 dma-ranges = <0 0 0 0 0x100 0>; 8 9 memtimer: timer@2a810000 { 10 compatible = "arm,armv7-timer-mem"; 11 reg = <0x0 0x2a810000 0x0 0x10000>; 12 clock-frequency = <50000000>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 ranges; 16 status = "disabled"; 17 frame@2a830000 { 18 frame-number = <1>; 19 interrupts = <0 60 4>; 20 reg = <0x0 0x2a830000 0x0 0x10000>; 21 }; 22 }; 23 24 mailbox: mhu@2b1f0000 { 25 compatible = "arm,mhu", "arm,primecell"; 26 reg = <0x0 0x2b1f0000 0x0 0x1000>; 27 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 28 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-names = "mhu_lpri_rx", 30 "mhu_hpri_rx"; 31 #mbox-cells = <1>; 32 clocks = <&soc_refclk100mhz>; 33 clock-names = "apb_pclk"; 34 }; 35 36 smmu_pcie: iommu@2b500000 { 37 compatible = "arm,mmu-401", "arm,smmu-v1"; 38 reg = <0x0 0x2b500000 0x0 0x10000>; 39 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 41 #iommu-cells = <1>; 42 #global-interrupts = <1>; 43 dma-coherent; 44 status = "disabled"; 45 }; 46 47 smmu_etr: iommu@2b600000 { 48 compatible = "arm,mmu-401", "arm,smmu-v1"; 49 reg = <0x0 0x2b600000 0x0 0x10000>; 50 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 52 #iommu-cells = <1>; 53 #global-interrupts = <1>; 54 dma-coherent; 55 power-domains = <&scpi_devpd 0>; 56 }; 57 58 gic: interrupt-controller@2c010000 { 59 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 60 reg = <0x0 0x2c010000 0 0x1000>, 61 <0x0 0x2c02f000 0 0x2000>, 62 <0x0 0x2c04f000 0 0x2000>, 63 <0x0 0x2c06f000 0 0x2000>; 64 #address-cells = <2>; 65 #interrupt-cells = <3>; 66 #size-cells = <2>; 67 interrupt-controller; 68 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 69 ranges = <0 0 0 0x2c1c0000 0 0x40000>; 70 v2m_0: v2m@0 { 71 compatible = "arm,gic-v2m-frame"; 72 msi-controller; 73 reg = <0 0 0 0x1000>; 74 }; 75 }; 76 77 timer { 78 compatible = "arm,armv8-timer"; 79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 80 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 82 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 83 }; 84 85 /* 86 * Juno TRMs specify the size for these coresight components as 64K. 87 * The actual size is just 4K though 64K is reserved. Access to the 88 * unmapped reserved region results in a DECERR response. 89 */ 90 etf@20010000 { /* etf0 */ 91 compatible = "arm,coresight-tmc", "arm,primecell"; 92 reg = <0 0x20010000 0 0x1000>; 93 94 clocks = <&soc_smc50mhz>; 95 clock-names = "apb_pclk"; 96 power-domains = <&scpi_devpd 0>; 97 ports { 98 #address-cells = <1>; 99 #size-cells = <0>; 100 101 /* input port */ 102 port@0 { 103 reg = <0>; 104 etf0_in_port: endpoint { 105 slave-mode; 106 remote-endpoint = <&main_funnel_out_port>; 107 }; 108 }; 109 110 /* output port */ 111 port@1 { 112 reg = <0>; 113 etf0_out_port: endpoint { 114 }; 115 }; 116 }; 117 }; 118 119 tpiu@20030000 { 120 compatible = "arm,coresight-tpiu", "arm,primecell"; 121 reg = <0 0x20030000 0 0x1000>; 122 123 clocks = <&soc_smc50mhz>; 124 clock-names = "apb_pclk"; 125 power-domains = <&scpi_devpd 0>; 126 port { 127 tpiu_in_port: endpoint { 128 slave-mode; 129 remote-endpoint = <&replicator_out_port0>; 130 }; 131 }; 132 }; 133 134 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ 135 main_funnel: funnel@20040000 { 136 compatible = "arm,coresight-funnel", "arm,primecell"; 137 reg = <0 0x20040000 0 0x1000>; 138 139 clocks = <&soc_smc50mhz>; 140 clock-names = "apb_pclk"; 141 power-domains = <&scpi_devpd 0>; 142 ports { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 /* output port */ 147 port@0 { 148 reg = <0>; 149 main_funnel_out_port: endpoint { 150 remote-endpoint = <&etf0_in_port>; 151 }; 152 }; 153 154 /* input ports */ 155 port@1 { 156 reg = <0>; 157 main_funnel_in_port0: endpoint { 158 slave-mode; 159 remote-endpoint = <&cluster0_funnel_out_port>; 160 }; 161 }; 162 163 port@2 { 164 reg = <1>; 165 main_funnel_in_port1: endpoint { 166 slave-mode; 167 remote-endpoint = <&cluster1_funnel_out_port>; 168 }; 169 }; 170 }; 171 }; 172 173 etr@20070000 { 174 compatible = "arm,coresight-tmc", "arm,primecell"; 175 reg = <0 0x20070000 0 0x1000>; 176 iommus = <&smmu_etr 0>; 177 178 clocks = <&soc_smc50mhz>; 179 clock-names = "apb_pclk"; 180 power-domains = <&scpi_devpd 0>; 181 port { 182 etr_in_port: endpoint { 183 slave-mode; 184 remote-endpoint = <&replicator_out_port1>; 185 }; 186 }; 187 }; 188 189 stm@20100000 { 190 compatible = "arm,coresight-stm", "arm,primecell"; 191 reg = <0 0x20100000 0 0x1000>, 192 <0 0x28000000 0 0x1000000>; 193 reg-names = "stm-base", "stm-stimulus-base"; 194 195 clocks = <&soc_smc50mhz>; 196 clock-names = "apb_pclk"; 197 power-domains = <&scpi_devpd 0>; 198 port { 199 stm_out_port: endpoint { 200 }; 201 }; 202 }; 203 204 cpu_debug0: cpu-debug@22010000 { 205 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 206 reg = <0x0 0x22010000 0x0 0x1000>; 207 208 clocks = <&soc_smc50mhz>; 209 clock-names = "apb_pclk"; 210 power-domains = <&scpi_devpd 0>; 211 }; 212 213 etm0: etm@22040000 { 214 compatible = "arm,coresight-etm4x", "arm,primecell"; 215 reg = <0 0x22040000 0 0x1000>; 216 217 clocks = <&soc_smc50mhz>; 218 clock-names = "apb_pclk"; 219 power-domains = <&scpi_devpd 0>; 220 port { 221 cluster0_etm0_out_port: endpoint { 222 remote-endpoint = <&cluster0_funnel_in_port0>; 223 }; 224 }; 225 }; 226 227 funnel@220c0000 { /* cluster0 funnel */ 228 compatible = "arm,coresight-funnel", "arm,primecell"; 229 reg = <0 0x220c0000 0 0x1000>; 230 231 clocks = <&soc_smc50mhz>; 232 clock-names = "apb_pclk"; 233 power-domains = <&scpi_devpd 0>; 234 ports { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 238 port@0 { 239 reg = <0>; 240 cluster0_funnel_out_port: endpoint { 241 remote-endpoint = <&main_funnel_in_port0>; 242 }; 243 }; 244 245 port@1 { 246 reg = <0>; 247 cluster0_funnel_in_port0: endpoint { 248 slave-mode; 249 remote-endpoint = <&cluster0_etm0_out_port>; 250 }; 251 }; 252 253 port@2 { 254 reg = <1>; 255 cluster0_funnel_in_port1: endpoint { 256 slave-mode; 257 remote-endpoint = <&cluster0_etm1_out_port>; 258 }; 259 }; 260 }; 261 }; 262 263 cpu_debug1: cpu-debug@22110000 { 264 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 265 reg = <0x0 0x22110000 0x0 0x1000>; 266 267 clocks = <&soc_smc50mhz>; 268 clock-names = "apb_pclk"; 269 power-domains = <&scpi_devpd 0>; 270 }; 271 272 etm1: etm@22140000 { 273 compatible = "arm,coresight-etm4x", "arm,primecell"; 274 reg = <0 0x22140000 0 0x1000>; 275 276 clocks = <&soc_smc50mhz>; 277 clock-names = "apb_pclk"; 278 power-domains = <&scpi_devpd 0>; 279 port { 280 cluster0_etm1_out_port: endpoint { 281 remote-endpoint = <&cluster0_funnel_in_port1>; 282 }; 283 }; 284 }; 285 286 cpu_debug2: cpu-debug@23010000 { 287 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 288 reg = <0x0 0x23010000 0x0 0x1000>; 289 290 clocks = <&soc_smc50mhz>; 291 clock-names = "apb_pclk"; 292 power-domains = <&scpi_devpd 0>; 293 }; 294 295 etm2: etm@23040000 { 296 compatible = "arm,coresight-etm4x", "arm,primecell"; 297 reg = <0 0x23040000 0 0x1000>; 298 299 clocks = <&soc_smc50mhz>; 300 clock-names = "apb_pclk"; 301 power-domains = <&scpi_devpd 0>; 302 port { 303 cluster1_etm0_out_port: endpoint { 304 remote-endpoint = <&cluster1_funnel_in_port0>; 305 }; 306 }; 307 }; 308 309 funnel@230c0000 { /* cluster1 funnel */ 310 compatible = "arm,coresight-funnel", "arm,primecell"; 311 reg = <0 0x230c0000 0 0x1000>; 312 313 clocks = <&soc_smc50mhz>; 314 clock-names = "apb_pclk"; 315 power-domains = <&scpi_devpd 0>; 316 ports { 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 port@0 { 321 reg = <0>; 322 cluster1_funnel_out_port: endpoint { 323 remote-endpoint = <&main_funnel_in_port1>; 324 }; 325 }; 326 327 port@1 { 328 reg = <0>; 329 cluster1_funnel_in_port0: endpoint { 330 slave-mode; 331 remote-endpoint = <&cluster1_etm0_out_port>; 332 }; 333 }; 334 335 port@2 { 336 reg = <1>; 337 cluster1_funnel_in_port1: endpoint { 338 slave-mode; 339 remote-endpoint = <&cluster1_etm1_out_port>; 340 }; 341 }; 342 port@3 { 343 reg = <2>; 344 cluster1_funnel_in_port2: endpoint { 345 slave-mode; 346 remote-endpoint = <&cluster1_etm2_out_port>; 347 }; 348 }; 349 port@4 { 350 reg = <3>; 351 cluster1_funnel_in_port3: endpoint { 352 slave-mode; 353 remote-endpoint = <&cluster1_etm3_out_port>; 354 }; 355 }; 356 }; 357 }; 358 359 cpu_debug3: cpu-debug@23110000 { 360 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 361 reg = <0x0 0x23110000 0x0 0x1000>; 362 363 clocks = <&soc_smc50mhz>; 364 clock-names = "apb_pclk"; 365 power-domains = <&scpi_devpd 0>; 366 }; 367 368 etm3: etm@23140000 { 369 compatible = "arm,coresight-etm4x", "arm,primecell"; 370 reg = <0 0x23140000 0 0x1000>; 371 372 clocks = <&soc_smc50mhz>; 373 clock-names = "apb_pclk"; 374 power-domains = <&scpi_devpd 0>; 375 port { 376 cluster1_etm1_out_port: endpoint { 377 remote-endpoint = <&cluster1_funnel_in_port1>; 378 }; 379 }; 380 }; 381 382 cpu_debug4: cpu-debug@23210000 { 383 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 384 reg = <0x0 0x23210000 0x0 0x1000>; 385 386 clocks = <&soc_smc50mhz>; 387 clock-names = "apb_pclk"; 388 power-domains = <&scpi_devpd 0>; 389 }; 390 391 etm4: etm@23240000 { 392 compatible = "arm,coresight-etm4x", "arm,primecell"; 393 reg = <0 0x23240000 0 0x1000>; 394 395 clocks = <&soc_smc50mhz>; 396 clock-names = "apb_pclk"; 397 power-domains = <&scpi_devpd 0>; 398 port { 399 cluster1_etm2_out_port: endpoint { 400 remote-endpoint = <&cluster1_funnel_in_port2>; 401 }; 402 }; 403 }; 404 405 cpu_debug5: cpu-debug@23310000 { 406 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 407 reg = <0x0 0x23310000 0x0 0x1000>; 408 409 clocks = <&soc_smc50mhz>; 410 clock-names = "apb_pclk"; 411 power-domains = <&scpi_devpd 0>; 412 }; 413 414 etm5: etm@23340000 { 415 compatible = "arm,coresight-etm4x", "arm,primecell"; 416 reg = <0 0x23340000 0 0x1000>; 417 418 clocks = <&soc_smc50mhz>; 419 clock-names = "apb_pclk"; 420 power-domains = <&scpi_devpd 0>; 421 port { 422 cluster1_etm3_out_port: endpoint { 423 remote-endpoint = <&cluster1_funnel_in_port3>; 424 }; 425 }; 426 }; 427 428 replicator@20120000 { 429 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 430 reg = <0 0x20120000 0 0x1000>; 431 432 clocks = <&soc_smc50mhz>; 433 clock-names = "apb_pclk"; 434 power-domains = <&scpi_devpd 0>; 435 436 ports { 437 #address-cells = <1>; 438 #size-cells = <0>; 439 440 /* replicator output ports */ 441 port@0 { 442 reg = <0>; 443 replicator_out_port0: endpoint { 444 remote-endpoint = <&tpiu_in_port>; 445 }; 446 }; 447 448 port@1 { 449 reg = <1>; 450 replicator_out_port1: endpoint { 451 remote-endpoint = <&etr_in_port>; 452 }; 453 }; 454 455 /* replicator input port */ 456 port@2 { 457 reg = <0>; 458 replicator_in_port0: endpoint { 459 slave-mode; 460 }; 461 }; 462 }; 463 }; 464 465 sram: sram@2e000000 { 466 compatible = "arm,juno-sram-ns", "mmio-sram"; 467 reg = <0x0 0x2e000000 0x0 0x8000>; 468 469 #address-cells = <1>; 470 #size-cells = <1>; 471 ranges = <0 0x0 0x2e000000 0x8000>; 472 473 cpu_scp_lpri: scp-shmem@0 { 474 compatible = "arm,juno-scp-shmem"; 475 reg = <0x0 0x200>; 476 }; 477 478 cpu_scp_hpri: scp-shmem@200 { 479 compatible = "arm,juno-scp-shmem"; 480 reg = <0x200 0x200>; 481 }; 482 }; 483 484 pcie_ctlr: pcie@40000000 { 485 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; 486 device_type = "pci"; 487 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ 488 bus-range = <0 255>; 489 linux,pci-domain = <0>; 490 #address-cells = <3>; 491 #size-cells = <2>; 492 dma-coherent; 493 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, 494 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, 495 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; 496 #interrupt-cells = <1>; 497 interrupt-map-mask = <0 0 0 7>; 498 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>, 499 <0 0 0 2 &gic 0 0 0 137 4>, 500 <0 0 0 3 &gic 0 0 0 138 4>, 501 <0 0 0 4 &gic 0 0 0 139 4>; 502 msi-parent = <&v2m_0>; 503 status = "disabled"; 504 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ 505 iommu-map = <0x0 &smmu_pcie 0x0 0x1>; 506 }; 507 508 scpi { 509 compatible = "arm,scpi"; 510 mboxes = <&mailbox 1>; 511 shmem = <&cpu_scp_hpri>; 512 513 clocks { 514 compatible = "arm,scpi-clocks"; 515 516 scpi_dvfs: scpi-dvfs { 517 compatible = "arm,scpi-dvfs-clocks"; 518 #clock-cells = <1>; 519 clock-indices = <0>, <1>, <2>; 520 clock-output-names = "atlclk", "aplclk","gpuclk"; 521 }; 522 scpi_clk: scpi-clk { 523 compatible = "arm,scpi-variable-clocks"; 524 #clock-cells = <1>; 525 clock-indices = <3>; 526 clock-output-names = "pxlclk"; 527 }; 528 }; 529 530 scpi_devpd: scpi-power-domains { 531 compatible = "arm,scpi-power-domains"; 532 num-domains = <2>; 533 #power-domain-cells = <1>; 534 }; 535 536 scpi_sensors0: sensors { 537 compatible = "arm,scpi-sensors"; 538 #thermal-sensor-cells = <1>; 539 }; 540 }; 541 542 thermal-zones { 543 pmic { 544 polling-delay = <1000>; 545 polling-delay-passive = <100>; 546 thermal-sensors = <&scpi_sensors0 0>; 547 }; 548 549 soc { 550 polling-delay = <1000>; 551 polling-delay-passive = <100>; 552 thermal-sensors = <&scpi_sensors0 3>; 553 }; 554 555 big_cluster_thermal_zone: big_cluster { 556 polling-delay = <1000>; 557 polling-delay-passive = <100>; 558 thermal-sensors = <&scpi_sensors0 21>; 559 status = "disabled"; 560 }; 561 562 little_cluster_thermal_zone: little_cluster { 563 polling-delay = <1000>; 564 polling-delay-passive = <100>; 565 thermal-sensors = <&scpi_sensors0 22>; 566 status = "disabled"; 567 }; 568 569 gpu0_thermal_zone: gpu0 { 570 polling-delay = <1000>; 571 polling-delay-passive = <100>; 572 thermal-sensors = <&scpi_sensors0 23>; 573 status = "disabled"; 574 }; 575 576 gpu1_thermal_zone: gpu1 { 577 polling-delay = <1000>; 578 polling-delay-passive = <100>; 579 thermal-sensors = <&scpi_sensors0 24>; 580 status = "disabled"; 581 }; 582 }; 583 584 smmu_dma: iommu@7fb00000 { 585 compatible = "arm,mmu-401", "arm,smmu-v1"; 586 reg = <0x0 0x7fb00000 0x0 0x10000>; 587 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 589 #iommu-cells = <1>; 590 #global-interrupts = <1>; 591 dma-coherent; 592 status = "disabled"; 593 }; 594 595 smmu_hdlcd1: iommu@7fb10000 { 596 compatible = "arm,mmu-401", "arm,smmu-v1"; 597 reg = <0x0 0x7fb10000 0x0 0x10000>; 598 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 600 #iommu-cells = <1>; 601 #global-interrupts = <1>; 602 }; 603 604 smmu_hdlcd0: iommu@7fb20000 { 605 compatible = "arm,mmu-401", "arm,smmu-v1"; 606 reg = <0x0 0x7fb20000 0x0 0x10000>; 607 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 609 #iommu-cells = <1>; 610 #global-interrupts = <1>; 611 }; 612 613 smmu_usb: iommu@7fb30000 { 614 compatible = "arm,mmu-401", "arm,smmu-v1"; 615 reg = <0x0 0x7fb30000 0x0 0x10000>; 616 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 618 #iommu-cells = <1>; 619 #global-interrupts = <1>; 620 dma-coherent; 621 }; 622 623 dma@7ff00000 { 624 compatible = "arm,pl330", "arm,primecell"; 625 reg = <0x0 0x7ff00000 0 0x1000>; 626 #dma-cells = <1>; 627 #dma-channels = <8>; 628 #dma-requests = <32>; 629 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 638 iommus = <&smmu_dma 0>, 639 <&smmu_dma 1>, 640 <&smmu_dma 2>, 641 <&smmu_dma 3>, 642 <&smmu_dma 4>, 643 <&smmu_dma 5>, 644 <&smmu_dma 6>, 645 <&smmu_dma 7>, 646 <&smmu_dma 8>; 647 clocks = <&soc_faxiclk>; 648 clock-names = "apb_pclk"; 649 }; 650 651 hdlcd@7ff50000 { 652 compatible = "arm,hdlcd"; 653 reg = <0 0x7ff50000 0 0x1000>; 654 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 655 iommus = <&smmu_hdlcd1 0>; 656 clocks = <&scpi_clk 3>; 657 clock-names = "pxlclk"; 658 659 port { 660 hdlcd1_output: hdlcd1-endpoint { 661 remote-endpoint = <&tda998x_1_input>; 662 }; 663 }; 664 }; 665 666 hdlcd@7ff60000 { 667 compatible = "arm,hdlcd"; 668 reg = <0 0x7ff60000 0 0x1000>; 669 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 670 iommus = <&smmu_hdlcd0 0>; 671 clocks = <&scpi_clk 3>; 672 clock-names = "pxlclk"; 673 674 port { 675 hdlcd0_output: hdlcd0-endpoint { 676 remote-endpoint = <&tda998x_0_input>; 677 }; 678 }; 679 }; 680 681 soc_uart0: uart@7ff80000 { 682 compatible = "arm,pl011", "arm,primecell"; 683 reg = <0x0 0x7ff80000 0x0 0x1000>; 684 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&soc_uartclk>, <&soc_refclk100mhz>; 686 clock-names = "uartclk", "apb_pclk"; 687 }; 688 689 i2c@7ffa0000 { 690 compatible = "snps,designware-i2c"; 691 reg = <0x0 0x7ffa0000 0x0 0x1000>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 695 clock-frequency = <400000>; 696 i2c-sda-hold-time-ns = <500>; 697 clocks = <&soc_smc50mhz>; 698 699 hdmi-transmitter@70 { 700 compatible = "nxp,tda998x"; 701 reg = <0x70>; 702 port { 703 tda998x_0_input: tda998x-0-endpoint { 704 remote-endpoint = <&hdlcd0_output>; 705 }; 706 }; 707 }; 708 709 hdmi-transmitter@71 { 710 compatible = "nxp,tda998x"; 711 reg = <0x71>; 712 port { 713 tda998x_1_input: tda998x-1-endpoint { 714 remote-endpoint = <&hdlcd1_output>; 715 }; 716 }; 717 }; 718 }; 719 720 ohci@7ffb0000 { 721 compatible = "generic-ohci"; 722 reg = <0x0 0x7ffb0000 0x0 0x10000>; 723 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 724 iommus = <&smmu_usb 0>; 725 clocks = <&soc_usb48mhz>; 726 }; 727 728 ehci@7ffc0000 { 729 compatible = "generic-ehci"; 730 reg = <0x0 0x7ffc0000 0x0 0x10000>; 731 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 732 iommus = <&smmu_usb 0>; 733 clocks = <&soc_usb48mhz>; 734 }; 735 736 memory-controller@7ffd0000 { 737 compatible = "arm,pl354", "arm,primecell"; 738 reg = <0 0x7ffd0000 0 0x1000>; 739 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&soc_smc50mhz>; 742 clock-names = "apb_pclk"; 743 }; 744 745 memory@80000000 { 746 device_type = "memory"; 747 /* last 16MB of the first memory area is reserved for secure world use by firmware */ 748 reg = <0x00000000 0x80000000 0x0 0x7f000000>, 749 <0x00000008 0x80000000 0x1 0x80000000>; 750 }; 751 752 smb@8000000 { 753 compatible = "simple-bus"; 754 #address-cells = <2>; 755 #size-cells = <1>; 756 ranges = <0 0 0 0x08000000 0x04000000>, 757 <1 0 0 0x14000000 0x04000000>, 758 <2 0 0 0x18000000 0x04000000>, 759 <3 0 0 0x1c000000 0x04000000>, 760 <4 0 0 0x0c000000 0x04000000>, 761 <5 0 0 0x10000000 0x04000000>; 762 763 #interrupt-cells = <1>; 764 interrupt-map-mask = <0 0 15>; 765 interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>, 766 <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>, 767 <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, 768 <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>, 769 <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>, 770 <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>, 771 <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>, 772 <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>, 773 <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>, 774 <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>, 775 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>, 776 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>, 777 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>; 778 779 /include/ "juno-motherboard.dtsi" 780 }; 781 782 site2: tlx@60000000 { 783 compatible = "simple-bus"; 784 #address-cells = <1>; 785 #size-cells = <1>; 786 ranges = <0 0 0x60000000 0x10000000>; 787 #interrupt-cells = <1>; 788 interrupt-map-mask = <0 0>; 789 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>; 790 }; 791}; 792