1// SPDX-License-Identifier: GPL-2.0 2#include "juno-clocks.dtsi" 3#include "juno-motherboard.dtsi" 4 5/ { 6 /* 7 * Devices shared by all Juno boards 8 */ 9 dma-ranges = <0 0 0 0 0x100 0>; 10 11 memtimer: timer@2a810000 { 12 compatible = "arm,armv7-timer-mem"; 13 reg = <0x0 0x2a810000 0x0 0x10000>; 14 clock-frequency = <50000000>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 ranges; 18 status = "disabled"; 19 frame@2a830000 { 20 frame-number = <1>; 21 interrupts = <0 60 4>; 22 reg = <0x0 0x2a830000 0x0 0x10000>; 23 }; 24 }; 25 26 mailbox: mhu@2b1f0000 { 27 compatible = "arm,mhu", "arm,primecell"; 28 reg = <0x0 0x2b1f0000 0x0 0x1000>; 29 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 31 interrupt-names = "mhu_lpri_rx", 32 "mhu_hpri_rx"; 33 #mbox-cells = <1>; 34 clocks = <&soc_refclk100mhz>; 35 clock-names = "apb_pclk"; 36 }; 37 38 smmu_pcie: iommu@2b500000 { 39 compatible = "arm,mmu-401", "arm,smmu-v1"; 40 reg = <0x0 0x2b500000 0x0 0x10000>; 41 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 43 #iommu-cells = <1>; 44 #global-interrupts = <1>; 45 dma-coherent; 46 status = "disabled"; 47 }; 48 49 smmu_etr: iommu@2b600000 { 50 compatible = "arm,mmu-401", "arm,smmu-v1"; 51 reg = <0x0 0x2b600000 0x0 0x10000>; 52 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 54 #iommu-cells = <1>; 55 #global-interrupts = <1>; 56 dma-coherent; 57 power-domains = <&scpi_devpd 0>; 58 }; 59 60 gic: interrupt-controller@2c010000 { 61 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 62 reg = <0x0 0x2c010000 0 0x1000>, 63 <0x0 0x2c02f000 0 0x2000>, 64 <0x0 0x2c04f000 0 0x2000>, 65 <0x0 0x2c06f000 0 0x2000>; 66 #address-cells = <2>; 67 #interrupt-cells = <3>; 68 #size-cells = <2>; 69 interrupt-controller; 70 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 71 ranges = <0 0 0 0x2c1c0000 0 0x40000>; 72 73 v2m_0: v2m@0 { 74 compatible = "arm,gic-v2m-frame"; 75 msi-controller; 76 reg = <0 0 0 0x10000>; 77 }; 78 79 v2m@10000 { 80 compatible = "arm,gic-v2m-frame"; 81 msi-controller; 82 reg = <0 0x10000 0 0x10000>; 83 }; 84 85 v2m@20000 { 86 compatible = "arm,gic-v2m-frame"; 87 msi-controller; 88 reg = <0 0x20000 0 0x10000>; 89 }; 90 91 v2m@30000 { 92 compatible = "arm,gic-v2m-frame"; 93 msi-controller; 94 reg = <0 0x30000 0 0x10000>; 95 }; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 104 }; 105 106 /* 107 * Juno TRMs specify the size for these coresight components as 64K. 108 * The actual size is just 4K though 64K is reserved. Access to the 109 * unmapped reserved region results in a DECERR response. 110 */ 111 etf@20010000 { /* etf0 */ 112 compatible = "arm,coresight-tmc", "arm,primecell"; 113 reg = <0 0x20010000 0 0x1000>; 114 115 clocks = <&soc_smc50mhz>; 116 clock-names = "apb_pclk"; 117 power-domains = <&scpi_devpd 0>; 118 ports { 119 #address-cells = <1>; 120 #size-cells = <0>; 121 122 /* input port */ 123 port@0 { 124 reg = <0>; 125 etf0_in_port: endpoint { 126 slave-mode; 127 remote-endpoint = <&main_funnel_out_port>; 128 }; 129 }; 130 131 /* output port */ 132 port@1 { 133 reg = <0>; 134 etf0_out_port: endpoint { 135 }; 136 }; 137 }; 138 }; 139 140 tpiu@20030000 { 141 compatible = "arm,coresight-tpiu", "arm,primecell"; 142 reg = <0 0x20030000 0 0x1000>; 143 144 clocks = <&soc_smc50mhz>; 145 clock-names = "apb_pclk"; 146 power-domains = <&scpi_devpd 0>; 147 port { 148 tpiu_in_port: endpoint { 149 slave-mode; 150 remote-endpoint = <&replicator_out_port0>; 151 }; 152 }; 153 }; 154 155 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ 156 main_funnel: funnel@20040000 { 157 compatible = "arm,coresight-funnel", "arm,primecell"; 158 reg = <0 0x20040000 0 0x1000>; 159 160 clocks = <&soc_smc50mhz>; 161 clock-names = "apb_pclk"; 162 power-domains = <&scpi_devpd 0>; 163 ports { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 /* output port */ 168 port@0 { 169 reg = <0>; 170 main_funnel_out_port: endpoint { 171 remote-endpoint = <&etf0_in_port>; 172 }; 173 }; 174 175 /* input ports */ 176 port@1 { 177 reg = <0>; 178 main_funnel_in_port0: endpoint { 179 slave-mode; 180 remote-endpoint = <&cluster0_funnel_out_port>; 181 }; 182 }; 183 184 port@2 { 185 reg = <1>; 186 main_funnel_in_port1: endpoint { 187 slave-mode; 188 remote-endpoint = <&cluster1_funnel_out_port>; 189 }; 190 }; 191 }; 192 }; 193 194 etr@20070000 { 195 compatible = "arm,coresight-tmc", "arm,primecell"; 196 reg = <0 0x20070000 0 0x1000>; 197 iommus = <&smmu_etr 0>; 198 199 clocks = <&soc_smc50mhz>; 200 clock-names = "apb_pclk"; 201 power-domains = <&scpi_devpd 0>; 202 port { 203 etr_in_port: endpoint { 204 slave-mode; 205 remote-endpoint = <&replicator_out_port1>; 206 }; 207 }; 208 }; 209 210 stm@20100000 { 211 compatible = "arm,coresight-stm", "arm,primecell"; 212 reg = <0 0x20100000 0 0x1000>, 213 <0 0x28000000 0 0x1000000>; 214 reg-names = "stm-base", "stm-stimulus-base"; 215 216 clocks = <&soc_smc50mhz>; 217 clock-names = "apb_pclk"; 218 power-domains = <&scpi_devpd 0>; 219 port { 220 stm_out_port: endpoint { 221 }; 222 }; 223 }; 224 225 cpu_debug0: cpu-debug@22010000 { 226 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 227 reg = <0x0 0x22010000 0x0 0x1000>; 228 229 clocks = <&soc_smc50mhz>; 230 clock-names = "apb_pclk"; 231 power-domains = <&scpi_devpd 0>; 232 }; 233 234 etm0: etm@22040000 { 235 compatible = "arm,coresight-etm4x", "arm,primecell"; 236 reg = <0 0x22040000 0 0x1000>; 237 238 clocks = <&soc_smc50mhz>; 239 clock-names = "apb_pclk"; 240 power-domains = <&scpi_devpd 0>; 241 port { 242 cluster0_etm0_out_port: endpoint { 243 remote-endpoint = <&cluster0_funnel_in_port0>; 244 }; 245 }; 246 }; 247 248 funnel@220c0000 { /* cluster0 funnel */ 249 compatible = "arm,coresight-funnel", "arm,primecell"; 250 reg = <0 0x220c0000 0 0x1000>; 251 252 clocks = <&soc_smc50mhz>; 253 clock-names = "apb_pclk"; 254 power-domains = <&scpi_devpd 0>; 255 ports { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 259 port@0 { 260 reg = <0>; 261 cluster0_funnel_out_port: endpoint { 262 remote-endpoint = <&main_funnel_in_port0>; 263 }; 264 }; 265 266 port@1 { 267 reg = <0>; 268 cluster0_funnel_in_port0: endpoint { 269 slave-mode; 270 remote-endpoint = <&cluster0_etm0_out_port>; 271 }; 272 }; 273 274 port@2 { 275 reg = <1>; 276 cluster0_funnel_in_port1: endpoint { 277 slave-mode; 278 remote-endpoint = <&cluster0_etm1_out_port>; 279 }; 280 }; 281 }; 282 }; 283 284 cpu_debug1: cpu-debug@22110000 { 285 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 286 reg = <0x0 0x22110000 0x0 0x1000>; 287 288 clocks = <&soc_smc50mhz>; 289 clock-names = "apb_pclk"; 290 power-domains = <&scpi_devpd 0>; 291 }; 292 293 etm1: etm@22140000 { 294 compatible = "arm,coresight-etm4x", "arm,primecell"; 295 reg = <0 0x22140000 0 0x1000>; 296 297 clocks = <&soc_smc50mhz>; 298 clock-names = "apb_pclk"; 299 power-domains = <&scpi_devpd 0>; 300 port { 301 cluster0_etm1_out_port: endpoint { 302 remote-endpoint = <&cluster0_funnel_in_port1>; 303 }; 304 }; 305 }; 306 307 cpu_debug2: cpu-debug@23010000 { 308 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 309 reg = <0x0 0x23010000 0x0 0x1000>; 310 311 clocks = <&soc_smc50mhz>; 312 clock-names = "apb_pclk"; 313 power-domains = <&scpi_devpd 0>; 314 }; 315 316 etm2: etm@23040000 { 317 compatible = "arm,coresight-etm4x", "arm,primecell"; 318 reg = <0 0x23040000 0 0x1000>; 319 320 clocks = <&soc_smc50mhz>; 321 clock-names = "apb_pclk"; 322 power-domains = <&scpi_devpd 0>; 323 port { 324 cluster1_etm0_out_port: endpoint { 325 remote-endpoint = <&cluster1_funnel_in_port0>; 326 }; 327 }; 328 }; 329 330 funnel@230c0000 { /* cluster1 funnel */ 331 compatible = "arm,coresight-funnel", "arm,primecell"; 332 reg = <0 0x230c0000 0 0x1000>; 333 334 clocks = <&soc_smc50mhz>; 335 clock-names = "apb_pclk"; 336 power-domains = <&scpi_devpd 0>; 337 ports { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 341 port@0 { 342 reg = <0>; 343 cluster1_funnel_out_port: endpoint { 344 remote-endpoint = <&main_funnel_in_port1>; 345 }; 346 }; 347 348 port@1 { 349 reg = <0>; 350 cluster1_funnel_in_port0: endpoint { 351 slave-mode; 352 remote-endpoint = <&cluster1_etm0_out_port>; 353 }; 354 }; 355 356 port@2 { 357 reg = <1>; 358 cluster1_funnel_in_port1: endpoint { 359 slave-mode; 360 remote-endpoint = <&cluster1_etm1_out_port>; 361 }; 362 }; 363 port@3 { 364 reg = <2>; 365 cluster1_funnel_in_port2: endpoint { 366 slave-mode; 367 remote-endpoint = <&cluster1_etm2_out_port>; 368 }; 369 }; 370 port@4 { 371 reg = <3>; 372 cluster1_funnel_in_port3: endpoint { 373 slave-mode; 374 remote-endpoint = <&cluster1_etm3_out_port>; 375 }; 376 }; 377 }; 378 }; 379 380 cpu_debug3: cpu-debug@23110000 { 381 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 382 reg = <0x0 0x23110000 0x0 0x1000>; 383 384 clocks = <&soc_smc50mhz>; 385 clock-names = "apb_pclk"; 386 power-domains = <&scpi_devpd 0>; 387 }; 388 389 etm3: etm@23140000 { 390 compatible = "arm,coresight-etm4x", "arm,primecell"; 391 reg = <0 0x23140000 0 0x1000>; 392 393 clocks = <&soc_smc50mhz>; 394 clock-names = "apb_pclk"; 395 power-domains = <&scpi_devpd 0>; 396 port { 397 cluster1_etm1_out_port: endpoint { 398 remote-endpoint = <&cluster1_funnel_in_port1>; 399 }; 400 }; 401 }; 402 403 cpu_debug4: cpu-debug@23210000 { 404 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 405 reg = <0x0 0x23210000 0x0 0x1000>; 406 407 clocks = <&soc_smc50mhz>; 408 clock-names = "apb_pclk"; 409 power-domains = <&scpi_devpd 0>; 410 }; 411 412 etm4: etm@23240000 { 413 compatible = "arm,coresight-etm4x", "arm,primecell"; 414 reg = <0 0x23240000 0 0x1000>; 415 416 clocks = <&soc_smc50mhz>; 417 clock-names = "apb_pclk"; 418 power-domains = <&scpi_devpd 0>; 419 port { 420 cluster1_etm2_out_port: endpoint { 421 remote-endpoint = <&cluster1_funnel_in_port2>; 422 }; 423 }; 424 }; 425 426 cpu_debug5: cpu-debug@23310000 { 427 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 428 reg = <0x0 0x23310000 0x0 0x1000>; 429 430 clocks = <&soc_smc50mhz>; 431 clock-names = "apb_pclk"; 432 power-domains = <&scpi_devpd 0>; 433 }; 434 435 etm5: etm@23340000 { 436 compatible = "arm,coresight-etm4x", "arm,primecell"; 437 reg = <0 0x23340000 0 0x1000>; 438 439 clocks = <&soc_smc50mhz>; 440 clock-names = "apb_pclk"; 441 power-domains = <&scpi_devpd 0>; 442 port { 443 cluster1_etm3_out_port: endpoint { 444 remote-endpoint = <&cluster1_funnel_in_port3>; 445 }; 446 }; 447 }; 448 449 replicator@20120000 { 450 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 451 reg = <0 0x20120000 0 0x1000>; 452 453 clocks = <&soc_smc50mhz>; 454 clock-names = "apb_pclk"; 455 power-domains = <&scpi_devpd 0>; 456 457 ports { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 461 /* replicator output ports */ 462 port@0 { 463 reg = <0>; 464 replicator_out_port0: endpoint { 465 remote-endpoint = <&tpiu_in_port>; 466 }; 467 }; 468 469 port@1 { 470 reg = <1>; 471 replicator_out_port1: endpoint { 472 remote-endpoint = <&etr_in_port>; 473 }; 474 }; 475 476 /* replicator input port */ 477 port@2 { 478 reg = <0>; 479 replicator_in_port0: endpoint { 480 slave-mode; 481 }; 482 }; 483 }; 484 }; 485 486 sram: sram@2e000000 { 487 compatible = "arm,juno-sram-ns", "mmio-sram"; 488 reg = <0x0 0x2e000000 0x0 0x8000>; 489 490 #address-cells = <1>; 491 #size-cells = <1>; 492 ranges = <0 0x0 0x2e000000 0x8000>; 493 494 cpu_scp_lpri: scp-shmem@0 { 495 compatible = "arm,juno-scp-shmem"; 496 reg = <0x0 0x200>; 497 }; 498 499 cpu_scp_hpri: scp-shmem@200 { 500 compatible = "arm,juno-scp-shmem"; 501 reg = <0x200 0x200>; 502 }; 503 }; 504 505 pcie_ctlr: pcie@40000000 { 506 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; 507 device_type = "pci"; 508 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ 509 bus-range = <0 255>; 510 linux,pci-domain = <0>; 511 #address-cells = <3>; 512 #size-cells = <2>; 513 dma-coherent; 514 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, 515 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, 516 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; 517 #interrupt-cells = <1>; 518 interrupt-map-mask = <0 0 0 7>; 519 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>, 520 <0 0 0 2 &gic 0 0 0 137 4>, 521 <0 0 0 3 &gic 0 0 0 138 4>, 522 <0 0 0 4 &gic 0 0 0 139 4>; 523 msi-parent = <&v2m_0>; 524 status = "disabled"; 525 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ 526 iommu-map = <0x0 &smmu_pcie 0x0 0x1>; 527 }; 528 529 scpi { 530 compatible = "arm,scpi"; 531 mboxes = <&mailbox 1>; 532 shmem = <&cpu_scp_hpri>; 533 534 clocks { 535 compatible = "arm,scpi-clocks"; 536 537 scpi_dvfs: scpi-dvfs { 538 compatible = "arm,scpi-dvfs-clocks"; 539 #clock-cells = <1>; 540 clock-indices = <0>, <1>, <2>; 541 clock-output-names = "atlclk", "aplclk","gpuclk"; 542 }; 543 scpi_clk: scpi-clk { 544 compatible = "arm,scpi-variable-clocks"; 545 #clock-cells = <1>; 546 clock-indices = <3>; 547 clock-output-names = "pxlclk"; 548 }; 549 }; 550 551 scpi_devpd: scpi-power-domains { 552 compatible = "arm,scpi-power-domains"; 553 num-domains = <2>; 554 #power-domain-cells = <1>; 555 }; 556 557 scpi_sensors0: sensors { 558 compatible = "arm,scpi-sensors"; 559 #thermal-sensor-cells = <1>; 560 }; 561 }; 562 563 thermal-zones { 564 pmic { 565 polling-delay = <1000>; 566 polling-delay-passive = <100>; 567 thermal-sensors = <&scpi_sensors0 0>; 568 }; 569 570 soc { 571 polling-delay = <1000>; 572 polling-delay-passive = <100>; 573 thermal-sensors = <&scpi_sensors0 3>; 574 }; 575 576 big_cluster_thermal_zone: big-cluster { 577 polling-delay = <1000>; 578 polling-delay-passive = <100>; 579 thermal-sensors = <&scpi_sensors0 21>; 580 status = "disabled"; 581 }; 582 583 little_cluster_thermal_zone: little-cluster { 584 polling-delay = <1000>; 585 polling-delay-passive = <100>; 586 thermal-sensors = <&scpi_sensors0 22>; 587 status = "disabled"; 588 }; 589 590 gpu0_thermal_zone: gpu0 { 591 polling-delay = <1000>; 592 polling-delay-passive = <100>; 593 thermal-sensors = <&scpi_sensors0 23>; 594 status = "disabled"; 595 }; 596 597 gpu1_thermal_zone: gpu1 { 598 polling-delay = <1000>; 599 polling-delay-passive = <100>; 600 thermal-sensors = <&scpi_sensors0 24>; 601 status = "disabled"; 602 }; 603 }; 604 605 smmu_dma: iommu@7fb00000 { 606 compatible = "arm,mmu-401", "arm,smmu-v1"; 607 reg = <0x0 0x7fb00000 0x0 0x10000>; 608 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 610 #iommu-cells = <1>; 611 #global-interrupts = <1>; 612 dma-coherent; 613 status = "disabled"; 614 }; 615 616 smmu_hdlcd1: iommu@7fb10000 { 617 compatible = "arm,mmu-401", "arm,smmu-v1"; 618 reg = <0x0 0x7fb10000 0x0 0x10000>; 619 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 621 #iommu-cells = <1>; 622 #global-interrupts = <1>; 623 }; 624 625 smmu_hdlcd0: iommu@7fb20000 { 626 compatible = "arm,mmu-401", "arm,smmu-v1"; 627 reg = <0x0 0x7fb20000 0x0 0x10000>; 628 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 630 #iommu-cells = <1>; 631 #global-interrupts = <1>; 632 }; 633 634 smmu_usb: iommu@7fb30000 { 635 compatible = "arm,mmu-401", "arm,smmu-v1"; 636 reg = <0x0 0x7fb30000 0x0 0x10000>; 637 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 639 #iommu-cells = <1>; 640 #global-interrupts = <1>; 641 dma-coherent; 642 }; 643 644 dma@7ff00000 { 645 compatible = "arm,pl330", "arm,primecell"; 646 reg = <0x0 0x7ff00000 0 0x1000>; 647 #dma-cells = <1>; 648 #dma-channels = <8>; 649 #dma-requests = <32>; 650 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 659 iommus = <&smmu_dma 0>, 660 <&smmu_dma 1>, 661 <&smmu_dma 2>, 662 <&smmu_dma 3>, 663 <&smmu_dma 4>, 664 <&smmu_dma 5>, 665 <&smmu_dma 6>, 666 <&smmu_dma 7>, 667 <&smmu_dma 8>; 668 clocks = <&soc_faxiclk>; 669 clock-names = "apb_pclk"; 670 }; 671 672 hdlcd@7ff50000 { 673 compatible = "arm,hdlcd"; 674 reg = <0 0x7ff50000 0 0x1000>; 675 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 676 iommus = <&smmu_hdlcd1 0>; 677 clocks = <&scpi_clk 3>; 678 clock-names = "pxlclk"; 679 680 port { 681 hdlcd1_output: endpoint { 682 remote-endpoint = <&tda998x_1_input>; 683 }; 684 }; 685 }; 686 687 hdlcd@7ff60000 { 688 compatible = "arm,hdlcd"; 689 reg = <0 0x7ff60000 0 0x1000>; 690 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 691 iommus = <&smmu_hdlcd0 0>; 692 clocks = <&scpi_clk 3>; 693 clock-names = "pxlclk"; 694 695 port { 696 hdlcd0_output: endpoint { 697 remote-endpoint = <&tda998x_0_input>; 698 }; 699 }; 700 }; 701 702 soc_uart0: uart@7ff80000 { 703 compatible = "arm,pl011", "arm,primecell"; 704 reg = <0x0 0x7ff80000 0x0 0x1000>; 705 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&soc_uartclk>, <&soc_refclk100mhz>; 707 clock-names = "uartclk", "apb_pclk"; 708 }; 709 710 i2c@7ffa0000 { 711 compatible = "snps,designware-i2c"; 712 reg = <0x0 0x7ffa0000 0x0 0x1000>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 716 clock-frequency = <400000>; 717 i2c-sda-hold-time-ns = <500>; 718 clocks = <&soc_smc50mhz>; 719 720 hdmi-transmitter@70 { 721 compatible = "nxp,tda998x"; 722 reg = <0x70>; 723 port { 724 tda998x_0_input: endpoint { 725 remote-endpoint = <&hdlcd0_output>; 726 }; 727 }; 728 }; 729 730 hdmi-transmitter@71 { 731 compatible = "nxp,tda998x"; 732 reg = <0x71>; 733 port { 734 tda998x_1_input: endpoint { 735 remote-endpoint = <&hdlcd1_output>; 736 }; 737 }; 738 }; 739 }; 740 741 ohci@7ffb0000 { 742 compatible = "generic-ohci"; 743 reg = <0x0 0x7ffb0000 0x0 0x10000>; 744 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 745 iommus = <&smmu_usb 0>; 746 clocks = <&soc_usb48mhz>; 747 }; 748 749 ehci@7ffc0000 { 750 compatible = "generic-ehci"; 751 reg = <0x0 0x7ffc0000 0x0 0x10000>; 752 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 753 iommus = <&smmu_usb 0>; 754 clocks = <&soc_usb48mhz>; 755 }; 756 757 memory-controller@7ffd0000 { 758 compatible = "arm,pl354", "arm,primecell"; 759 reg = <0 0x7ffd0000 0 0x1000>; 760 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&soc_smc50mhz>; 763 clock-names = "apb_pclk"; 764 }; 765 766 memory@80000000 { 767 device_type = "memory"; 768 /* last 16MB of the first memory area is reserved for secure world use by firmware */ 769 reg = <0x00000000 0x80000000 0x0 0x7f000000>, 770 <0x00000008 0x80000000 0x1 0x80000000>; 771 }; 772 773 smb@8000000 { 774 compatible = "simple-bus"; 775 #address-cells = <2>; 776 #size-cells = <1>; 777 ranges = <0 0 0 0x08000000 0x04000000>, 778 <1 0 0 0x14000000 0x04000000>, 779 <2 0 0 0x18000000 0x04000000>, 780 <3 0 0 0x1c000000 0x04000000>, 781 <4 0 0 0x0c000000 0x04000000>, 782 <5 0 0 0x10000000 0x04000000>; 783 784 #interrupt-cells = <1>; 785 interrupt-map-mask = <0 0 15>; 786 interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>, 787 <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>, 788 <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, 789 <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>, 790 <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>, 791 <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>, 792 <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>, 793 <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>, 794 <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>, 795 <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>, 796 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>, 797 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>, 798 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>; 799 }; 800 801 site2: tlx@60000000 { 802 compatible = "simple-bus"; 803 #address-cells = <1>; 804 #size-cells = <1>; 805 ranges = <0 0 0x60000000 0x10000000>; 806 #interrupt-cells = <1>; 807 interrupt-map-mask = <0 0>; 808 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>; 809 }; 810}; 811