1// SPDX-License-Identifier: GPL-2.0 2#include "juno-clocks.dtsi" 3#include "juno-motherboard.dtsi" 4 5/ { 6 /* 7 * Devices shared by all Juno boards 8 */ 9 10 memtimer: timer@2a810000 { 11 compatible = "arm,armv7-timer-mem"; 12 reg = <0x0 0x2a810000 0x0 0x10000>; 13 clock-frequency = <50000000>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = <0 0x0 0x2a820000 0x20000>; 17 status = "disabled"; 18 frame@2a830000 { 19 frame-number = <1>; 20 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 21 reg = <0x10000 0x10000>; 22 }; 23 }; 24 25 mailbox: mhu@2b1f0000 { 26 compatible = "arm,mhu", "arm,primecell"; 27 reg = <0x0 0x2b1f0000 0x0 0x1000>; 28 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 30 #mbox-cells = <1>; 31 clocks = <&soc_refclk100mhz>; 32 clock-names = "apb_pclk"; 33 }; 34 35 smmu_gpu: iommu@2b400000 { 36 compatible = "arm,mmu-400", "arm,smmu-v1"; 37 reg = <0x0 0x2b400000 0x0 0x10000>; 38 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 40 #iommu-cells = <1>; 41 #global-interrupts = <1>; 42 power-domains = <&scpi_devpd 1>; 43 dma-coherent; 44 status = "disabled"; 45 }; 46 47 smmu_pcie: iommu@2b500000 { 48 compatible = "arm,mmu-401", "arm,smmu-v1"; 49 reg = <0x0 0x2b500000 0x0 0x10000>; 50 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 52 #iommu-cells = <1>; 53 #global-interrupts = <1>; 54 dma-coherent; 55 status = "disabled"; 56 }; 57 58 smmu_etr: iommu@2b600000 { 59 compatible = "arm,mmu-401", "arm,smmu-v1"; 60 reg = <0x0 0x2b600000 0x0 0x10000>; 61 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 63 #iommu-cells = <1>; 64 #global-interrupts = <1>; 65 dma-coherent; 66 power-domains = <&scpi_devpd 0>; 67 }; 68 69 gic: interrupt-controller@2c010000 { 70 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 71 reg = <0x0 0x2c010000 0 0x1000>, 72 <0x0 0x2c02f000 0 0x2000>, 73 <0x0 0x2c04f000 0 0x2000>, 74 <0x0 0x2c06f000 0 0x2000>; 75 #address-cells = <1>; 76 #interrupt-cells = <3>; 77 #size-cells = <1>; 78 interrupt-controller; 79 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 80 ranges = <0 0 0x2c1c0000 0x40000>; 81 82 v2m_0: v2m@0 { 83 compatible = "arm,gic-v2m-frame"; 84 msi-controller; 85 reg = <0 0x10000>; 86 }; 87 88 v2m@10000 { 89 compatible = "arm,gic-v2m-frame"; 90 msi-controller; 91 reg = <0x10000 0x10000>; 92 }; 93 94 v2m@20000 { 95 compatible = "arm,gic-v2m-frame"; 96 msi-controller; 97 reg = <0x20000 0x10000>; 98 }; 99 100 v2m@30000 { 101 compatible = "arm,gic-v2m-frame"; 102 msi-controller; 103 reg = <0x30000 0x10000>; 104 }; 105 }; 106 107 timer { 108 compatible = "arm,armv8-timer"; 109 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 110 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 111 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 112 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 113 }; 114 115 /* 116 * Juno TRMs specify the size for these coresight components as 64K. 117 * The actual size is just 4K though 64K is reserved. Access to the 118 * unmapped reserved region results in a DECERR response. 119 */ 120 etf@20010000 { /* etf0 */ 121 compatible = "arm,coresight-tmc", "arm,primecell"; 122 reg = <0 0x20010000 0 0x1000>; 123 124 clocks = <&soc_smc50mhz>; 125 clock-names = "apb_pclk"; 126 power-domains = <&scpi_devpd 0>; 127 128 in-ports { 129 port { 130 etf0_in_port: endpoint { 131 remote-endpoint = <&main_funnel_out_port>; 132 }; 133 }; 134 }; 135 136 out-ports { 137 port { 138 etf0_out_port: endpoint { 139 }; 140 }; 141 }; 142 }; 143 144 tpiu@20030000 { 145 compatible = "arm,coresight-tpiu", "arm,primecell"; 146 reg = <0 0x20030000 0 0x1000>; 147 148 clocks = <&soc_smc50mhz>; 149 clock-names = "apb_pclk"; 150 power-domains = <&scpi_devpd 0>; 151 in-ports { 152 port { 153 tpiu_in_port: endpoint { 154 remote-endpoint = <&replicator_out_port0>; 155 }; 156 }; 157 }; 158 }; 159 160 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ 161 main_funnel: funnel@20040000 { 162 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 163 reg = <0 0x20040000 0 0x1000>; 164 165 clocks = <&soc_smc50mhz>; 166 clock-names = "apb_pclk"; 167 power-domains = <&scpi_devpd 0>; 168 169 out-ports { 170 port { 171 main_funnel_out_port: endpoint { 172 remote-endpoint = <&etf0_in_port>; 173 }; 174 }; 175 }; 176 177 main_funnel_in_ports: in-ports { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 181 port@0 { 182 reg = <0>; 183 main_funnel_in_port0: endpoint { 184 remote-endpoint = <&cluster0_funnel_out_port>; 185 }; 186 }; 187 188 port@1 { 189 reg = <1>; 190 main_funnel_in_port1: endpoint { 191 remote-endpoint = <&cluster1_funnel_out_port>; 192 }; 193 }; 194 }; 195 }; 196 197 etr@20070000 { 198 compatible = "arm,coresight-tmc", "arm,primecell"; 199 reg = <0 0x20070000 0 0x1000>; 200 iommus = <&smmu_etr 0>; 201 202 clocks = <&soc_smc50mhz>; 203 clock-names = "apb_pclk"; 204 power-domains = <&scpi_devpd 0>; 205 arm,scatter-gather; 206 in-ports { 207 port { 208 etr_in_port: endpoint { 209 remote-endpoint = <&replicator_out_port1>; 210 }; 211 }; 212 }; 213 }; 214 215 stm@20100000 { 216 compatible = "arm,coresight-stm", "arm,primecell"; 217 reg = <0 0x20100000 0 0x1000>, 218 <0 0x28000000 0 0x1000000>; 219 reg-names = "stm-base", "stm-stimulus-base"; 220 221 clocks = <&soc_smc50mhz>; 222 clock-names = "apb_pclk"; 223 power-domains = <&scpi_devpd 0>; 224 out-ports { 225 port { 226 stm_out_port: endpoint { 227 }; 228 }; 229 }; 230 }; 231 232 replicator@20120000 { 233 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 234 reg = <0 0x20120000 0 0x1000>; 235 236 clocks = <&soc_smc50mhz>; 237 clock-names = "apb_pclk"; 238 power-domains = <&scpi_devpd 0>; 239 240 out-ports { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 244 /* replicator output ports */ 245 port@0 { 246 reg = <0>; 247 replicator_out_port0: endpoint { 248 remote-endpoint = <&tpiu_in_port>; 249 }; 250 }; 251 252 port@1 { 253 reg = <1>; 254 replicator_out_port1: endpoint { 255 remote-endpoint = <&etr_in_port>; 256 }; 257 }; 258 }; 259 in-ports { 260 port { 261 replicator_in_port0: endpoint { 262 }; 263 }; 264 }; 265 }; 266 267 cpu_debug0: cpu-debug@22010000 { 268 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 269 reg = <0x0 0x22010000 0x0 0x1000>; 270 271 clocks = <&soc_smc50mhz>; 272 clock-names = "apb_pclk"; 273 power-domains = <&scpi_devpd 0>; 274 }; 275 276 etm0: etm@22040000 { 277 compatible = "arm,coresight-etm4x", "arm,primecell"; 278 reg = <0 0x22040000 0 0x1000>; 279 280 clocks = <&soc_smc50mhz>; 281 clock-names = "apb_pclk"; 282 power-domains = <&scpi_devpd 0>; 283 out-ports { 284 port { 285 cluster0_etm0_out_port: endpoint { 286 remote-endpoint = <&cluster0_funnel_in_port0>; 287 }; 288 }; 289 }; 290 }; 291 292 funnel@220c0000 { /* cluster0 funnel */ 293 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 294 reg = <0 0x220c0000 0 0x1000>; 295 296 clocks = <&soc_smc50mhz>; 297 clock-names = "apb_pclk"; 298 power-domains = <&scpi_devpd 0>; 299 out-ports { 300 port { 301 cluster0_funnel_out_port: endpoint { 302 remote-endpoint = <&main_funnel_in_port0>; 303 }; 304 }; 305 }; 306 307 in-ports { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 311 port@0 { 312 reg = <0>; 313 cluster0_funnel_in_port0: endpoint { 314 remote-endpoint = <&cluster0_etm0_out_port>; 315 }; 316 }; 317 318 port@1 { 319 reg = <1>; 320 cluster0_funnel_in_port1: endpoint { 321 remote-endpoint = <&cluster0_etm1_out_port>; 322 }; 323 }; 324 }; 325 }; 326 327 cpu_debug1: cpu-debug@22110000 { 328 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 329 reg = <0x0 0x22110000 0x0 0x1000>; 330 331 clocks = <&soc_smc50mhz>; 332 clock-names = "apb_pclk"; 333 power-domains = <&scpi_devpd 0>; 334 }; 335 336 etm1: etm@22140000 { 337 compatible = "arm,coresight-etm4x", "arm,primecell"; 338 reg = <0 0x22140000 0 0x1000>; 339 340 clocks = <&soc_smc50mhz>; 341 clock-names = "apb_pclk"; 342 power-domains = <&scpi_devpd 0>; 343 out-ports { 344 port { 345 cluster0_etm1_out_port: endpoint { 346 remote-endpoint = <&cluster0_funnel_in_port1>; 347 }; 348 }; 349 }; 350 }; 351 352 cpu_debug2: cpu-debug@23010000 { 353 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 354 reg = <0x0 0x23010000 0x0 0x1000>; 355 356 clocks = <&soc_smc50mhz>; 357 clock-names = "apb_pclk"; 358 power-domains = <&scpi_devpd 0>; 359 }; 360 361 etm2: etm@23040000 { 362 compatible = "arm,coresight-etm4x", "arm,primecell"; 363 reg = <0 0x23040000 0 0x1000>; 364 365 clocks = <&soc_smc50mhz>; 366 clock-names = "apb_pclk"; 367 power-domains = <&scpi_devpd 0>; 368 out-ports { 369 port { 370 cluster1_etm0_out_port: endpoint { 371 remote-endpoint = <&cluster1_funnel_in_port0>; 372 }; 373 }; 374 }; 375 }; 376 377 funnel@230c0000 { /* cluster1 funnel */ 378 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 379 reg = <0 0x230c0000 0 0x1000>; 380 381 clocks = <&soc_smc50mhz>; 382 clock-names = "apb_pclk"; 383 power-domains = <&scpi_devpd 0>; 384 out-ports { 385 port { 386 cluster1_funnel_out_port: endpoint { 387 remote-endpoint = <&main_funnel_in_port1>; 388 }; 389 }; 390 }; 391 392 in-ports { 393 #address-cells = <1>; 394 #size-cells = <0>; 395 396 port@0 { 397 reg = <0>; 398 cluster1_funnel_in_port0: endpoint { 399 remote-endpoint = <&cluster1_etm0_out_port>; 400 }; 401 }; 402 403 port@1 { 404 reg = <1>; 405 cluster1_funnel_in_port1: endpoint { 406 remote-endpoint = <&cluster1_etm1_out_port>; 407 }; 408 }; 409 port@2 { 410 reg = <2>; 411 cluster1_funnel_in_port2: endpoint { 412 remote-endpoint = <&cluster1_etm2_out_port>; 413 }; 414 }; 415 port@3 { 416 reg = <3>; 417 cluster1_funnel_in_port3: endpoint { 418 remote-endpoint = <&cluster1_etm3_out_port>; 419 }; 420 }; 421 }; 422 }; 423 424 cpu_debug3: cpu-debug@23110000 { 425 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 426 reg = <0x0 0x23110000 0x0 0x1000>; 427 428 clocks = <&soc_smc50mhz>; 429 clock-names = "apb_pclk"; 430 power-domains = <&scpi_devpd 0>; 431 }; 432 433 etm3: etm@23140000 { 434 compatible = "arm,coresight-etm4x", "arm,primecell"; 435 reg = <0 0x23140000 0 0x1000>; 436 437 clocks = <&soc_smc50mhz>; 438 clock-names = "apb_pclk"; 439 power-domains = <&scpi_devpd 0>; 440 out-ports { 441 port { 442 cluster1_etm1_out_port: endpoint { 443 remote-endpoint = <&cluster1_funnel_in_port1>; 444 }; 445 }; 446 }; 447 }; 448 449 cpu_debug4: cpu-debug@23210000 { 450 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 451 reg = <0x0 0x23210000 0x0 0x1000>; 452 453 clocks = <&soc_smc50mhz>; 454 clock-names = "apb_pclk"; 455 power-domains = <&scpi_devpd 0>; 456 }; 457 458 etm4: etm@23240000 { 459 compatible = "arm,coresight-etm4x", "arm,primecell"; 460 reg = <0 0x23240000 0 0x1000>; 461 462 clocks = <&soc_smc50mhz>; 463 clock-names = "apb_pclk"; 464 power-domains = <&scpi_devpd 0>; 465 out-ports { 466 port { 467 cluster1_etm2_out_port: endpoint { 468 remote-endpoint = <&cluster1_funnel_in_port2>; 469 }; 470 }; 471 }; 472 }; 473 474 cpu_debug5: cpu-debug@23310000 { 475 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 476 reg = <0x0 0x23310000 0x0 0x1000>; 477 478 clocks = <&soc_smc50mhz>; 479 clock-names = "apb_pclk"; 480 power-domains = <&scpi_devpd 0>; 481 }; 482 483 etm5: etm@23340000 { 484 compatible = "arm,coresight-etm4x", "arm,primecell"; 485 reg = <0 0x23340000 0 0x1000>; 486 487 clocks = <&soc_smc50mhz>; 488 clock-names = "apb_pclk"; 489 power-domains = <&scpi_devpd 0>; 490 out-ports { 491 port { 492 cluster1_etm3_out_port: endpoint { 493 remote-endpoint = <&cluster1_funnel_in_port3>; 494 }; 495 }; 496 }; 497 }; 498 499 gpu: gpu@2d000000 { 500 compatible = "arm,juno-mali", "arm,mali-t624"; 501 reg = <0 0x2d000000 0 0x10000>; 502 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "job", "mmu", "gpu"; 506 clocks = <&scpi_dvfs 2>; 507 power-domains = <&scpi_devpd 1>; 508 dma-coherent; 509 /* The SMMU is only really of interest to bare-metal hypervisors */ 510 /* iommus = <&smmu_gpu 0>; */ 511 status = "disabled"; 512 }; 513 514 sram: sram@2e000000 { 515 compatible = "arm,juno-sram-ns", "mmio-sram"; 516 reg = <0x0 0x2e000000 0x0 0x8000>; 517 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges = <0 0x0 0x2e000000 0x8000>; 521 522 cpu_scp_lpri: scp-sram@0 { 523 compatible = "arm,juno-scp-shmem"; 524 reg = <0x0 0x200>; 525 }; 526 527 cpu_scp_hpri: scp-sram@200 { 528 compatible = "arm,juno-scp-shmem"; 529 reg = <0x200 0x200>; 530 }; 531 }; 532 533 pcie_ctlr: pcie@40000000 { 534 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; 535 device_type = "pci"; 536 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ 537 bus-range = <0 255>; 538 linux,pci-domain = <0>; 539 #address-cells = <3>; 540 #size-cells = <2>; 541 dma-coherent; 542 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, 543 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, 544 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; 545 /* Standard AXI Translation entries as programmed by EDK2 */ 546 dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>, 547 <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>; 548 #interrupt-cells = <1>; 549 interrupt-map-mask = <0 0 0 7>; 550 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 551 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 552 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 553 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 554 msi-parent = <&v2m_0>; 555 status = "disabled"; 556 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ 557 iommu-map = <0x0 &smmu_pcie 0x0 0x1>; 558 }; 559 560 scpi { 561 compatible = "arm,scpi"; 562 mboxes = <&mailbox 1>; 563 shmem = <&cpu_scp_hpri>; 564 565 clocks { 566 compatible = "arm,scpi-clocks"; 567 568 scpi_dvfs: clocks-0 { 569 compatible = "arm,scpi-dvfs-clocks"; 570 #clock-cells = <1>; 571 clock-indices = <0>, <1>, <2>; 572 clock-output-names = "atlclk", "aplclk","gpuclk"; 573 }; 574 scpi_clk: clocks-1 { 575 compatible = "arm,scpi-variable-clocks"; 576 #clock-cells = <1>; 577 clock-indices = <3>; 578 clock-output-names = "pxlclk"; 579 }; 580 }; 581 582 scpi_devpd: power-controller { 583 compatible = "arm,scpi-power-domains"; 584 num-domains = <2>; 585 #power-domain-cells = <1>; 586 }; 587 588 scpi_sensors0: sensors { 589 compatible = "arm,scpi-sensors"; 590 #thermal-sensor-cells = <1>; 591 }; 592 }; 593 594 thermal-zones { 595 pmic { 596 polling-delay = <1000>; 597 polling-delay-passive = <100>; 598 thermal-sensors = <&scpi_sensors0 0>; 599 }; 600 601 soc { 602 polling-delay = <1000>; 603 polling-delay-passive = <100>; 604 thermal-sensors = <&scpi_sensors0 3>; 605 }; 606 607 big_cluster_thermal_zone: big-cluster { 608 polling-delay = <1000>; 609 polling-delay-passive = <100>; 610 thermal-sensors = <&scpi_sensors0 21>; 611 status = "disabled"; 612 }; 613 614 little_cluster_thermal_zone: little-cluster { 615 polling-delay = <1000>; 616 polling-delay-passive = <100>; 617 thermal-sensors = <&scpi_sensors0 22>; 618 status = "disabled"; 619 }; 620 621 gpu0_thermal_zone: gpu0 { 622 polling-delay = <1000>; 623 polling-delay-passive = <100>; 624 thermal-sensors = <&scpi_sensors0 23>; 625 status = "disabled"; 626 }; 627 628 gpu1_thermal_zone: gpu1 { 629 polling-delay = <1000>; 630 polling-delay-passive = <100>; 631 thermal-sensors = <&scpi_sensors0 24>; 632 status = "disabled"; 633 }; 634 }; 635 636 smmu_dma: iommu@7fb00000 { 637 compatible = "arm,mmu-401", "arm,smmu-v1"; 638 reg = <0x0 0x7fb00000 0x0 0x10000>; 639 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 641 #iommu-cells = <1>; 642 #global-interrupts = <1>; 643 dma-coherent; 644 }; 645 646 smmu_hdlcd1: iommu@7fb10000 { 647 compatible = "arm,mmu-401", "arm,smmu-v1"; 648 reg = <0x0 0x7fb10000 0x0 0x10000>; 649 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 651 #iommu-cells = <1>; 652 #global-interrupts = <1>; 653 }; 654 655 smmu_hdlcd0: iommu@7fb20000 { 656 compatible = "arm,mmu-401", "arm,smmu-v1"; 657 reg = <0x0 0x7fb20000 0x0 0x10000>; 658 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 660 #iommu-cells = <1>; 661 #global-interrupts = <1>; 662 }; 663 664 smmu_usb: iommu@7fb30000 { 665 compatible = "arm,mmu-401", "arm,smmu-v1"; 666 reg = <0x0 0x7fb30000 0x0 0x10000>; 667 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 669 #iommu-cells = <1>; 670 #global-interrupts = <1>; 671 dma-coherent; 672 }; 673 674 dma-controller@7ff00000 { 675 compatible = "arm,pl330", "arm,primecell"; 676 reg = <0x0 0x7ff00000 0 0x1000>; 677 #dma-cells = <1>; 678 #dma-channels = <8>; 679 #dma-requests = <32>; 680 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 689 iommus = <&smmu_dma 0>, 690 <&smmu_dma 1>, 691 <&smmu_dma 2>, 692 <&smmu_dma 3>, 693 <&smmu_dma 4>, 694 <&smmu_dma 5>, 695 <&smmu_dma 6>, 696 <&smmu_dma 7>, 697 <&smmu_dma 8>; 698 clocks = <&soc_faxiclk>; 699 clock-names = "apb_pclk"; 700 }; 701 702 hdlcd@7ff50000 { 703 compatible = "arm,hdlcd"; 704 reg = <0 0x7ff50000 0 0x1000>; 705 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 706 iommus = <&smmu_hdlcd1 0>; 707 clocks = <&scpi_clk 3>; 708 clock-names = "pxlclk"; 709 710 port { 711 hdlcd1_output: endpoint { 712 remote-endpoint = <&tda998x_1_input>; 713 }; 714 }; 715 }; 716 717 hdlcd@7ff60000 { 718 compatible = "arm,hdlcd"; 719 reg = <0 0x7ff60000 0 0x1000>; 720 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 721 iommus = <&smmu_hdlcd0 0>; 722 clocks = <&scpi_clk 3>; 723 clock-names = "pxlclk"; 724 725 port { 726 hdlcd0_output: endpoint { 727 remote-endpoint = <&tda998x_0_input>; 728 }; 729 }; 730 }; 731 732 soc_uart0: serial@7ff80000 { 733 compatible = "arm,pl011", "arm,primecell"; 734 reg = <0x0 0x7ff80000 0x0 0x1000>; 735 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&soc_uartclk>, <&soc_refclk100mhz>; 737 clock-names = "uartclk", "apb_pclk"; 738 }; 739 740 i2c@7ffa0000 { 741 compatible = "snps,designware-i2c"; 742 reg = <0x0 0x7ffa0000 0x0 0x1000>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 746 clock-frequency = <400000>; 747 i2c-sda-hold-time-ns = <500>; 748 clocks = <&soc_smc50mhz>; 749 750 hdmi-transmitter@70 { 751 compatible = "nxp,tda998x"; 752 reg = <0x70>; 753 port { 754 tda998x_0_input: endpoint { 755 remote-endpoint = <&hdlcd0_output>; 756 }; 757 }; 758 }; 759 760 hdmi-transmitter@71 { 761 compatible = "nxp,tda998x"; 762 reg = <0x71>; 763 port { 764 tda998x_1_input: endpoint { 765 remote-endpoint = <&hdlcd1_output>; 766 }; 767 }; 768 }; 769 }; 770 771 usb@7ffb0000 { 772 compatible = "generic-ohci"; 773 reg = <0x0 0x7ffb0000 0x0 0x10000>; 774 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 775 iommus = <&smmu_usb 0>; 776 clocks = <&soc_usb48mhz>; 777 }; 778 779 usb@7ffc0000 { 780 compatible = "generic-ehci"; 781 reg = <0x0 0x7ffc0000 0x0 0x10000>; 782 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 783 iommus = <&smmu_usb 0>; 784 clocks = <&soc_usb48mhz>; 785 }; 786 787 memory-controller@7ffd0000 { 788 compatible = "arm,pl354", "arm,primecell"; 789 reg = <0 0x7ffd0000 0 0x1000>; 790 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&soc_smc50mhz>; 793 clock-names = "apb_pclk"; 794 }; 795 796 memory@80000000 { 797 device_type = "memory"; 798 /* last 16MB of the first memory area is reserved for secure world use by firmware */ 799 reg = <0x00000000 0x80000000 0x0 0x7f000000>, 800 <0x00000008 0x80000000 0x1 0x80000000>; 801 }; 802 803 bus@8000000 { 804 #interrupt-cells = <1>; 805 interrupt-map-mask = <0 0 15>; 806 interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 807 <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 808 <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 809 <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 810 <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 811 <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 812 <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 813 <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 814 <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 815 <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 816 <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 817 <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 818 <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 819 }; 820 821 site2: tlx-bus@60000000 { 822 compatible = "simple-bus"; 823 #address-cells = <1>; 824 #size-cells = <1>; 825 ranges = <0 0 0x60000000 0x10000000>; 826 #interrupt-cells = <1>; 827 interrupt-map-mask = <0 0>; 828 interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 829 }; 830}; 831