1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Fast Models
4 *
5 * Architecture Envelope Model (AEM) ARMv8-A
6 * ARMAEMv8AMPCT
7 *
8 * FVP Base RevC
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15/memreserve/ 0x80000000 0x00010000;
16
17#include "rtsm_ve-motherboard.dtsi"
18#include "rtsm_ve-motherboard-rs2.dtsi"
19
20/ {
21	model = "FVP Base RevC";
22	compatible = "arm,fvp-base-revc", "arm,vexpress";
23	interrupt-parent = <&gic>;
24	#address-cells = <2>;
25	#size-cells = <2>;
26
27	chosen { };
28
29	aliases {
30		serial0 = &v2m_serial0;
31		serial1 = &v2m_serial1;
32		serial2 = &v2m_serial2;
33		serial3 = &v2m_serial3;
34	};
35
36	psci {
37		compatible = "arm,psci-0.2";
38		method = "smc";
39	};
40
41	cpus {
42		#address-cells = <2>;
43		#size-cells = <0>;
44
45		cpu0: cpu@0 {
46			device_type = "cpu";
47			compatible = "arm,armv8";
48			reg = <0x0 0x000>;
49			enable-method = "psci";
50		};
51		cpu1: cpu@100 {
52			device_type = "cpu";
53			compatible = "arm,armv8";
54			reg = <0x0 0x100>;
55			enable-method = "psci";
56		};
57		cpu2: cpu@200 {
58			device_type = "cpu";
59			compatible = "arm,armv8";
60			reg = <0x0 0x200>;
61			enable-method = "psci";
62		};
63		cpu3: cpu@300 {
64			device_type = "cpu";
65			compatible = "arm,armv8";
66			reg = <0x0 0x300>;
67			enable-method = "psci";
68		};
69		cpu4: cpu@10000 {
70			device_type = "cpu";
71			compatible = "arm,armv8";
72			reg = <0x0 0x10000>;
73			enable-method = "psci";
74		};
75		cpu5: cpu@10100 {
76			device_type = "cpu";
77			compatible = "arm,armv8";
78			reg = <0x0 0x10100>;
79			enable-method = "psci";
80		};
81		cpu6: cpu@10200 {
82			device_type = "cpu";
83			compatible = "arm,armv8";
84			reg = <0x0 0x10200>;
85			enable-method = "psci";
86		};
87		cpu7: cpu@10300 {
88			device_type = "cpu";
89			compatible = "arm,armv8";
90			reg = <0x0 0x10300>;
91			enable-method = "psci";
92		};
93	};
94
95	memory@80000000 {
96		device_type = "memory";
97		reg = <0x00000000 0x80000000 0 0x80000000>,
98		      <0x00000008 0x80000000 0 0x80000000>;
99	};
100
101	reserved-memory {
102		#address-cells = <2>;
103		#size-cells = <2>;
104		ranges;
105
106		/* Chipselect 2,00000000 is physically at 0x18000000 */
107		vram: vram@18000000 {
108			/* 8 MB of designated video RAM */
109			compatible = "shared-dma-pool";
110			reg = <0x00000000 0x18000000 0 0x00800000>;
111			no-map;
112		};
113	};
114
115	gic: interrupt-controller@2f000000 {
116		compatible = "arm,gic-v3";
117		#interrupt-cells = <3>;
118		#address-cells = <2>;
119		#size-cells = <2>;
120		ranges;
121		interrupt-controller;
122		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
123		      <0x0 0x2f100000 0 0x200000>,	// GICR
124		      <0x0 0x2c000000 0 0x2000>,	// GICC
125		      <0x0 0x2c010000 0 0x2000>,	// GICH
126		      <0x0 0x2c02f000 0 0x2000>;	// GICV
127		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
128
129		its: msi-controller@2f020000 {
130			#msi-cells = <1>;
131			compatible = "arm,gic-v3-its";
132			reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
133			msi-controller;
134		};
135	};
136
137	timer {
138		compatible = "arm,armv8-timer";
139		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
140			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
141			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
142			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
143	};
144
145	pmu {
146		compatible = "arm,armv8-pmuv3";
147		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
148	};
149
150	spe-pmu {
151		compatible = "arm,statistical-profiling-extension-v1";
152		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
153	};
154
155	pci: pci@40000000 {
156		#address-cells = <0x3>;
157		#size-cells = <0x2>;
158		#interrupt-cells = <0x1>;
159		compatible = "pci-host-ecam-generic";
160		device_type = "pci";
161		bus-range = <0x0 0x1>;
162		reg = <0x0 0x40000000 0x0 0x10000000>;
163		ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
164		interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
165				<0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
166				<0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
167				<0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
168		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
169		msi-map = <0x0 &its 0x0 0x10000>;
170		iommu-map = <0x0 &smmu 0x0 0x10000>;
171
172		dma-coherent;
173	};
174
175	smmu: iommu@2b400000 {
176		compatible = "arm,smmu-v3";
177		reg = <0x0 0x2b400000 0x0 0x100000>;
178		interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
179			     <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
180			     <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
181			     <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
182		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
183		dma-coherent;
184		#iommu-cells = <1>;
185		msi-parent = <&its 0x10000>;
186	};
187
188	panel {
189		compatible = "arm,rtsm-display", "panel-dpi";
190		port {
191			panel_in: endpoint {
192				remote-endpoint = <&clcd_pads>;
193			};
194		};
195	};
196
197	bus@8000000 {
198		#interrupt-cells = <1>;
199		interrupt-map-mask = <0 0 63>;
200		interrupt-map = <0 0  0 &gic 0 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
201				<0 0  1 &gic 0 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
202				<0 0  2 &gic 0 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
203				<0 0  3 &gic 0 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
204				<0 0  4 &gic 0 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
205				<0 0  5 &gic 0 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
206				<0 0  6 &gic 0 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
207				<0 0  7 &gic 0 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
208				<0 0  8 &gic 0 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
209				<0 0  9 &gic 0 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
210				<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
211				<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
212				<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
213				<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
214				<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
215				<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
216				<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
217				<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
218				<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
219				<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
220				<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
221				<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
222				<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
223				<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
224				<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
225				<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
226				<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
227				<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
228				<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
229				<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
230				<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
231				<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
232				<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
233				<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
234				<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
235				<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
236				<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
237				<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
238				<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
239				<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
240				<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
241				<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
242				<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
243				<0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
244				<0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
245				<0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
246	};
247};
248