1/*
2 * ARM Ltd.
3 *
4 * ARMv8 Foundation model DTS
5 */
6
7/dts-v1/;
8
9/memreserve/ 0x80000000 0x00010000;
10
11/ {
12	model = "Foundation-v8A";
13	compatible = "arm,foundation-aarch64", "arm,vexpress";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	chosen { };
19
20	aliases {
21		serial0 = &v2m_serial0;
22		serial1 = &v2m_serial1;
23		serial2 = &v2m_serial2;
24		serial3 = &v2m_serial3;
25	};
26
27	cpus {
28		#address-cells = <2>;
29		#size-cells = <0>;
30
31		cpu@0 {
32			device_type = "cpu";
33			compatible = "arm,armv8";
34			reg = <0x0 0x0>;
35			enable-method = "spin-table";
36			cpu-release-addr = <0x0 0x8000fff8>;
37			next-level-cache = <&L2_0>;
38		};
39		cpu@1 {
40			device_type = "cpu";
41			compatible = "arm,armv8";
42			reg = <0x0 0x1>;
43			enable-method = "spin-table";
44			cpu-release-addr = <0x0 0x8000fff8>;
45			next-level-cache = <&L2_0>;
46		};
47		cpu@2 {
48			device_type = "cpu";
49			compatible = "arm,armv8";
50			reg = <0x0 0x2>;
51			enable-method = "spin-table";
52			cpu-release-addr = <0x0 0x8000fff8>;
53			next-level-cache = <&L2_0>;
54		};
55		cpu@3 {
56			device_type = "cpu";
57			compatible = "arm,armv8";
58			reg = <0x0 0x3>;
59			enable-method = "spin-table";
60			cpu-release-addr = <0x0 0x8000fff8>;
61			next-level-cache = <&L2_0>;
62		};
63
64		L2_0: l2-cache0 {
65			compatible = "cache";
66		};
67	};
68
69	memory@80000000 {
70		device_type = "memory";
71		reg = <0x00000000 0x80000000 0 0x80000000>,
72		      <0x00000008 0x80000000 0 0x80000000>;
73	};
74
75	timer {
76		compatible = "arm,armv8-timer";
77		interrupts = <1 13 0xf08>,
78			     <1 14 0xf08>,
79			     <1 11 0xf08>,
80			     <1 10 0xf08>;
81		clock-frequency = <100000000>;
82	};
83
84	pmu {
85		compatible = "arm,armv8-pmuv3";
86		interrupts = <0 60 4>,
87			     <0 61 4>,
88			     <0 62 4>,
89			     <0 63 4>;
90	};
91
92	watchdog@2a440000 {
93		compatible = "arm,sbsa-gwdt";
94		reg = <0x0 0x2a440000 0 0x1000>,
95			<0x0 0x2a450000 0 0x1000>;
96		interrupts = <0 27 4>;
97		timeout-sec = <30>;
98	};
99
100	smb@08000000 {
101		compatible = "arm,vexpress,v2m-p1", "simple-bus";
102		arm,v2m-memory-map = "rs1";
103		#address-cells = <2>; /* SMB chipselect number and offset */
104		#size-cells = <1>;
105
106		ranges = <0 0 0 0x08000000 0x04000000>,
107			 <1 0 0 0x14000000 0x04000000>,
108			 <2 0 0 0x18000000 0x04000000>,
109			 <3 0 0 0x1c000000 0x04000000>,
110			 <4 0 0 0x0c000000 0x04000000>,
111			 <5 0 0 0x10000000 0x04000000>;
112
113		#interrupt-cells = <1>;
114		interrupt-map-mask = <0 0 63>;
115		interrupt-map = <0 0  0 &gic 0 0 0  0 4>,
116				<0 0  1 &gic 0 0 0  1 4>,
117				<0 0  2 &gic 0 0 0  2 4>,
118				<0 0  3 &gic 0 0 0  3 4>,
119				<0 0  4 &gic 0 0 0  4 4>,
120				<0 0  5 &gic 0 0 0  5 4>,
121				<0 0  6 &gic 0 0 0  6 4>,
122				<0 0  7 &gic 0 0 0  7 4>,
123				<0 0  8 &gic 0 0 0  8 4>,
124				<0 0  9 &gic 0 0 0  9 4>,
125				<0 0 10 &gic 0 0 0 10 4>,
126				<0 0 11 &gic 0 0 0 11 4>,
127				<0 0 12 &gic 0 0 0 12 4>,
128				<0 0 13 &gic 0 0 0 13 4>,
129				<0 0 14 &gic 0 0 0 14 4>,
130				<0 0 15 &gic 0 0 0 15 4>,
131				<0 0 16 &gic 0 0 0 16 4>,
132				<0 0 17 &gic 0 0 0 17 4>,
133				<0 0 18 &gic 0 0 0 18 4>,
134				<0 0 19 &gic 0 0 0 19 4>,
135				<0 0 20 &gic 0 0 0 20 4>,
136				<0 0 21 &gic 0 0 0 21 4>,
137				<0 0 22 &gic 0 0 0 22 4>,
138				<0 0 23 &gic 0 0 0 23 4>,
139				<0 0 24 &gic 0 0 0 24 4>,
140				<0 0 25 &gic 0 0 0 25 4>,
141				<0 0 26 &gic 0 0 0 26 4>,
142				<0 0 27 &gic 0 0 0 27 4>,
143				<0 0 28 &gic 0 0 0 28 4>,
144				<0 0 29 &gic 0 0 0 29 4>,
145				<0 0 30 &gic 0 0 0 30 4>,
146				<0 0 31 &gic 0 0 0 31 4>,
147				<0 0 32 &gic 0 0 0 32 4>,
148				<0 0 33 &gic 0 0 0 33 4>,
149				<0 0 34 &gic 0 0 0 34 4>,
150				<0 0 35 &gic 0 0 0 35 4>,
151				<0 0 36 &gic 0 0 0 36 4>,
152				<0 0 37 &gic 0 0 0 37 4>,
153				<0 0 38 &gic 0 0 0 38 4>,
154				<0 0 39 &gic 0 0 0 39 4>,
155				<0 0 40 &gic 0 0 0 40 4>,
156				<0 0 41 &gic 0 0 0 41 4>,
157				<0 0 42 &gic 0 0 0 42 4>;
158
159		ethernet@2,02000000 {
160			compatible = "smsc,lan91c111";
161			reg = <2 0x02000000 0x10000>;
162			interrupts = <15>;
163		};
164
165		v2m_clk24mhz: clk24mhz {
166			compatible = "fixed-clock";
167			#clock-cells = <0>;
168			clock-frequency = <24000000>;
169			clock-output-names = "v2m:clk24mhz";
170		};
171
172		v2m_refclk1mhz: refclk1mhz {
173			compatible = "fixed-clock";
174			#clock-cells = <0>;
175			clock-frequency = <1000000>;
176			clock-output-names = "v2m:refclk1mhz";
177		};
178
179		v2m_refclk32khz: refclk32khz {
180			compatible = "fixed-clock";
181			#clock-cells = <0>;
182			clock-frequency = <32768>;
183			clock-output-names = "v2m:refclk32khz";
184		};
185
186		iofpga@3,00000000 {
187			compatible = "simple-bus";
188			#address-cells = <1>;
189			#size-cells = <1>;
190			ranges = <0 3 0 0x200000>;
191
192			v2m_sysreg: sysreg@010000 {
193				compatible = "arm,vexpress-sysreg";
194				reg = <0x010000 0x1000>;
195			};
196
197			v2m_serial0: uart@090000 {
198				compatible = "arm,pl011", "arm,primecell";
199				reg = <0x090000 0x1000>;
200				interrupts = <5>;
201				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
202				clock-names = "uartclk", "apb_pclk";
203			};
204
205			v2m_serial1: uart@0a0000 {
206				compatible = "arm,pl011", "arm,primecell";
207				reg = <0x0a0000 0x1000>;
208				interrupts = <6>;
209				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
210				clock-names = "uartclk", "apb_pclk";
211			};
212
213			v2m_serial2: uart@0b0000 {
214				compatible = "arm,pl011", "arm,primecell";
215				reg = <0x0b0000 0x1000>;
216				interrupts = <7>;
217				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
218				clock-names = "uartclk", "apb_pclk";
219			};
220
221			v2m_serial3: uart@0c0000 {
222				compatible = "arm,pl011", "arm,primecell";
223				reg = <0x0c0000 0x1000>;
224				interrupts = <8>;
225				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
226				clock-names = "uartclk", "apb_pclk";
227			};
228
229			virtio_block@0130000 {
230				compatible = "virtio,mmio";
231				reg = <0x130000 0x200>;
232				interrupts = <42>;
233			};
234		};
235	};
236};
237